FIR_Filter

//Owner:
Abdul Rehman
//Contact:
abdulrehman.ee.010@gmail.com
//Please mention reference if this code is used anywhere
//Assuming 8bit values for the Lab 11 Q8.0 format and coff Q0.4 format
//order must be greater than 2
module FIR_filter#(parameter
obits_m=8,obits_f=0,dbits_m=8,dbits_f=0,coffbits_m=0,coffbits_f=4,order=4)
(output [obits_m+obits_f-1:0] result,
input [dbits_m+dbits_f-1:0] xn,
input [coffbits_m+coffbits_f-1:0] fil_coff,
input set_coff,clk,rst_n);
reg [coffbits_m+coffbits_f-1:0] coff[0:order-1];
reg [dbits_m+dbits_f-1:0]
xd[0:order-1];
wire [obits_m+obits_f-1:0]
ans[0:order-1];
//setting up the string of coff and xns
integer i;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
for(i=1;i<order;i=i+1)begin
xd[i]<=0;
end
for(i=0;i<order;i=i+1)begin
coff[i]<=0;
end
end else begin
xd[0]<=xn;
for(i=1;i<(order);i=i+1)begin
xd[i]<=xd[i-1];
end
if(set_coff)
coff[0]<=fil_coff;
else
coff[0]<=coff[0];
for(i=1;i<(order);i=i+1)begin
if(set_coff)
coff[i]<=coff[i-1];
else
coff[i]<=coff[i];
end
end
end
//Multiplying each xd with coff
genvar k;
generate
for(k=0;k<order;k=k+1)begin:multipliers
Mutiply#(8,0,8,0,coffbits_m,coffbits_f) m1(ans[k],xd[k],coff[k]);
end
endgenerate
//Adding each ans of multiplication combinationally
genvar j;
wire [obits_m+obits_f-1:0]
temp[0:order-2];
generate
assign temp[0]=ans[0]+ans[1];
for(j=1;j<order-1;j=j+1)begin:adders_my
assign temp[j]=temp[j-1]+ans[j+1];
end
endgenerate
//assing result
assign result=temp[order-2];
endmodule

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