IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO.

7, JULY 2014

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Design of Gate-All-Around Silicon MOSFETs

for 6-T SRAM Area Efficiency and Yield
Yi-Bo Liao, Student Member, IEEE, Meng-Hsueh Chiang, Senior Member, IEEE,
Nattapol Damrongplasit, Student Member, IEEE, Wei-Chou Hsu, Member, IEEE,
and Tsu-Jae King Liu, Fellow, IEEE
Abstract Gate-all-around (GAA) MOSFETs relevant for the
11.9-nm CMOS technology node are optimized with device
dimensions following the scale length rule. Variability in transistor performance due to systematic and random variations is
estimated with the aid of TCAD 3-D device simulations, for
these well-tempered GAA structures. The tradeoff between read
stability and write-ability of 6-T static RAM cell designs implemented with GAA MOSFETs with either square or rectangular
nanowire channel regions is then investigated, and a calibrated
transistor IV compact model is used to estimate cell yield. The
results indicate that a rectangular (thin and wide) channel design
achieves the optimal balance between the read yield and write
yield and hence provides for the lowest minimum cell operating
voltage, estimated to be 0.45 V, as well as smaller cell area.
Index Terms 6-T static RAM (SRAM), gate-all-around
(GAA), variability.

I. I NTRODUCTION

DVANCED transistor structures such as the 3-D

tri-gate MOSFET have been adopted at the 22-nm CMOS
technology node [1] because they can better suppress shortchannel effects (SCEs) than the conventional planar bulk
MOSFET structure. The gate-all-around (GAA) MOSFET
structure can provide for superior gate control and hence is
the most promising for gate-length scaling to 10 nm and
below [2]. The channel thinness requirement for adequate
SCE suppression can be relaxed if the channel width is very
narrow [3] but then multiple such nanowire (NW) channels must be connected in parallel or vertically stacked [4]
to achieve high drive current, decreasing the layout area
efficiency or increasing the fabrication process complexity,
respectively. Sensitivity to process-induced variations in NW

Manuscript received July 2, 2013; revised February 25, 2014, April 1, 2014,
and May 5, 2014; accepted May 8, 2014. Date of publication May 29, 2014;
date of current version June 17, 2014. This work was supported in part
by the National Science Council of Taiwan the Ministry of Science and
Technology of Taiwan and in part by the University of California IMPACT+
Research Program. The review of this paper was arranged by Editor
Y.-H. Shih.
Y.-B. Liao and W.-C. Hsu are with the Department of Electrical Engineering,
Institute of Microelectronics, National Cheng Kung University, Tainan 701,
Taiwan.
M.-H. Chiang is with the MS Degree Program on Nano-Integrated-Circuit
Engineering, Department of Electrical Engineering, National Cheng Kung
University, Tainan 701, Taiwan (e-mail: mhchiang@mail.ncku.edu.tw).
N. Damrongplasit and T.-J. K. Liu are with the Department of Electrical Engineering and Computer Sciences, University of California at
Berkeley, Berkeley, CA 94720 USA (e-mail: nattapol@eecs.berkeley.edu;
tking@eecs.berkeley.edu).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2323059

width requires careful design to ensure reliable operation [5].

Gate line-edge roughness (G-LER) and random dopant fluctuation (RDF) effects also contribute substantially to threshold
voltage variation for gate lengths below 20 nm [6].
The impact of device performance variations on 6-T static
RAM (SRAM) cell yield previously has been estimated for
planar bulk MOSFET [7][9] and FinFET [10], [11] technologies at the 22-nm node. In this paper, 6-T SRAM cell yield
estimations are performed for GAA MOSFET technology
relevant for the 11.9-nm node. The design of GAA MOSFETs
is investigated via 3-D TCAD simulation with Fermi-Dirac
statistics, drift-diffusion transport using the Philips unified
mobility model [12], and the density gradient quantization
model [13]. Using a transistor I V compact model calibrated
to the TCAD simulations, it is shown that the tradeoff between
read noise margin and write current for the 6-T SRAM
cell design can be finely tuned using only single-NW GAA
MOSFETs to achieve optimal cell layout area efficiency and
yield.
II. GAA MOSFET D ESIGN
Fig. 2(a) shows a 3-D perspective view and 2-D cross
section of the channel region of the GAA MOSFET design
investigated in this paper. The gate length (L g ) and equivalent
oxide thickness are fixed at 10 and 0.62 nm, respectively, based
on ITRS specifications for the 11.9-nm technology node [14].
The minimum lithographically defined feature size is assumed
to be 10 nm. Raised-source/drain regions are assumed to
be formed by selective epitaxial growth of 15-nm-thick
in situ-doped Si (2 1020 cm3 ) [15]; the source/drain extensions have a Gaussian lateral (1-D) doping profile with peak
concentration at the edge of the thick source/drain regions.
Ohmic contacts (8 109 -cm2) are made to the top surfaces
(15 nm 15 nm) of the thick source/drain regions.
A. Optimization of Channel Region Dimensions
The concept of an electrostatic scale length () was
proposed for both double-gate [16], [17] and GAA [3], [18]
MOSFETs. The scale length must be a few times smaller than
the electrical channel length (L eff ) for a transistor to have good
electrostatic integrity. In this paper, the scale length GAA is
selected to be 3.3 nm, such that drain-induced barrier lowering
(DIBL) is equal to 70 mV/V. The curve in Fig. 1 delineates
the combinations of channel region height (HSi) and width
(WSi ) corresponding to GAA = 3.3 nm. Combinations of
HSi and WSi , which lie below this curve correspond to even

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Fig. 1. GAA MOSFET channel dimensions corresponding to scale length

GAA = 3.3 nm.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 7, JULY 2014

Fig. 3.

Predicted SS in channel width variation.

The design comprising a wide and thin channel achieves the

highest ON-state drive current (ION ) because it has the lowest
parasitic source/drain resistance. This design also is the least
sensitive to lithography- and etch-process-induced variations
in channel width, i.e., a tall and narrow NW design is more
sensitive to channel width variation. Furthermore, ION for a
GAA MOSFET with small HSi can be adjusted linearly by
changing WSi without significantly affecting IOFF and DIBL
[5], [21]. Thus, this GAA MOSFET design is more robust
and versatile. Though the tall and narrow NW device has an
advantage in slightly smaller footprint, it does not seem to be a
preferred option when variation is of concern. Its scale length
becomes the longest among the three cases when accounting
for same width variation, and hence its SCEs are the worst.
As shown in Fig. 3, the tall and narrow NW device shows
most significant SS degradation in width variation.
B. Impact of Random Variations

Fig. 2. (a) 3-D view and channel region cross section of the GAA MOSFET
(not to scale). (b) Simulated IDS VGS characteristics for various designs with
the same scale length, GAA (3.3 nm).

shorter scale length, i.e., superior electrostatic integrity. Note

that the channel region cross section can be either rectangular
or square.
The effective channel length (L eff ) is defined as the distance between the locations where the source/drain doping
level drops to 1019 cm3 [19]. It can be adjusted by tuning
the steepness of the Gaussian source/drain extension doping
profile, to optimize the tradeoff between SCE (increasing with
decreasing L eff ) and parasitic series resistance (increasing with
increasing L eff ) [20]. The maximum ON / OFF current ratio is
achieved for L eff = 13.5 nm
= 4GAA [21]. The OFF-state
leakage current (IOFF ) is set to 100 nA/m at VDS = 0.68 V
by tuning the gate work function (m = 4.43/4.84 eV for
nMOS/pMOS).
Fig. 2(b) shows the simulated IDS VGS characteristics for
various GAA MOSFET designs, all with the same scale length.

Previously, the impacts of RDF and G-LER on the

performance of planar bulk MOSFETs [22], FinFETs [23],
and NW MOSFETs [24] were studied. This paper extends
to GAA MOSFETs with rectangular channel region cross
section. 3-D device simulations with atomistic doping profiles
(Sano model [25]) and rough gate electrode edges (with 10-nm
correlation length and 1-nm rms roughness, following ITRS
specifications for lithography) were performed, following the
methodology described in [26]. Fig. 4 shows the impacts
of RDF and G-LER on ION IOFF , for GAA MOSFETs of
square versus rectangular channel cross section (200 cases
each). Fig. 5 plots the corresponding threshold voltage (Vt )
distributions. Because the two designs have the same scale
length, they exhibit similar effects of random variations. The
standard deviation of Vt variation ( Vt ) due to G-LER is
smaller than that due to RDF, indicating that RDF has more
significant effect on L eff than does G-LER.
RDF does not only influence Vt , but also the effective
channel length (L eff ), which gives another secondary effect
on Vt . However, G-LER has a major impact on the gate
while L eff is nearly unchanged [same as nominal device
(13.5 nm)] following 1-D Gaussian S/D doping profile. Thus,
the Vt |GLER is smaller than Vt |RDF . Gate work function
variation (WFV) results directly in Vt variation and is a

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TABLE I
C OMPARISON OF GAA MOSFET P ERFORMANCE PARAMETERS FOR
C ELL O PERATING V OLTAGE VDD = 0.68 V. C URRENT VALUES A RE
N ORMALIZED TO E FFECTIVE C HANNEL W IDTH ( HSi + WSi ) 2

Fig. 4. Impact of random variations on ION versus IOFF for GAA MOSFETs
of various designs of the same scale length, GAA (3.3 nm).

Fig. 5. Threshold voltage distributions resulting from RDF and G-LER.

(a) p- and (b) n-channel GAA MOSFETs.

consequence of the polycrystalline microstructure of a metallic

gate material whose work function is a function of crystalline
orientation; it is dependent on fabrication process conditions
[27], [28]. The standard deviation of WFV for TiN gate
material is 17 mV [29].
The sources of RDF, G-LER, and WFV are independent.
Hence, the standard deviation of Vt variation due to all sources
can be calculated as

Vt |Total = Vt2 |RDF + Vt2 |GLER + Vt2 |WFV .
Table I compares the performance parameters for GAA
MOSFETs with either a square or rectangular channel region
cross section. The gate WFV is the largest source of Vt
variation. Since the channel region of GAA NW is nominally
undoped, the impacts of RDF and G-LER on Vt are minor.
C. Model Calibration
The analytical macromodel developed in [30] is used herein
to predict 6-T SRAM cell performance and to estimate cell
yield [31]. The macromodel uses a relatively simple analytical
transistor I V model, calibrated to the (TCAD-simulated)

Fig. 6. Comparison of the calibrated analytical transistor I V model against

TCAD simulations, for square-NW GAA MOSFETs.

transistor current values for key bias conditions [(VGS , VDS ) =

(0.34 V, 0.05 V), (0.68 V, 0.05 V), (0.68 V, 0.34 V), (0 V,
0.68 V), (0.34 V, 0.68 V), and (0.68 V, 0.68 V)] in addition
to the linear- and saturation-region values of Vt (Vt,LIN and
Vt,SAT , corresponding to VDS = 0.05 V and VDS = 0.68 V,
respectively). The macromodel also captures the dependences
of IOFF , Vt,LIN and Vt,SAT on NW width (WSi ) and gate
length (L g ), and is calibrated across a reasonable range of
parameter values (3 nm) to ensure accurate SRAM cell yield
estimation. Fig. 6 shows that the calibrated transistor IV
model well matches the TCAD simulations.
III. GAA 6-T SRAM C ELLS
A 6-T SRAM cell comprises 2 pull-up (MPU ), 2 pull-down
(MPD ), and two access/pass-gate (MPG ) transistors, as shown
in Fig. 7. The read noise margin and write-ability of 6-T
SRAM cells implemented with 10-nm L g GAA MOSFETs
are investigated herein using TCAD mixed-mode simulations,
and also using the calibrated macromodel.

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Fig. 7.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 7, JULY 2014

Circuit diagram of a 6-T SRAM cell.

Fig. 10. Impact of cell operating voltage VDD on SNM and IW for various
GAA 6-T SRAM designs. For each curve, VDD ranges from 0.35 to 0.8 V in
50-mV steps.

GAA MOSFETs achieves higher IW due to higher transistor

drive current [Fig. 2(b)].
B. Design Optimization

Fig. 8. Butterfly plots for 6-T SRAM cells implemented with single-NW
GAA MOSFETs. Good agreement in SNM between TCAD (mixed-mode)
simulations and the macromodel is seen.

Fig. 9. Write N-curves for 6-T SRAM cells implemented with single-NW
GAA MOSFETs. Good agreement in IW values between TCAD (mixedmode) simulations and the macromodel is seen.

A. Read Static Noise Margin and Write-Ability Current

Figs. 8 and 9 show the TCAD-simulated and macromodeled
read voltage transfer characteristics (a.k.a. butterfly plots) and
write N-curves, respectively, for 6-T SRAM cells implemented
with either square-NW or rectangular-NW GAA MOSFETs.
From these, the read static noise margin (SNM) and writeability current (IW ) values are extracted. It can be seen that the
macromodel well-predicts SNM and IW . For a similar value
of SNM, the SRAM cell implemented with rectangular-NW

The read stability and write-ability of a 6-T SRAM cell

can be adjusted by changing the relative strengths of the
transistors, i.e., by adjusting their effective channel widths.
To increase SNM, the cell -ratio (WPD /WPG ) should be
increased. To increase IW , the cell -ratio (WPU /WPG ) should
be decreased. Since it is desirable to minimize the cell layout area to maximize storage density, the pull-up transistor
should be minimally sized. In this paper, the pull-up and the
pass-gate transistors are minimally sized with NW width
WSi = 10 nm. Since the drive current of a p-channel MOSFET
is lower than that of an n-channel MOSFET with the same
channel dimensions [Fig. 2(b)] the -ratio is less than 1 as
required for good write ability. To achieve good SNM, the
-ratio should be greater than 1, i.e., the effective channel
width of the pull-down transistors should be greater than
that of the minimally sized pass-gate transistors. For squareNW GAA MOSFETs, this requirement can only be met by
connecting two NW channels in parallel between the source
and drain regions of the pull-down transistors (increasing WSi
would result in substantially degraded electrostatic integrity
and hence is not a viable option). For rectangular-NW GAA
MOSFETs, however, this requirement can be met by increasing WSi to be larger than the minimum size of 10 nm. From
Fig. 1, it can be observed that WSi can be increased to 20 nm
if HSi
= 7 nm, while maintaining good electrostatic integrity
(GAA 3.3 nm).
Fig. 10 shows how both SNM and IW increase with
increasing cell supply voltage (VDD ), for various GAA 6-T
SRAM cell designs. Clearly, SNM improves with increasing
effective channel width of the pull-down devices (WPD ). The
rectangular-NW GAA 6-T SRAM cell design with WPD =
20 nm is advantageous for VDD < 0.6 V.
C. Cell Area Comparison
The 6-T SRAM cell layouts described in [7] and [8]
are scaled herein to be appropriately sized for the 11.9-nm

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TABLE II
L AYOUT D IMENSIONS FOR 11.9- NM N ODE 6-T SRAM C ELL . T HE
H ALF -C ELL L AYOUT I S S HOWN ON THE R IGHT FOR R EFERENCE

Fig. 12. GAA 6-T SRAM cell read (SNM) yield and write (Iw ) yield as a
function of cell operating voltage.

Fig. 11. 6-T SRAM half-cell layouts (not to scale). (a) Square (HSi = 10 nm)
double-NW PD and (b) rectangular (HSi = 7.5 nm) GAA SRAM cell designs.

technology node [14]; Table II lists the cell layout dimensions

alongside the half-cell layout. For minimum cell layout area,
Fig. 11 compares the layouts for the best square-NW and the
best rectangular-NW GAA 6-T SRAM cell designs (Fig. 10).
Because a square-NW GAA MOSFET comprising two
10-nm-wide NWs requires larger layout area (due to the
spacing between NWs) than a rectangular GAA MOSFET
comprising one 20-nm-wide NW, the rectangular GAA 6-T
SRAM cell design with WPD = 20 nm has smaller layout
area.

Fig. 13. Adjustment of the tradeoff between write (IW ) yield and read
(SNM) yield through PG transistor sizing, for a 6-T SRAM cell implemented
with single-NW GAA MOSFETs with HSi = 7.5 nm.
TABLE III
S UMMARY C OMPARISON OF GAA 6-T SRAM C ELL D ESIGNS

IV. GAA 6-T SRAM C ELL Y IELD E STIMATION

In this section, the read and write yields for the best
square-NW and the best rectangular-NW GAA 6-T SRAM
cell designs are estimated. The cell sigma, defined as the
minimum number of standard deviations (for any combination
of variation sources) that can result in a read failure or a
write failure (i.e., SNM or IW less than zero, respectively)
[7], [30], [31], is computed accounting for process-induced
variations in NW width and gate length (assuming Gaussian
distributions with 3 = 10% of nominal value) as well as
random variations in Vt due to RDF, G-LER, and WFV. For
large-capacity SRAM, six-sigma yield for both read and write
operation is required.
Fig. 12 shows the dependences of read yield and write yield
(each measured in number of cell sigmas) on the cell operating
voltage VDD . The minimum cell operating voltage (Vmin ) is

defined as the lowest value of VDD that meets the six-sigma

yield requirement for both read and write operation. For the
optimal square-NW cell design, Vmin is limited by the write
yield, to be 0.5 V; for the optimal rectangular-NW cell design,
the read and write yields are better balanced so that Vmin is
lower, at 0.45 V. (If Vmin is limited by write yield, it can be
improved by increasing IW at the cost of decreasing SNM and
read yield). It should be noted that the tall NW GAA MOSFET
design can provide for improved SNM or Iw , but has lower cell
yield and hence larger Vmin because of its greater sensitivity
to process-induced variations in channel width.
Fig. 13 shows how the tradeoff between the read and write
yield can be fine-tuned by slightly increasing the width of

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 7, JULY 2014

the PG devices, for the rectangular-NW GAA 6-T SRAM cell

design. Note that this has no impact on the cell area, as long as
WPG WPD . The optimal value of WPG is seen to be 10 nm.
Table III provides a summary comparison of the two GAA
6-T SRAM cell designs.
V. C ONCLUSION
GAA MOSFETs are designed for 10-nm gate length
following the scale length rule (Leff = 13.5 nm
= 4GAA ).
Variability in transistor performance due to systematic and
random variations is estimated with the aid of TCAD 3-D
device simulations. A calibrated macromodel is then used to
estimate 6-T SRAM cell yield. The modeled results indicate that a rectangular (thin and wide) NW channel design
achieves the optimal balance between read and write yield and
hence provides for the lowest minimum cell operating voltage
(0.45 V) as well as 28% smaller cell area than the double
square NW channel design.
ACKNOWLEDGMENT
The authors would like to thank Dr. N. Xu for insightful
discussions and the National Center for High-Performance
Computing and National Chip Implementation Center for
technical support.
R EFERENCES
[1] C. Auth et al., A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts
and high density MIM capacitors, in Proc. VLSI Symp., Jun. 2012,
pp. 131132.
[2] M. Li et al., Sub-10 nm gate-all-around CMOS nanowire transistors
on bulk Si substrate, in Proc. IEEE Symp. VLSI Technol., Jun. 2009,
pp. 9495.
[3] S. Bangsaruntip, G. M. Cohen, A. Majumdar, and J. W. Sleight,
Universality of short-channel effects in undoped-body silicon nanowire
MOSFETs, IEEE Electron Device Lett., vol. 31, no. 9, pp. 903905,
Sep. 2010.
[4] T. Ernst et al., Novel 3D integration process for highly scalable
nano-beam stacked-channels GAA (NBG) FinFETs with HfO2 /TiN gate
stack, in Proc. IEEE IEDM, Dec. 2006, pp. 9971000.
[5] Y.-B. Liao, M.-H. Chiang, K. Kim, and W.-C. Hsu, Assessment of
structure variation in silicon nanowire FETs and impact on SRAM,
Microelectron. J., vol. 43, no. 5, pp. 300304, 2012.
[6] A. Asenov, Simulation of statistical variability in nano MOSFETs, in
Proc. IEEE Symp. VLSI Technol., Jun. 2007, pp. 8687.
[7] C. Shin Performance and area scaling benefits of FD-SOI technology
for 6-T SRAM cells at the 22-nm node, IEEE Trans. Electron Devices,
vol. 57, no. 6, pp. 13011309, Jun. 2010.
[8] C. Shin, N. Damrongplasit, X. Sun, Y. Tsukamoto, B. Nikolic, and
T.-J. K. Liu, Performance and yield benefits of quasi-planar bulk CMOS
technology for 6-T SRAM at the 22-nm node, IEEE Trans. Electron
Devices, vol. 58, no. 7, pp. 18461854, Jul. 2011.
[9] N. Damrongplasit et al., Comparative study of uniform versus
supersteep retrograde MOSFET channel doping and implications for
6-T SRAM yield, IEEE Trans. Electron Devices, vol. 60, no. 5,
pp. 17901793, May 2013.
[10] T.-J. K. Liu, C. Shin, M. H. Cho, X. Sun, B. Nikolic, and B.-Y. Nguyen,
SRAM cell design considerations for SOI technology, in Proc. IEEE
Int. SOI Conf., Oct. 2009, pp. 14.
[11] B. Nikolic, C. Shin, M. H. Cho, X. Sun, T.-J. K. Liu, and B.-Y. Nguyen,
SRAM design in fully-depleted SOI technology, in Proc. IEEE ISCAS,
May/Jun. 2010, pp. 17071710.
[12] D. B. M. Klaassen, A unified mobility model for device simulationI.
Model equations and concentration dependence, Solid-State Electron.,
vol. 35, no. 7, pp. 953959, 1992.
[13] Sentaurus Device version G-2012.06, Synopsys, Mountain View, CA,
USA, Jun. 2012.

[14] (2011). International Technology Roadmap for Semiconductors (ITRS)

[Online]. Available: http://public.itrs.net/
[15] A. Hokazono, K. Ohuchi, K. Miyano, I. Mizushima, Y. Tsunashima,
and Y. Toyoshima, Source/drain engineering for sub-100 nm CMOS
using selective epitaxial growth technique, in IEEE IEDM Tech. Dig.,
Dec. 2000, pp. 243246.
[16] R. H. Yan, A. Ourmazd, and K. F. Lee, Scaling the Si MOSFET: From
bulk to SOI to bulk, IEEE Trans. Electron Devices, vol. 39, no. 7,
pp. 17041710, Jul. 1992.
[17] K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, Scaling
theory for double-gate SOI MOSFETs, IEEE Trans. Electron Devices,
vol. 40, no. 12, pp. 23262329, Dec. 1993.
[18] C. P. Auth and J. D. Plummer, Scaling theory for cylindrical, fullydepleted, surrounding-gate MOSFETs, IEEE Electron Device Lett.,
vol. 18, no. 2, pp. 7476, Feb. 1997.
[19] V. Varadarajan, Thin-Body Silicon FET Devices and Technology,
Ph.D. dissertation, Univ. California Berkeley, Berkeley, CA, USA,
2001.
[20] S. Chouksey, J. G. Fossum, A. Behnam, S. Agrawal, and L. Mathew,
Threshold voltage adjustment in nanoscale DG FinFETs via limited
source/drain dopants in the channel, IEEE Trans. Electron Devices,
vol. 56, no. 10, pp. 23482353, Oct. 2009.
[21] Y.-B. Liao, M.-H. Chiang, N. Damrongplasit, T.-J. K. Liu, and
W.-C. Hsu, 6-T SRAM cell design with gate-all-around silicon
nanowire MOSFETs, in Proc. VLSI-TSA Symp., Apr. 2013, pp. 12.
[22] A. Cathignol et al., Quantitative evaluation of statistical variability
sources in a 45-nm technological node LP N-MOSFET, IEEE Electron
Device Lett., vol. 29, no. 6, pp. 609611, Jun. 2008.
[23] V. Vidya, L. Smith, and T.-J. K. Liu, FinFET design for tolerance to
statistical dopant fluctuations, IEEE Trans. Nanotechnol., vol. 8, no. 3,
pp. 375378, May 2009.
[24] A. Martinez, M. Aldegunde, N. Seoane, A. R. Brown, J. R. Barker,
and A. Asenov, Quantum-transport study on the impact of channel
length and cross sections on variability induced by random discrete
dopants in narrow gate-all-around silicon nanowire transistors, IEEE
Trans. Electron Devices, vol. 58, no. 8, pp. 22092217, Aug. 2011.
[25] N. Sano, K. Matsuzawa, M. Mukai, and N. Nakayama, On discrete random dopant modeling in drift-diffusion simulations: Physical meaning
of atomistic dopants, Microelectron. Rel., vol. 42, no. 2, pp. 189199,
2002.
[26] A. Asenov, S. Kaya, and A. R. Brown, Intrinsic parameter fluctuations
in decananometer MOSFETs introduced by gate line edge roughness, IEEE Trans. Electron Devices, vol. 50, no. 5, pp. 12541260,
May 2003.
[27] H. Dadgour, K. Endo, V. De, and K. Banerjee, Modeling and analysis of grain-orientation effects in emerging metal-gate devices and
implications for SRAM reliability, in Proc. IEEE IEDM, Dec. 2008,
pp. 705708.
[28] H. F. Dadgour, K. Endo, V. K. De, and K. Banerjee, Grain-orientation
induced work function variation in nanoscale metal-gate transistors
Part I: Modeling, analysis, and experimental validation, IEEE Trans.
Electron Devices, vol. 57, no. 10, pp. 25042514, Oct. 2010.
[29] X. Wang, B. Cheng, A. R. Brown, C. Millar, and A. Asenov, Statistical
variability in 14-nm node SOI FinFETs and its impact on corresponding
6T-SRAM cell design, in Proc. ESSDERC, 2012, pp. 113116.
[30] A. E. Carlson, Device and circuit techniques for reducing variation in
nanoscale SRAM, Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci.,
Univ. California Berkeley, Berkeley, CA, USA, 2008.
[31] C. Shin, Advanced MOSFET designs and implications for SRAM
scaling, Ph.D. dissertation, Dept. Elect. Eng. Comput. Sci., Univ.
California Berkeley, Berkeley, CA, USA, 2011.

Yi-Bo Liao (S12) received the B.S. and M.S.

degrees in electronics engineering from National
Ilan University, Yilan, Taiwan, in 2006 and 2008,
respectively. He is currently pursuing the Ph.D.
degree with the Institute of Microelectronics and
the Department of Electrical Engineering, National
Cheng Kung University, Tainan, Taiwan.

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2377

Meng-Hsueh
Chiang
(S97M01SM07)
received the B.S. degree in electrical engineering
from National Cheng Kung University, Tainan,
Taiwan, in 1992, and the M.S. and Ph.D. degrees
in electrical and computer engineering from the
University of Florida, Gainesville, FL, USA, in
1995 and 2001, respectively.
He is a Faculty Member of the Department of
Electrical Engineering at National Cheng Kung
University.

Wei-Chou Hsu (M87) received the Ph.D. degree

from National Cheng Kung University, Tainan, Taiwan.
He is with the Department of Electrical Engineering, the Institute of Microelectronics, the Advanced
Optoelectronic Technology Center, and the College
of Electrical Engineering and Computer Science,
National Cheng Kung University.

Nattapol Damrongplasit (S10) received the B.S.

(summa cum laude) degree in electrical engineering
from the University of California at Los Angeles,
Los Angeles, CA, USA. He is currently pursuing
the Ph.D. degree in electrical engineering with the
Department of Electrical Engineering and Computer Sciences, University of California at Berkeley,
Berkeley, CA, USA.

Tsu-Jae King Liu (SM00F07) received the B.S.,

M.S., and Ph.D. degrees in electrical engineering
from Stanford University, Stanford, CA, USA, in
1984, 1986, and 1994, respectively.
She has been with the faculty of the Department
of Electrical Engineering and Computer Sciences,
University of California at Berkeley, Berkeley, CA,
USA, since 1996, where she is currently the Conexant Systems Distinguished Professor of Electrical
Engineering and Computer Sciences.