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LAB 4
Multiplexer Description
Using Truth Table Entry

Truth Table Entry Lab

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Introduction
This lab introduces the Truth Table entry feature of the FPGA Advantage. In this lab you will
describe an 8:1 multiplexer using Truth Table entry. After completing this lab you will have an
understanding of using truth table entry for describing the block such as multiplexer, comb logic etc.
This lab comprises three primary steps:
1. Create a new project
2. Graphically describe the behavior of a multiplexer using truth table entry.
3. Convert the truth table into HDL.
Following each general instruction for a given procedure, you will find accompanying step-by-step
directions and illustrated figures that provide more detail for performing the general instruction. If
you feel confident about a specific instruction, feel free to skip the step-by-step directions and move
on to the next general instruction in the procedure.

Create a new Project

Step 1

Launch the FPGA Advantage HDL Designer and create a new project.

Select Start Programs FPGA Advantage 8.1 PP FPGAdv with PP

Select File New Project, New Project Wizard opens (Figure 1.1)

Enter the following Details and Click Next.

Name of new project

Optional Short Description
Directory
Name for the default working library
Advanced

: multiplexer
: 8:1 multiplexer
: C:/training/labs/lab4
: work
: Unchecked

Figure 1.1: New Project Wizard

View the Project Summary wizard and Click Next.

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C

Create a new truth table entry design using File Creation Wizard.

After Clicking Next in the New Project Wizard, File Creation Wizard will appear (figure 1.2),
Select Create new design Files and Click finish

Figure 1.2: Project Content Wizard

In the Design Content Creation Wizard select Graphic View in Categories, Truth Table in the
File Types and VHDL for language option. (Refer to figure 1.3) and click Next.

Figure 1.3: Design Content Creation Wizard

Enter the following Details in the Design Specification wizard (refer to Fig 1.4) and Click Next

o Library
: work
o Entity Name : multiplexer
o Architecture : rtl

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Figure 1.4: Design Specification

Specify Interface wizard appears, enter the following ports for the design (Figure 1.5) and click
Finish.
Port

Direction

Type

Bounds

data_in

IN

std_logic_vector

(7:0)

sel

IN

std_logic_vector

(2:0)

data_out

OUT

std_logic

Figure 1.5: Specifying Interface

Once you click finish, Truth Table entry window appears.

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Truth Table Entry

Step 2

Delete a column and add more rows to default view of Truth Table Entry window.

Analyze the Default view of Truth Table Entry Wizard (Figure 2.1).

Figure 2.1: Default view of Truth Table Entry Wizard

Since the data_in column is not required, delete the data_in column. To delete the data_in column
right click on it and select delete column option.

Add 5 more ROWS to truth table by right clicking on the truth table and selecting Add Row 5
times. Refer to figure 2.2

Figure 2.2: Adding Rows

Describe the 8:1 multiplexer logic in truth table entry window as shown in figure 2.3.
Sel
000
001
010
011
100
101
Truth Table Entry Lab

Data_out
data_in(0)
data_in(1)
data_in(2)
data_in(3)
data_in(4)
data_in(5)

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110
111

data_in(6)
data_in(7)
X

Figure 2.3: Truth table description of the multiplexer

To enter a value to a cell, double click on it and enter the value. Figure 2.4.

Figure 2.4: Entering a value to a cell

Add the values as shown in the figure 2.3 & complete the truth table. After completion, save the
design. Figure 2.5 shows the completed design.

Figure 2.5: Completed truth table Entry

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Convert Truth Table entry to HDL

Step 3

Convert the truth table entry to HDL and view generated HDL.

Select Table Truth table properties to set the HDL style of Implementation.

It opens the Truth Table properties window, select if as HDL Implementation Style.

Figure 3.1: Truth Table Properties window

To generate the HDL equivalent of the truth table, in the tool bar click Generate button. Refer to
Figure 3.2.

Figure 3.2: Generating HDL

The Generate plug-in checks for the correctness of the truth table and then generates the
equivalent HDL code. If any errors were found, it reports them. (Figure 3.3 Example).

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Figure 3.3: syntax error in truth table entry

Correct the error if any and rerun Generate process.

After completing the Generation process, Generate process shows Generation Process
completed successfully message in Log Window.

After successful generation of HDL code, Click on View Generated HDL option in the HDL
menu.

Figure 3.4: Viewing generated HDL

This opens the generated HDL code in Design Pad as shown in Figure 3.5. Analyze the code and
note the if-else style of implementation. After analyzing close the Design Pad.

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Figure 3.5: Generated code in IF-Else Style

Change to the HDL style to case in the Truth Table Properties window and generate the
HDL.

Launch Truth Table properties and change the HDL Style to CASE and click ok to close the
Truth Table properties window.

Save the Design and Generate the HDL code for the design using Generate plug-in.

View the Generated HDL using View Generated HDL option. This will open the HDL code in
the Design pad. Note that the multiplexer is described in case style.

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Figure 3.6: Case style Implementation of the design

Conclusion
In this demonstration, you completed the major stages of the Graphical Design Entry in HDL
Designer: creating a project, Using Truth table entry, generating the HDL code and controlling the
HDL conversion.
In the next module, you will understand the State Diagram Entry in HDL Designer

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