RFIT2011-IEEE International Symposium on Radio-Frequency Integration Technology, Nov. 30 - Dec.

2, 2011, Beijing, China

900 MHz CMOS RF-to-DC Converter Using a Cross-Coupled

Charge Pump for Energy Harvesting
Kwangrok You1, Hyungchul Kim, Minsu Kim, Youngoo Yang2
1

School of Information and Communication Engineering, SungKyunKwan University, Suwon,

440-746, Republic of Korea
1
dorro112@gmail.com, 2yang09@skku.edu

Abstract This paper presents a CMOS RF-to-DC

converter with a cross-coupled charge pump for energy
harvesting. The proposed RF-to-DC converter consists of a
cross-coupled rectifier and a cross-coupled charge pump. The
charge pump can operate with a non-overlapping clock with
a switching frequency of 25 MHz using a pump capacitance
of 4 pF. The RF-to-DC converter IC was designed and
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of 2.05 V was achieved at an RF input power of -6 dBm with
an input frequency of 900 MHz and the load of 100 K)RU
this condition, the charge pump exhibited a high efficiency of
about 74 %.
Index Terms CMOS RF-to-DC converter, charge pump,
energy harvesting, rectifier, ultra-high frequency (UHF).
Fig. 1. A block diagram of the proposed RF-to-DC converter

I. INTRODUCTION
Batteries have a limited life time and hazardous
chemicals. Finite battery life drives many researchers to
propose new ideas for the wireless systems including
energy harvesting [1]. There are many interesting ways for
energy harvesting from the ambient sources, such as light,
heat, vibration, RF, and so on. Among all, RF signals are
available everywhere as well as every time [2]-[3].
An RF-to-DC converter is very important for the energy
harvesting devices using RF signals. It generates stable
DC power with an appropriate voltage level which is
required by the target devices [4]. Conventional RF-to-DC
converter uses a Dicksons circuit [5]. An RF-to-DC
converter based on Dicksons circuit suffers from
efficiency drop due to the turn-on voltage of the diode.
Especially for the integrated circuit, a MOSFET diode has
to be generally used to design the circuit, because an
additional processing step is required to provide a
Schottky diode which has very low turn-on voltage [6]-[7].
In this paper, a CMOS RF-to-DC converter integrated
circuit is presented for the 900 MHz band. The proposed
RF-to-DC converter has a cross-coupled rectifier based on
MOSFET to convert the RF input signal to a DC voltage.
It also has a high-efficiency cross-coupled charge pump to
boost the low input DC voltage. The cross-coupled
structure has advantages in low reverse leakage current
and low voltage drop across the MOSFET diode.

Fig. 1 shows a block diagram of the proposed RF-to-DC

converter. It has a cross-coupled rectifier and a crosscoupled charge pump. The rectifier operates at the 900
MHz band. The charge pump operates at a very low
frequency of about 25 MHz. The integrated oscillator
generates a non-overlapped clock for the charge pump.
The rectifier is optimized for a load resistance of 10 k
A. Cross-coupled rectifier
RF+
C1N

N1

P1

N1N

P1N Vout

N2

P2

N2N

P2N

Cs
C2

C2N

RF-

Fig. 2. A schematic diagram of an N-stage cross-coupled

rectifier.

Fig. 2 shows an N-stages cross-coupled rectifier [8]. A

voltage generated by a single-stage rectifier is not enough
to operate the clock generator and the charge pump.
Therefore, the rectifier should be designed more than twostages. A differential RF signal is applied to the input of

II. CIRCUIT DESIGN

978-1-4577-0520-5/11/$26.00 2011 IEEE

C1

149

clock signal with a short dead time. For the bias voltage of
0.8 V, the clock generator generates a non-overlapping
clock with a frequency of 25 MHz.

Fig. 3. Measured output voltages of the two- and four-stage

rectifiers.

the rectifier. The gates of the NMOSFETs and the

PMOSFETs are connected each other. When the node A
has a positive signal swing, N1 and P2 are turned on,
while N2 and P1 are turned off. The voltage of the first
stage is nearly doubled by the peak voltage of the RF
signal [9]-[11].
To maximize the RF-to-DC conversion efficiency, the
aspect ratio between NMOS and PMOS transistors should
be optimized. Channel widths for the NMOS and PMOS
transistors were selected to be 30  and 42 ,
respectively. Channel length of 0.13  for both
transistors is selected. Flying capacitors of 0.7 pF were
selected for the optimized performance.
Fig. 3 shows the measured output voltages of the two- and
four-stage rectifiers according to the RF input power with
a load resistance of 10 k. The output voltage of the twostage rectifier is larger than that of the four-stage rectifier
at an RF input power level less than -8 dBm. The fourstage rectifier outperforms and generates more than 0.8 V
at the input power of higher than -6 dBm.

Fig. 4. A schematic diagram of the charge pump circuit: (a)

cross-coupled doubler, (b) clock generator.

B. Charge pump
Fig. 4 shows the cross-coupled charge pump, which is
composed of clock generator and cross-coupled doubler.
Typical Dicksons charge pump has limited performance
due to turn-on voltage of the MOSFET-based diode and
reverse charge sharing. However, the cross-coupled
charge pump has better efficiency due to a crosscompensation of the threshold voltage. Fig. 4(a) shows a
two-stage gate cross-coupled doubler. Fig. 4(b) shows a
clock generator using an inverter chain. In the charge
pump design, switching frequency, load condition, flying
capacitor, channel width of the transistors, and dead time
of a non-overlapping clock should be carefully considered
[12].
Fig. 5 shows the simulated clock frequency according to
the bias voltage. The clock generates non-overlapping

Fig. 5. The simulated clock frequency according to the bias

voltage

Fig. 6 shows the simulated and measured PCE

according to the input DC voltage. The measurement was
carried out with a load resistance of 100
k 

150

integrated charge pump has a good efficiency which is

more than 60 % at input voltages of more than 0.6 V. The
implemented charge pump exhibited a very high peak
PCE of 74 % at an input voltage of 0.8 V.

Fig. 8. The measured output voltages of the RF-to-DC

converters based on the two-stage and four-stage rectifiers.

Fig. 6. The simulated and measured performances of the

implemented charge pump.

III. EXPERIMENTAL RESULT

Fig. 7 shows a photograph of the fabricated RF-to-DC
converter IC whose size is 400x512 2. The chip was
designed and fabricated using Dongbus 0.13 
 
process. An RF input signal from the signal generator
having a frequency of 900 MHz is applied to the proposed
RF-to-DC converter IC via a transformer for differential
signal excitation. Then, the output voltage was measured
through an oscilloscope.
Fig. 8 shows the measured output voltages of the RF-toDC converter IC with two-stage and four-stage rectifiers
with a load resistance of 100 kThe RF-to-DC converter
with a four-stage rectifier has better performance at an
input power level of more than -7 dBm.

Fig. 9. The measured output DC voltages as a parameter of the

load resistances.

Fig. 9 shows the measured output voltage as a

parameter of the load resistances for the RF-to-DC
converter with a four-stage rectifier. With a load
resistance of 100 k       -6 dBm,
PCEs of the RF-to-DC converter and the charge pump
are 24 and 74 %, respectively. The output voltage for this
condition was as high as 2.05 V.
IV. CONCLUSION
In this paper, an RF-to-DC converter using a charge
pump for RF energy harvesting is presented for the 900
MHz band. It consists of a cross-coupled rectifier and a
cross-coupled charge pump with a clock generator which
generates non-overlapping anti-phased clock signal. The
voltage drop and reverse leakage current of the transistor
is minimized using the cross-coupled circuit configuration.
A high output voltage is achieved using a charge pump
which operates with a non-overlapping clock whose
frequency is about 25 MHz. The implemented RF-to-DC
converter exhibited an output voltage of as high as 2.05 V

Fig. 7. A photograph of the fabricated RF-to-DC converter IC.

151

at an RF input power of -6 dBm with a load resistance of

100 k. This CMOS RF-to-DC converter can be applied
to an RF energy harvesting systems.

ACKNOWLEDGEMENT
The chips were design with Cadence and fabricated
Through the IC Design Education Center.

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