Escolar Documentos
Profissional Documentos
Cultura Documentos
iii
iv
ACKNOWLEDGEMENT
I would like to take this opportunity to thank various people who have
provided much assistance and invaluable information to make this project a success.
First of all, I would like to take this opportunity to express my deepest gratitude to
my supervisor of this project, Associate Professor Dr. Zainal bin Salam for his
valuable guidance and generous encouragement throughout the project duration. His
patience in understanding my tasks and problems has brought light to the
development of this project.
I also wish to express my gratitude to the members of academic and technical
staff of Power Electronics and Drives Group, Department of Energy Conversion,
Faculty of Electrical Engineering, Universiti Teknologi Malaysia for the discussions
and technical assistances. Not forgetting my friends and the graduated seniors who
have encouraged and assisted me in needing times.
Last but not least, my utmost thanks go to my beloved mother and Chai Ling
for their unimaginable love, encouragement and support.
ABSTRACT
The past several years have seen a rapid increase of power electronics-based
loads connected to the distribution system. These types of loads draw nonsinusoidal
current from the mains, degrading the power quality by causing harmonic distortion.
This thesis proposes a single-phase hybrid active power filter with photovoltaic
application.
parallel with a shunt active power filter and a DC source that represents the
photovoltaic array. The uniqueness of the proposed topology is the fact that it
improves the harmonic filtering performance of a basic shunt active power filter, as
well as simultaneously supplies the power from the photovoltaic array to the load.
The compensation current reference for the proposed topology is obtained by using
the extension instantaneous reactive-power theorem. This theorem simplifies the
equations for the current reference estimation, thus leading to a more efficient
implementation in digital signal processor. To generate the compensation current
that follows the current reference, the fixed-band hysteresis current control method is
adopted. This work describes the design of circuit topology, control system, highpass filter and compensation current reference estimation. The system is verified by
simulation using MATLAB/Simulink simulation package. To validate the result, a
500 VA laboratory prototype is constructed. It is based on the dSPACE DS1104
digital signal processor.
reduces the total harmonic distortion of the source current from 130.2 % to 19.6 %.
Furthermore, it is demonstrated that the system can also supply active power to the
load.
vii
TABLE OF CONTENTS
CHAPTER
TITLE
TITLE PAGE
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENT
iv
ABSTRACT
ABSTRAK
vi
TABLE OF CONTENTS
vii
LIST OF TABLES
xii
LIST OF FIGURES
xiii
LIST OF SYMBOLS
xviii
LIST OF ABBREVIATIONS
xxiii
LIST OF APPENDICES
PAGE
xxv
INTRODUCTION
1.1
Overview
1.2
Objective of Research
1.3
Methodology of Research
1.4
Thesis Organisation
LITERATURE REVIEW
2.1
Introduction
2.2
viii
2.2.1
2.2.2
2.3
10
2.3.1
11
12
14
16
18
19
2.4.2
20
2.5
2.4
22
23
2.5.1
24
2.5.2
Techniques
24
25
26
27
2.5.2.3 Synchronous-Detection
Theorem
28
2.7
29
29
30
2.6.1
30
2.6.2
32
Summary
33
ix
3
35
3.1
Introduction
35
3.2
3.3
3.4
APF
36
38
3.3.1
38
40
3.3.3
41
Interfacing Inductor
42
43
3.4.1
43
3.4.2
45
47
3.4.4
49
3.4.5
51
3.5
53
3.6
Summary
57
58
4.1
Introduction
58
4.2
59
4.2.1
Distribution Source
59
4.2.2
Nonlinear Load
60
4.2.3
61
4.2.4
63
4.2.5
66
67
70
x
4.2.5.3 DC-Bus Voltage Controller
and PV Current Estimator
72
73
4.3
74
4.4
Summary
75
76
5.1
Introduction
76
5.2
5.3
5.4
5.5
5.6
5.7
Set-Up
76
79
5.3.1
Nonlinear Load
80
5.3.2
81
81
82
83
5.3.3
Gate-Driver Circuit
83
5.3.4
84
85
5.4.1
85
86
87
88
88
89
Control Software
91
91
92
92
93
Summary
96
xi
6
97
6.1
Introduction
97
6.2
98
6.3
99
6.4
101
6.5
104
6.6
6.7
107
111
6.8
115
6.9
116
6.10
Summary
121
122
7.1
Conclusions
122
7.2
123
REFERENCES
125
PUBLICATIONS
135
APPENDICES A K
136 214
xii
LIST OF TABLES
TABLE NO.
TITLE
PAGE
5.1
80
5.2
81
5.3
82
5.4
85
5.5
87
6.1
121
xiii
LIST OF FIGURES
FIGURE NO.
TITLE
PAGE
1.1
2.1
2.2
10
11
2.4
13
2.5
14
2.6
15
2.7
16
2.8
17
2.9
18
19
2.11
20
2.12
21
2.13
22
2.14
24
2.3
2.10
xiv
2.15
31
2.16
31
2.17
32
2.18
33
3.1
36
37
3.3
39
3.4
40
3.5
41
3.6
44
3.7
48
3.8
49
3.9
52
55
3.11
55
3.12
56
59
4.2
60
4.3
61
4.4
62
4.5
63
4.6
65
3.2
3.10
4.1
xv
4.7
66
4.8
67
4.9
68
4.10
68
4.11
70
72
74
74
77
5.2
78
5.3
79
82
5.5
DC-bus capacitor
83
5.6
84
5.7
86
87
5.9
88
5.10
89
4.12
4.13
4.14
5.1
5.4
5.8
xvi
5.11
90
5.12
92
5.13
94
5.14
94
5.15
95
6.1
98
99
100
100
101
102
103
104
6.9
105
6.10
106
107
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.11
xvii
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
108
109
110
111
113
114
115
116
117
118
119
120
xviii
LIST OF SYMBOLS
Constant of H 1( z )
a LPF 1 , a LPF 2
Coefficients of G LPF (z )
Gain coefficient of Z hp (s )
Constant of H 2( z )
Capacitor
C 0 , C1
Coefficients of z
Cd
DC Smoothing capacitor
Cf
DC-bus capacitor
C hp
ECf
ECf ,ref
f0
fc
f c1
f c2
f LPF
fr
fs
f s1
f s2
G LPF ( s )
G LPF
Coefficient of G LPF (z )
xix
GD1
GD2
H ( s)
H ( z)
H 1( z )
H 2( z )
H cds ( s )
H max
I Cf
if
Compensation current
if,f
i f ,h
i f ,ref
i f ,ref 1
i f ,ref 2
ihp
I hp
ihp , p
ihp ,q
ihysteresis
iL
Load current
IL
i L'
iL, f
i L,h
i L,q
xx
inoise
Noise current
i PV
PV current
I PV
Amplitude of PV current
is
Source current
is , f
is ,h
i sw
KI
Kp
Inductor
Lf
Lhp
Ls
Source inductor
Lsmooth
AC smoothing inductor
Mh
~
p
pL
PPV
q~
q hp
qL
Resistor
xxi
RB
Bleed resistor
Rhp
RL
Load resistor
s 0 , s1
Poles of H (s )
Sn
sin(t )
Reference sinewave
sin(t 90 o ) -
Ts
Tsw
VCf
DC-bus voltage
vf
Compensation voltage
v f ,ref
vs
Source voltage
Vs
v s'
vs, f
v s ,h
vu
Distribution voltage
Damped frequency
Pole frequency of Z hp (s )
z 0 , z1
Poles of H (z )
z 1
Unit delay
xxii
Z eq
Zf
Z hp (s)
Zs
Source impedance
Z s (s )
Z s, f
Z s ,h
ECf
I L
I sw, p p
VCf
Characteristic equation of H (z )
fd (z )
in (z )
Damping factor
Damping ratio
xxiii
LIST OF ABBREVIATIONS
AC
Alternating current
ADC
Analogue-to-digital converter
APF
ASD
CPU
DAC
Digital-to-analogue converter
DC
Direct current
DCO
Digitally-controlled oscillator
DSP
EMI
Electromagnetic interference
ESL
ESR
FFT
HPF
High-pass filter
I/O
Input/output
IGBT
LPF
Low-pass filter
MOSFET
p-q
Instantaneous reactive-power
PCC
PCI
PI
Proportional-integral controller
PLL
Phase-lock loop
PQ
Power quality
PV
Photovoltaic
PWM
xxiv
rms
Root-mean-square
RE
Renewable energy
RTI
Real-time interface
RTLib
Real-time library
RTW
Real-time workshop
THD
THD12.5 kHz
VSI
xxv
LIST OF APPENDICES
APPENDIX
TITLE
PAGE
136
139
147
150
153
158
169
171
195
202
209
CHAPTER 1
INTRODUCTION
1.1
Overview
The power quality (PQ) problems in power distribution systems are not new,
but only recently the effects of these problems have gained public awareness.
Advances in semiconductor device technology have fuelled a revolution in power
electronics over the past decade, and there are indications that this trend will
continue [1].
motor drives (ASDs), electronic power supplies, direct current (DC) motor drives,
battery chargers, electronic ballasts are responsible for the rise in related PQ
problems [2]-[4]. These nonlinear loads are constructed by nonlinear devices, in
which the current is not proportional to the applied voltage. A simple circuit as
shown in Figure 1.1 illustrates the concept of current distortion. In this case, a
sinusoidal voltage is applied to a simple nonlinear resistor in which the voltage and
current vary according to the curve shown. While the voltage is perfectly sinusoidal,
the resulting current is distorted.
i(t)
V
I
v(t)
Figure 1.1
Nonlinear Resistor
2
Nonlinear loads appear to be prime sources of harmonic distortion in a power
distribution system. Harmonic currents produced by nonlinear loads are injected
back into power distribution systems through the point of common coupling (PCC).
These harmonic currents can interact adversely with a wide range of power system
equipment, most notably capacitors, transformers, and motors, causing additional
losses, overheating, and overloading [2]-[4].
There are set of conventional solutions to the harmonic distortion problems
which have existed for a long time. The passive filtering is the simplest conventional
solution to mitigate the harmonic distortion [5]-[7].
conventional solutions that use passive elements do not always respond correctly to
the dynamics of the power distribution systems [8]. Over the years, these passive
filters have developed to high level of sophistication. Some even tuned to bypass
specific harmonic frequencies. However, the use of passive elements at high power
level makes the filter heavy and bulky. Moreover, the passive filters are known to
cause resonance, thus affecting the stability of the power distribution systems [9]. As
the regulatory requirements become more stringent, the passive filters might not be
able to meet future revisions of a particular Standard.
Remarkable progress in power electronics had spurred interest in active
power filter (APF) for harmonic distortion mitigation [10]-[15]. The basic principle
of APF is to utilise power electronics technologies to produce currents components
that cancel the harmonic currents from the nonlinear loads [10]. Previously, majority
of controllers developed for APF are based on analogue circuits [11], [12]. As a
result, the APF is inherently subjected to signal drift. Digital controller using digital
signal processor (DSP) or microprocessor is preferable, primarily due to its
flexibility and immunity to noise signals [13]-[15]. However it is known that using
digital methods, the high order harmonics are not filtered effectively. This is due to
the hardware limitation of sampling rate in real-time application [15]. Moreover, the
utilisation of fast switching transistors (i.e. IGBT) in APF application causes
switching frequency noise to appear in the compensated source current.
This
3
The idea of hybrid APF has been proposed by several researchers [16]-[18].
In this scheme, a low cost passive high-pass filter (HPF) is used in addition to the
conventional APF. The harmonics filtering task is divided between the two filters.
The APF cancels the lower order harmonics, while the HPF filters the higher order
harmonics. The main objective of hybrid APF, therefore is to improve the filtering
performance of high-order harmonics while providing a cost-effective low order
harmonics mitigation.
Recently, there is an increasing concern about the environment. The need to
generate pollution-free energy has triggered considerable effort toward renewable
energy (RE). RE sources such as sunlight, wind, flowing water and biomass offer
the promise of clean and abundant energy [19]-[21]. They do not generate any
greenhouse gases and are inexhaustible [22]. Solar energy, in particular, is especially
attractive in a sunshine country like Malaysia. This energy is in DC form from
photovoltaic (PV) arrays. It is converted into a more convenient alternating current
(AC) power through an inverter system. Efforts have been made to combine the APF
with PV array [23]-[25]. However, it appears that no attempt has been made to
combine a hybrid APF with PV array.
1.2
Objective of Research
The objective of the research is two-fold: (1) to propose a new variation of
hybrid APF topology with PV application. (2) to propose a simple current reference
estimation method for the proposed topology.
To achieve the first objective, this research proposes a hybrid APF topology
for a single-phase system, connected to a DC source that represents the PV array.
The topology is unique because it effectively filters harmonic currents of low and
high frequencies to obtain sinusoidal source current. Furthermore, it simultaneously
supplies the power from the PV array to the load.
4
For the second objective, this research proposes the application of the
extension instantaneous reactive-power (p-q) theorem to estimate the compensation
current reference. Although the estimation of current reference based on extension
p-q theorem is not new [24]-[26], this approach has not yet being applied to a singlephase hybrid APF system involving passive HPF, shunt APF and a PV array. Using
the extension p-q theorem, the resulting equations for the current reference is simpler
compared with the conventional p-q theorem presented in [27]. This will lead to
more efficient digital controller implementation using DSP.
1.3
Methodology of Research
In the elaboration of the research, a harmonic analysis of source current
distortion has been carried out. It has featured a nonlinear full-bridge diode rectifier
with DC smoothing capacitor and resistive load as a harmonic currents source. The
time domain simulation is performed using MATLAB/Simulink simulation package.
Afterwards, an extensive computer simulation involving the power circuit of the
shunt APF, passive HPF, a DC source that represents the PV array, current reference
estimation based on extension p-q theorem, phase-lock loop (PLL) circuit and fixedband hysteresis current controller is carried out.
Once satisfactory simulation results are obtained, the proposed topology is
tested in the laboratory with an experimental prototype. The prototype is designed to
compensate the distorted current produced by nonlinear load, as well as
simultaneously supplies the power from the PV array to the load. The proposed
algorithm and control system are implemented using a dSPACE DS1104 DSP
controller board.
Although the original work is intended to include the PV array, the
experimental set-up using PV array is not possible due to facility and time constraints.
However, the PV array can be adequately replaced with a DC source. This is
because the PV array is fundamentally a DC source that produces electricity in DC
form.
5
Finally, a harmonic analysis is carried out to validate the filtering
performance of the proposed hybrid APF in comparison to a basic shunt APF. The
experimental results are analyzed and compared with the results obtained from the
computer simulation.
1.4
Thesis Organisation
This thesis consists of this introductory chapter and six other chapters
arranged as follows:
Chapter 2 covers the literature review and a brief discussion of harmonic
distortion problems, conventional mitigation methods using passive filters and
improved mitigation methods using APF approaches. The efforts in combining the
PV array with the APF are discussed briefly. Different types of compensation
reference signal estimation techniques suitable for APF applications are reviewed. A
brief overview of the control strategies for APF is also provided in this chapter.
Chapter 3 presents the proposed hybrid APF topology.
This chapter
elucidates the topology, operating principles and control of the proposed hybrid APF
and illustrates how this system can be used to supply the PV power to the load.
Emphasis is given to a discussion on the design consideration of the passive HPF.
Chapter 4 concerns the system level simulation using MATLAB/Simulink.
The computer simulation design is described in detail.
Chapter 5 describes the design and construction of the experimental
prototype to validate the proposed hybrid APF.
hardware components is provided.
6
Chapter 6 provides the simulation and experimental results. Comparison
between the simulation and experimental results is discussed in detail. A harmonic
analysis is carried out to evaluate the filtering performance of the proposed hybrid
APF in comparison to a basic shunt APF.
Chapter 7 summarises the research undertaken and highlights the
contribution of this thesis. It offers recommendations for further research.
CHAPTER 2
LITERATURE REVIEW
2.1
Introduction
This chapter reviews the development of active power filter (APF)
The conventional
harmonic mitigation approaches using passive filters are presented first, followed by
the improved mitigation methods using APF techniques. The efforts in combining
the photovoltaic (PV) system with the APF are discussed briefly.
In addition,
2.2
However, certain types of loads produce currents and voltages with frequencies that
are integer multiples of the 50 or 60 Hz fundamental frequency. These frequencies
components are a form of electrical pollution known as harmonic distortion.
Harmonic distortion has sparked research that has led to the present-day
understanding of PQ problems [2]-[4], [28]-[30]. In this section, the concept of
harmonic distortion is introduced and its impacts on electric PQ are discussed.
8
2.2.1
one of the electric PQ issues that received much attention is the harmonic distortion.
These nonlinear loads control the flow of power by drawing currents only during
certain intervals of the 50/60 Hz period. Thus, the current drawn by the nonlinear
load is nonsinusoidal and appear chopped or flattened.
Figure 2.1 illustrates that any periodic, distorted waveform can be expressed
as a sum of pure sinusoids. The sum of sinusoids is referred to as a Fourier series,
named after the great mathematician who discovered the concept. The Fourier
analysis permits a periodic distorted waveform to be decomposed into an infinite
series containing DC component, fundamental component (50/60 Hz for power
systems) and its integer multiples called the harmonic components. The harmonic
number (h) usually specifies a harmonic component, which is the ratio of its
frequency to the fundamental frequency [4].
50 Hz
(h = 1)
+
150 Hz
(h = 3)
+
250 Hz
(h = 5)
+
.
.
.
.
Figure 2.1
9
hmax
THD =
M
h >1
M1
2
h
100% ,
(2.1)
2.2.2
harmonic currents source [3], [4]. As Figure 2.2 shows, voltage distortion is the
result of distorted currents passing through the linear, series impedance of power
distribution system. Although the source bus is a pure sinusoid, there is a nonlinear
load that draws a distorted current. The harmonic currents passing through the
impedance of the system cause a voltage drop for each harmonic. This results in
harmonic voltages appearing at the PCC. The amount of voltage distortion depends
on the source impedance and the current.
Harmonics have a number of undesirable effects on electric PQ. These falls
into two basic categories: short-term and long-term. Short-term effects are usually
the most noticeable and are related to excessive voltage distortion. On the other hand,
long-term effects often go undetected and are usually related to increased resistive
losses or voltage stresses [28]. In addition, the harmonic currents produced by
nonlinear loads can interact adversely with a wide range of power system equipment,
most notably capacitors, transformers, and motors, causing additional losses,
overheating, and overloading. These harmonic currents can also cause interferences
with telecommunication lines and errors in metering devices [2]-[4], [30], [31].
10
Distorted Voltage
+
(Voltage Drop)
_
PCC
Pure
Sinusoid
Figure 2.2
Distorted Load
Current
Nonlinear
Load
2.3
Passive filter.
(2)
(3)
11
2.3.1
long time. The passive filtering is the simplest conventional solution to mitigate the
harmonic distortion [4]-[8], [34]. Passive filters are inductance, capacitance, and
resistance elements configured and tuned to control harmonics. Figure 2.3 shows
common types of passive filters and their configurations.
Load
Load
R
Load
Load
C
C
Single-tuned
Figure 2.3
1st-order
High-pass
2nd-order
High-pass
3rd-order
High-pass
The single-tuned notch filter is the most common and economical type of
passive filter [4], [5], [7]. The notch filter is connected in shunt with the power
distribution system and is series-tuned to present low impedance to a particular
harmonic current. Thus, harmonic currents are diverted from their normal flow path
through the filter.
Another popular type of passive filter is the high-pass filter (HPF) [4], [6]. A
HPF will allow a large percentage of all harmonics above its corner frequency to
pass through. HPF typically takes on one of the three forms, as shown in Figure 2.3.
The first-order, which is characterised by large power losses at fundamental
frequency, is rarely used. The second-order HPF is the simplest to apply while
providing good filtering action and reduced fundamental frequency losses [8]. The
filtering performance of the third-order HPF is superior to that of the second-order
HPF. However, it is found that the third-order HPF is not commonly used for lowvoltage or medium-voltage applications since the economic, complexity, and
reliability factors do not justify them [7].
12
Although simple and least expensive, the passive filter inherits several
shortcomings. The filter components are very bulky because the harmonics that need
to be suppressed are usually of the low order [4], [8]. Furthermore the compensation
characteristics of these filters are influenced by the source impedance. As such, the
filter design is heavily dependent on the power system in which it is connected to [7].
The passive filter is also known to cause resonance, thus affecting the stability of the
power distribution systems [8], [9], [34].
Frequency variation of the power distribution system and tolerances in
components values affect the filtering characteristics. The size of the components
become impractical if the frequency variation is large [8], [9]. As the regulatory
requirements become more stringent, the passive filters might not be able to meet
future revisions of a particular Standard. This may required a retrofit of new filters.
2.3.2
harmonic distortion mitigation [1], [9], [10], [34], [35]. The basic principle of APF
is to utilise power electronics technologies to produce specific currents components
that cancel the harmonic currents components caused by the nonlinear load. Figure
2.4 shows the components of a typical APF system and their connections. The
information regarding the harmonic currents and other system variables are passed to
the compensation current/voltage reference signal estimator.
The compensation
reference signal from the estimator drives the overall system controller. This in turn
provides the control for the gating signal generator. The output of the gating signal
generator controls the power circuit via a suitable interface. Finally, the power
circuit in the generalised block diagram can be connected in parallel, series or
parallel/series configurations depending on the interfacing inductor/transformer used.
13
supply
interfacing
inductor/
transformer
switching
pattern
nonlinear Load
power circuit
system variables
detection
interface
gating signals
generator
compensated
variables
control
effort
overall system
controller
Figure 2.4
reference
signal
reference signal
estimator
APFs have a number of advantages over the passive filters. First of all, they
can suppress not only the supply current harmonics, but also the reactive currents.
Moreover, unlike passive filters, they do not cause harmful resonances with the
power distribution systems. Consequently, the APFs performances are independent
of the power distribution system properties [9], [34].
On the other hand, APFs have some drawbacks.
Active filtering is a
relatively new technology, practically less than four decades old. There is still a
need for further research and development to make this technology well established.
An unfavourable but inseparable feature of APF is the necessity of fast switching of
high currents in the power circuit of the APF. This results in a high frequency noise
that may cause an electromagnetic interference (EMI) in the power distribution
systems [34].
APF can be connected in several power circuit configurations as illustrated in
the block diagram shown in Figure 2.5. In general, they are divided into three main
categories, namely shunt APF, series APF and hybrid APF.
14
shunt APF
current-source
inverter
series APF
voltage-source
inverter
Note:
APF: Active power filter,
Figure 2.5
shunt APF
+
series APF
hybrid APF
series APF
+
shunt PF
shunt APF
+
shunt PF
APF in series
with
shunt PF
connections
current waveform ( i f ), using the VSI switches. The shape of compensation current
is obtained by measuring the load current ( i L ) and subtracting it from a sinusoidal
reference. The aim of shunt APF is to obtain a sinusoidal source current ( i s ) using
the relationship: is = i L i f .
15
AC Source
is
iL
Nonlinear
Load
Lf
if
+
-
Cf
VSI
Figure 2.6
Suppose the nonlinear load current can be written as the sum of the
fundamental current component ( i L , f ) and the current harmonics ( i L ,h ) according to
i L = i L , f + i L ,h
(2.2)
i f = i L ,h
(2.3)
is = i L i f = i L , f
(2.4)
which only contains the fundamental component of the nonlinear load current and
thus free from harmonics. Figure 2.7 shows the ideal source current when the shunt
APF performs harmonic filtering of a diode rectifier. The injected shunt APF current
completely cancels the current harmonics from the nonlinear load, resulting in a
harmonic free source current.
From the nonlinear load current point of view, the shunt APF can be regarded
as a varying shunt impedance. The impedance is zero, or at least small, for the
harmonic frequencies and infinite in terms of the fundamental frequency. As a result,
reduction in the voltage distortion occurs because the harmonic currents flowing
16
through the source impedance are reduced. Shunt APFs have the advantage of
carrying only the compensation current plus a small amount of active fundamental
current supplied to compensate for system losses [10], [35]. It can also contribute to
reactive power compensation. Moreover, it is also possible to connect several shunt
APFs in parallel to cater for higher currents, which makes this type of circuit suitable
for a wide range of power ratings [34].
iL
1
0
-1
if
1
0
-1
is
1
0
-1
20
Figure 2.7
40
60
t [ms]
controlled source, thus the principle configuration of series APF is similar to shunt
APF, except that the interfacing inductor of shunt APF is replaced with the
interfacing transformer.
The operation principle of series APF is based on isolation of the harmonics
in between the nonlinear load and the source. This is obtained by the injection of
harmonic voltages ( v f ) across the interfacing transformer. The injected harmonic
voltages are added/subtracted, to/from the source voltage to maintain a pure
sinusoidal voltage waveform across the nonlinear load. The series APF can be
thought of as a harmonic isolator as shown in Figure 2.9. It is controlled in such a
17
way that it presents zero impedance for the fundamental component, but appears as a
resistor with high impedance for harmonic frequencies components. That is, no
current harmonics can flow from nonlinear load to source, and vice versa.
AC Source
is
iL
vf
Nonlinear
Load
+
-
Cf
VSI
Figure 2.8
is
vf
iL
if
Zs
+
-
Zf
vs
is,f
Zeq=0
iL,f
if,f
Zs,f
(a)
Figure 2.9
Zf
vs,f
is,h
Zeq=
if,h
Zs,h
+
vs,h
-
(b)
iL,h
Zf
(c)
series APF, (b) fundamental equivalent circuit, and (c) harmonic equivalent circuit
Series APFs are less common than their rival, i.e. the shunt APF [1], [10].
This is because they have to handle high load currents. The resulting high capacity
of load currents will increases their current rating considerably compared with shunt
APF, especially in the secondary side of the interfacing transformer. This will
increase the I 2 R losses [10]. However, the main advantage of series APFs over
shunt one is that they are ideal for voltage harmonics elimination [1]. It provides the
load with a pure sinusoidal waveform, which is important for voltage sensitive
devices (such as power system protection devices). With this feature, series APF is
suitable for improving the quality of the distribution source voltage.
18
2.3.2.3 Hybrid Active Power Filter
Previously, majority of the controllers developed for APF are based on
analogue circuits [9], [11], [12], [36]-[38]. As a result, the APF performance is
inherently subjected to signal drift [15].
microcontrollers are preferable, primarily due to its flexibility and immunity to noise
[13]-[15], [39], [40]. However it is known that using digital methods, the high-order
harmonics are not filtered effectively. This is due to the hardware limitation of
sampling rate in real-time application [15].
19
frequency and high impedance (ideally open circuit) at all undesired harmonic
frequencies. This constrains all the nonlinear load current harmonics to flow into the
passive filter, decoupling the source and nonlinear load at all frequencies, except at
the fundamental.
Nonlinear Load
AC Source
Shunt Passive
Filter
Shunt APF
Shunt Passive
Filter
Series APF
(a)
Figure 2.10
Nonlinear Load
AC Source
(b)
Hybrid APFs: (a) combination of shunt APF and shunt passive filter
2.4
20
Distribution line interactive PV inverters have been proposed [47]-[49]. They
merely provide real power from the PV array to the distribution line and fixed loads.
Efforts have been made to combine the shunt APF with PV system [23]-[25], [50],
[51]. The PV interactive shunt APF system can supply real power from the PV array
to loads, and support reactive and harmonic power simultaneously to utilise its
utmost installation capacity. This section reviews the distribution line interactive PV
inverter and the PV interactive shunt APF. A brief discussion on their operation
principles will be given.
2.4.1
devices to convert sunlight into electric energy. This technology has many excellent
features: it causes little environmental burden, it is of a modular type technology that
can be easily expanded, and it is applicable almost everywhere [21], [22]. Figure
2.11 illustrates the operation principle of a PV cell. When the PV cell is exposed to
sunlight, electrical charges are generated and this can be conducted away by metal
contacts as DC electricity. Groups of PV cells are electrical configured into modules
and arrays, which can be used to power electrical loads. With the appropriate power
conversion equipment, PV systems can produce AC power compatible with any
conventional appliances, and interconnected to the distribution line.
Electrical Load
(-)
DC Current
Flow
Sun
Photovoltaic
Cell
(+)
Figure 2.11
21
Distribution line interactive PV systems are designed to operate in parallel
with the distribution line [47]-[49].
distribution line interactive PV inverter system that comprises of a PV array, a DCbus capacitor, a smoothing inductor and an inverter. The primary component in
distribution line interactive PV systems is the inverter. The inverter converts the DC
power produced by the PV array into AC power consistent with the voltage of the
distribution system. A bi-directional interface is made between the PV system AC
output circuits and the distribution system, typically at the point of common coupling
(PCC). This allows the AC power produced by the PV system to supply the loads
and distribution line.
PCC
Electrical
Load
AC Source
PV Array
+
Inverter
Figure 2.12
Generally, the distribution line interactive PV system extracts power from the
PV array, providing current to the distribution line. When the distribution power
sources need to provide the peak power to the load, the energy provided by PV array
can alleviate the burden of distribution power sources. At night and during no
sunlight periods, the power required by the loads is received from the distribution
line.
22
2.4.2
merely provides real power from the PV array to the distribution line and fixed loads.
However during no sunlight period, the operation of distribution line interactive PV
inverter is halted.
Recently,
researchers have spent efforts in developing PV interactive shunt APF systems [23][25], [50], [51]. The PV interactive shunt APF can inject PV power into distribution
line. In addition, it can support reactive power compensation and filter harmonic
currents caused by nonlinear load.
Figure 2.13 illustrates the configuration of a PV interactive shunt APF system
which is similar to the standard distribution line interactive PV inverter system. This
scheme employs only one inverter to have the reactive power compensation,
harmonic currents mitigation, and real power supply functions.
PCC
Nonlinear
Load
AC Source
Electrical
Load
PV Array
+
Shunt APF
Figure 2.13
In the day-time with intensive sunlight, the PV interactive shunt APF system
brings all its functions into operation. At night and during no sunlight periods, the
power required by the loads is received from the distribution system while the
inverter system only provides reactive power compensation and filter harmonic
23
currents. Thus, the utilisation level of the PV interactive shunt APF system is higher
than the distribution line interactive PV inverter system.
Although the research in combining APF and PV array is not new, it appears
that no attempt has been made to combine a hybrid APF with PV array.
2.5
is the key component that ensures the correct operation of APF. The reference signal
estimation is initiated through the detection of essential voltage/current signals to
gather accurate system variables information. The voltage variables to be sensed are
AC source voltage, DC-bus voltage of the APF, and voltage across interfacing
transformer.
compensation current and DC-link current of the APF. Based on these system
variables feedbacks, reference signals estimation in terms of voltage/current levels
are estimated in frequency-domain or time-domain. Numerous publications, for
example [10], [35], [52]-[55] report on the theories related to detection and
measurement of the various system variables for reference signals estimation.
Figure 2.14 illustrates the considered reference signal estimation techniques.
These techniques cannot be considered to belong to the control loop since they
perform an independent task by providing the controller with the required reference
for further processing.
estimation techniques, providing for each of them a short description of their basic
features.
24
Frequency
Domain
Reference Signal
Estimation Techniques
Fourier Transform
p-q Theorem
Extension p-q Theorem
Time
Domain
Synchronous-Detection Theorem
Synchronous-Reference-Frame
Theorem
Sine-Multiplication Theorem
Figure 2.14
2.5.1
and three phase systems. It is mainly derived from the principle of Fourier analysis
as follows.
25
impractical for real-time application with dynamically varying loads. Therefore, this
technique is only suitable for slowly varying load conditions.
In order to make computation much faster, some modifications were
proposed and practiced in [56]. In this modified Fourier-series scheme, only the
fundamental component of current is calculated and this is used to separate the total
harmonic signal from the sampled load-current waveform.
2.5.2
signal in the form of either voltage or current signal from distorted and harmonicpolluted voltage and current signals.
voltages and currents into the 0 stationary reference frame [14], [45], [58]. From
this transformed quantities, the instantaneous active and reactive power of the
nonlinear load is calculated, which consists of a DC component and an AC
component.
26
waveforms are symmetrical and purely sinusoidal. If this technique is applied to
contaminated supplies, the resulting performance is proven to be poor [59].
In order to make the p-q theorem applicable for single-phase system, some
modifications in the original p-q theorem were proposed and implemented by
Dobrucky et al. [27]. The basics of extension p-q theorem for a single-phase system
are as follows:
Assume that the source voltage ( v s ) and load current ( i L ) of a single-phase system
are defined as
v s (t ) = 2Vs sin(t )
(2.5)
i L (t ) = 2 I L sin(t + )
(2.6)
(2.7)
i L' (t ) = 2 I L sin(t + 90 o )
(2.8)
v = v s (t ) and v = v s' (t )
(2.9)
i = i L (t ) and i = i L' (t )
(2.10)
(2.11)
27
The instantaneous reactive power of the load can be derived as
q = v i v i = q + q~
(2.12)
(2.13)
28
The instantaneous reactive power of the load can be derived as
q = v s' (t ) i L (t ) = q + q~
(2.14)
estimation based on the extension p-q theorem is not new [25], [60], this approach
has not yet been applied to a single-phase hybrid APF system involving passive HPF,
shunt APF and PV array.
29
2.5.2.4 Synchronous-Reference-Frame Theorem
30
2.6
The aim of APF control is to generate appropriate gating signals for the
switching transistors based on the estimated compensation reference signals. The
performance of an APF is affected significantly by the selection of control
techniques [62]. Therefore, the choice and implementation of the control technique
is very important for the achievement of a satisfactory APF performance.
A variety of control techniques, such as linear control [9], [11]-[13], [18],
[23]-[25], [36], [37], [40], digital deadbeat control [14], [15], [63]-[65], hysteresis
control [17], [26], [27], [57], [58], [60], etc., have been implemented for the APF
applications. Several publications [10], [52], [54], [55], [62] comprehensively report
the theories related to APF control techniques. This section briefly describes the
considered control techniques and their basic features.
2.6.1
resulting control signal is then compared with a sawtooth signal through a pulse
width modulation (PWM) controller to generate the appropriate gating signals for the
switching transistors [9], [11]-[13], [18], [23]-[25], [36], [37], [40]. The frequency
of the repetitive sawtooth signal establishes the switching frequency. This frequency
is kept constant in linear control technique. As shown in Figure 2.16, the gating
signal is set high when the control signal has a higher numerical value than the
sawtooth signal and via versa.
31
Compensated
error amplifier
control
signal
PWM
controller
+
if,ref or vf,ref
Figure 2.15
gating
signal
Active Power
Filter
if or vf
sawtooth
signal
sawtooth signal
control signal
t
sawtooth
control
<
signal
signal
gating signal
control
sawtooth
>
signal
signal
Ts
Figure 2.16
( switching frequency fs =
1
)
Ts
Generally, the Nyquist stability criterion and the Bode plots are used to
determine the appropriate compensation in the feedback loop for the desired steadystate and transient responses. With analogue PWM circuit, the response is fast and
its implementation is simple [54]. Nevertheless, due to inherent problem of analogue
circuitry, the linear control technique has an unsatisfactory harmonic compensation
performance. This is mainly due to the limitation of the achievable bandwidth of the
compensated error amplifier [55], [62].
32
2.6.2
The control of APF can also be realised by the hysteresis control technique
[17], [26], [27], [57], [58], [60]. It imposes a bang-bang type instantaneous control
that forces the APF compensation current ( i f ) or voltage ( v f ) signal to follow its
estimated reference signal ( i f ,ref or v f ,ref ) within a certain tolerance band. This
control scheme is shown in a block diagram form in Figure 2.17. In this control
scheme, a signal deviation ( H ) is designed and imposed on i f ,ref or v f ,ref to form
the upper and lower limits of a hysteresis band. The i f or v f is then measured and
compared with i f ,ref or v f ,ref ; the resulting error is subjected to a hysteresis
controller to determine the gating signals when exceeds the upper or lower limits set
by (estimated reference signal + H ) or (estimated reference signal - H ). As long
2
2
as the error is within the hysteresis band, no switching action is taken. Switching
occurs whenever the error hits the hysteresis band. The APF is therefore switched in
such a way that the peak-to-peak compensation current/voltage signal is limited to a
specified band determined by H as illustrated by Figure 2.18.
Hysteresis band
comparator
if,ref or vf,ref
Figure 2.17
+H
2
error
error
gating
signal
Active Power
Filter
if or vf
33
The advantages of using the hysteresis current controller are its excellent
dynamic performance and controllability of the peak-to-peak current ripple within a
specified hysteresis band [54], [55], [62]. Furthermore, the implementation of this
control scheme is simple; this is evident from the controller structure shown in
Figure 2.17. However, this control scheme exhibits several unsatisfactory features.
The main drawback is that it produces uneven switching frequency. Consequently,
difficulties arise in designing the passive HPF.
if or vf
actual signal
if or vf
reference signal
if,ref or vf,ref
t
gating signal
( uneven frequency fs )
Figure 2.18
2.7
Summary
34
This review reveals that there is a significant interest in hybrid APF for PQ
improvement and RE source for electric power generation. This could be attributed
to the availability of suitable power-switching devices, high performance PV array
and fast computing devices (microcontroller and DSP) at affordable prices. It is
obvious that more work still needs to be done in integrating the hybrid APF with PV
array to achieve a multifunctional active filtering system.
CHAPTER 3
3.1
Introduction
It has been shown that one of the electric power quality (PQ) issues that
receive much attention is the harmonic distortion of the source current. The hybrid
APF has been demonstrated to be an effective solution for harmonic mitigation. On
the other hand, renewable energy (RE) sources, in particular solar energy has become
feasible due to enormous research and development work being conducted over the
years.
Considering these facts, a new variation of a single-phase hybrid APF
topology, connected to a PV array is proposed. This topology is unique because it
effectively filters harmonic currents less than 1 kHz and of higher frequencies.
Furthermore, it simultaneously supplies the power from the PV array to the load.
This work also proposes the application of the extension p-q theorem to estimate the
compensation current reference for this topology.
simplifies the equations for the current reference. This will lead to a more efficient
implementation using DSP digital controller.
The proposed topology is presented in the following sections.
It will
36
3.2
is = iL,p
vu
2:1
is
vs
PCC
iL
240 Vrms
50Hz
Nonlinear load
Passive
HPF
ihp
if
Shunt APF
ihp = ihp,q
Figure 3.1
DC source
In the proposed scheme, the low-order harmonics are compensated using the
shunt APF, while the high-order harmonics are filtered by a passive high-pass filter
(HPF). Since the aim in using the HPF is to improve the filtering performance of
high-order harmonics, the HPFs resonant frequency can be tuned to frequency
where the filtering performance of the shunt APF is impaired, i.e. over 1 kHz. In this
way, the size of the HPF can be kept small. It is envisaged that this configuration is
effective to improve the filtering performance of high-order harmonics.
37
The size of interfacing inductor is a compromise between current control
dynamic response and switching ripple. The current control dynamic response can
be improved by using a small interfacing inductor. However, this would raise the
switching ripple in the basic shunt APF. In the proposed hybrid APF, the resulting
switching ripple is filtered by the HPF.
In day-time where intensive sunlight is available, the proposed hybrid APF
extracts power from the DC source that represents the PV array, providing additional
PV current ( i PV ) to the load. When the distribution source need to provide the peak
power to the load, the energy provided by the PV array can alleviate the burden of
distribution source as illustrated by Figure 3.2. At night and during no sunlight
periods, the power required by the load is delivered by the distribution source.
is = iL,p - iPV
vu
is
2:1
vs
PCC
iL
240 Vrms
50Hz
Nonlinear load
Passive
HPF
ihp
if
Shunt APF
DC source
+
ihp = ihp,q
Figure 3.2
38
3.3
APF topology is presented. The power circuit, interfacing inductor, and DC-bus
capacitor are discussed in detail.
3.3.1
hybrid APF topology, connected in parallel with the nonlinear load. It consists of a
passive HPF, a single-phase shunt APF constructed using a full-bridge voltage
source inverter (VSI) and a DC source that represents PV array. Subscript s, L, f, and
hp refer to source, load, shunt APF and passive HPF. The shunt APF and the DC
source are connected back-to-back with a DC-bus capacitor ( C f ). The VSI used in
this topology is operated in current controlled mode (CCM) to make the
compensation current ( i f ) control possible. This VSI uses DC-bus capacitor as the
supply and switches at high-frequency to generate a compensation current that
follows the estimated current reference.
capacitor ( VCf ) must kept to a value that is higher than the amplitude of the source
voltage ( > 2 Vs ).
The proposed hybrid APF is connected with the distribution line at the PCC
through an interfacing inductor ( L f ). This interfacing inductor provides isolation
from the distribution line. A large interfacing inductor is preferable because it results
in small switching ripple. However, the large interfacing inductor limits the dynamic
response of the compensation current. Therefore, there is a compromise involved in
sizing the interfacing inductor.
39
Distribution
voltage
vu
Ls
2:1
Source
voltage
vs
Lsmooth
PCC
is
Nonlinear load
iL
Cd
RL
240 Vrms
50Hz
Rhp
Lhp
ihp
Chp
Passive HPF
PV array
Shunt APF
if
Lf S1
S3
+
VCf
S2
S4
Cf
DC source
Figure 3.3
40
AC to DC in an uncontrolled manner. It is well known that this nonlinear load draws
highly distorted current from the distribution source, thus a major source of harmonic
distortion [4].
3.3.2
Power Circuit
The power circuit used in the proposed hybrid APF is a full-bridge VSI as
shown in Figure 3.4. The VSI consists of four transistors, each connected to an antiparallel diode. The transistors are the insulated gate bipolar transistors (IGBTs).
They are selected due to their superior performance characteristics, i.e. low forward
voltage drop, fast switching times and high power handling capability.
Gating signal
S1
Driver
Gating signal
S3
Driver
+
VCf
S4
S2
Driver
Figure 3.4
Driver
Cf
Gate drivers are needed to convert the gating signals to gate voltage that is
suitable to the IGBTs. The logic inverters ensure that each IGBTs on the same leg
complements each other. However, the finite switching times imply that during
current commutation, the IGBTs in one leg (S1 & S2 or S3 & S4) may conduct at the
switching instants. This will cause short circuit problem of the DC-bus capacitor
( C f ). Additional control logic in the gate drivers is needed to ensure the complete
turn on and turn off processes of the IGBTs in one bridge leg. This is referred to as
the blanking time, since both IGBTs have temporarily logic low gating signals.
41
3.3.3
Interfacing Inductor
The desired compensation current waveform is obtained by controlling the
switching of the IGBTs in the VSI. The switching ripple ( i sw ) of the compensation
current is determined by the available driving voltage across the interfacing inductor,
the size of the interfacing inductor and switching frequency. In the proposed scheme,
the driving voltage is the DC-bus voltage ( VCf ). As shown in Figure 3.5, the bipolar
DC-bus voltage across the interfacing inductor determines the peak-to-peak
switching ripple ( I sw, p p ).
Driving voltage
Switching ripple
I sw, p p =
VCf
2 L f f sw
i sw
VCf
0
t
VCf
Tsw =
Figure 3.5
1
f sw
From Figure 3.5, the minimum interfacing inductor ( L f ,min ) can be calculated
based on [66] as
L f ,min =
VCf
2 (I sw, p p ) f sw,max
(3.1)
where f sw,max maximum frequency of switching ripple and I sw, p p is the peak-topeak switching ripple of compensation current. The detailed derivation of (3.1) is
presented in Appendix A.
42
3.3.4
DC-Bus Capacitor
1
1
C f (VCf ) 2 (VCf ,ref ) 2 = 2Vs I L T
2
2
2
(3.2)
where VCf is the maximum or minimum DC-bus voltage, VCf ,ref is the DC-bus
voltage reference, Vs is the rms value of the source voltage, I L is the peak rms
value of the reactive and harmonic load currents and T is the period of source
voltage. The size of DC-bus capacitor is determined by
Cf
2Vs I L T
(3.3)
43
3.4
3.4.1
Figure 3.6 shows the overall control system for the proposed hybrid APF.
Subscript s, L, f, and hp refer to source, load, shunt APF and passive HPF. The task
of the control system is to produce appropriate gating signals for the switching
transistors (IGBTs). The control system consists of an instantaneous active/reactive
power calculator, three LPFs, a compensation current estimator, a proportionalintegral (PI) controller, a PLL and a hysteresis current controller.
Three current sensors and two voltage sensors are required for system
variables detection. The load current ( i L ), HPF current ( ihp ) and compensation
current ( i f ) are detected using Hall-Effect current sensors, while the source voltage
( v s ) and DC-bus voltage ( VCf ) are detected using Hall-Effect voltage sensors. The
digital based PLL is responsible to generate the reference sinewave ( sin(t ) and
sin(t 90 o ) ) with unity amplitude and synchronous with the source voltage.
Butterworth LPFs. These DC components are then fed to the compensation current
reference estimator to obtain the reactive load current ( i L ,q ), harmonic load current
44
( i L ,h ) and reactive HPF current ( ihp ,q ). The summation of these three current signals
will form the first component of the current reference signal ( i f ,ref 1 ).
VCf
PPV
DC-bus Voltage Controller
VCf,ref
VCf,ref
_
switch + IPV
ICf
PI
_
controller
+
S1
S2
S3
S4
Hysteresis
current
controller
Gating
signals
if,ref 2
+
iL,q
iL,h
ihp,q _
pL
_
Compensation
qL
_
current
q
hp
estimator
+
+
+
LPF
LPF
LPF
if,ref 1
_
pL
pL + ~
_
~
qL + qL
_
qhp+ q~hp
sin(
Figure 3.6
if
if,ref
iL
ihp
vs
-90o
t-90o)
sin(t)
PLL
DSP Based Implementation
The DC-bus voltage controller maintains the average voltage across the DCbus capacitor ( VCf ) constant against variations in distribution source. Under a loss
free situation, the hybrid APF does not need to draw any active power from the
distribution source. However, there will be losses in the resistance of interfacing
inductor, switches, etc., when the hybrid APF is generating the compensation current.
Unless these losses are regulated, the DC-bus voltage will drop steadily. Hence the
control of DC-bus voltage involves drawing an in phase sinusoidal charging current
( I Cf ) from the distribution source.
The DC voltage across the DC-bus capacitor is detected and compared with
its reference voltage ( VCf ,ref ). The compared result is processed by a PI controller to
obtain the desired amplitude of the DC-bus capacitor charging current ( I Cf ). This
charging current is then subtracted from the PV current ( I PV ). The resulting current
45
is then multiplied with the reference sinewave ( sin(t ) ) to form the second
component of current reference signal ( i f ,ref 2 ).
connected to the DC-bus capacitor, the DC-bus voltage controller can be removed.
In order to generate the compensation current that follows the current
reference signal, the fixed-band hysteresis current control method is adopted. The
estimated compensation current reference signal ( i f ,ref ) and the actual compensation
current signal ( i f ) are fed to a fixed-band hysteresis current controller to generate
appropriate gating signals for the switching transistors.
3.4.2
In the proposed topology, the extension p-q theorem is adopted for the
estimation of active, reactive and harmonic components of load current, and the
reactive component of HPF current.
For a single-phase distribution power system with nonlinear load, the load
current can be represented as,
i L (t ) = 2 I L ,n sin(nt + n )
(3.4)
n =1
where n is the phase angle of the n-th load current component. Under normal
circumstances, the source voltage can be assumed to be a sinusoidal, i.e.,
v s (t ) = 2Vs sin(t + )
(3.5)
46
The HPF current is assumed to contain only the reactive component as
ihp (t ) = 2 I hp sin(t + 90 o )
(3.6)
(3.7)
(3.8)
= q hp + q~hp
(3.9)
AC components, and v s' (t ) denotes the source voltage delayed by 90 o . The detailed
derivation of p L (t ) , q L (t ) and q hp (t ) based on extension p-q theorem is presented in
Appendix B.
By obtaining the DC components in (3.7), (3.8), and (3.9), the active load
current ( i L , p ), reactive load current ( i L ,q ), harmonic load current ( i L ,h ) and reactive
HPF current ( ihp ,q ) can be readily estimated as follows:
47
i L , p (t ) = 2
pL
sin(t )
Vs
(3.10)
i L ,q (t ) = 2
qL
sin(t 90 o )
Vs
(3.11)
i L,h (t ) = i L (t ) i L , p (t ) i L ,q (t )
(3.12)
and
ihp ,q (t ) = 2
q hp
Vs
sin(t 90 o )
(3.13)
PPV
sin(t )
VCf ,ref
(3.14)
where PPV is the active power of PV array, I Cf is the amplitude value of DC-bus
capacitor charging current and VCf ,ref is the DC-bus voltage reference.
3.4.3
Under a loss free situation, the hybrid APF need not provide any active power
to cancel the reactive and harmonic currents from the load, and the reactive current
from the HPF. These currents show up as reactive power. Thus, it is indeed possible
to make the DC-bus capacitor delivers the reactive power demanded by the proposed
hybrid APF. As the reactive power comes from the DC-bus capacitor and this
reactive energy transfers between the load and the DC-bus capacitor (charging and
discharging of the DC-bus capacitor), the average DC-bus voltage can be maintained
at a prescribed value.
48
However, due to switching loss, capacitor leakage current, etc., the
distribution source must provide not only the active power required by the load but
also the additional power required by the VSI to maintain the DC-bus voltage
constant. Unless these losses are regulated, the DC-bus voltage will drop steadily.
A PI controller used to control the DC-bus voltage is shown in Figure 3.7. Its
transfer function can be represented as
H ( s) = K p +
KI
s
(3.15)
where K p is the proportional constant that determines the dynamic response of the
DC-bus voltage control, and K I is the integration constant that determines its
settling time.
DC-bus actual
voltage
VCf
PI controller
voltage
transducer
_
+
Kp + K I / s
ICf
capacitor
charging current
VCf,ref
DC-bus voltage
reference
Figure 3.7
It can be noted that if K p and K I are large, the DC-bus voltage regulation is
dominant, and the steady-state DC-bus voltage error is low. On the hand, if K p and
K I are small, the real power unbalance give little effect to the transient performance.
49
As described in [12], the K p can be calculated using the energy-balance
principle. After K p is calculated, the K I can be determined empirically. Appendix
C presents the K p calculation using the energy-balance principle for the proposed
hybrid APF.
3.4.4
phase
detector
in (z )
input phase
signal
Loop Filter
H1(z)
z 1
DCO
H2(z)
sin(t)
Divider
-90o
sin(t-90o)
fd (z )
feedback phase signal
Digital PLL
Figure 3.8
The phase detector detects the phase difference between the input signal
( in ( z ) ) and the feedback signal ( fd ( z ) ). The compared result is sent to a loop
filter. Typically, the loop filter is a low-pass type. The output of loop filter is feed to
a DCO to generate the fd ( z ) . In order to generate sin(t ) with unity amplitude,
the fd ( z ) can be divided with the amplitude of the in ( z ) using a divider as
50
illustrated by Figure 3.8. On the other hand, the sin(t 90 o ) can be obtained by
delaying sin(t ) by 90.
H 1( z ) =
az 1
z 1
(3.16)
H 2( z ) =
cz
z 1
(3.17)
H ( z) =
acz c
z + (ac 2) z + (1 c)
2
(3.18)
Based on the closed-loop transfer function in (3.18), one can easily recognise
that it is a second-order system. In control system theory, the transfer function of the
second-order system can be written in a general format as,
H ( z) =
N ( z)
( z z1 )( z z 0 )
(3.19)
51
Based on the transfer function in (3.19), a characteristic equation of a discrete
time system is defined as,
( z ) = ( z z1 )( z z 0 ) = z 2 ( z1 + z 0 ) z + z1 z 0
(3.20)
(3.21)
(3.22)
As soon as C1 and C 0 of the system are given, the poles of a second-order system
can be determined. Those two parameters are usually used to specify performance
requirements of a system.
Appendix D.
3.4.5
52
_
pL
_
qL
_
qhp
_
pL
pL + ~
_
~
qL + qL
_
qhp+ q~hp
LPF
LPF
LPF
Figure 3.9
extraction
The transfer function of the second-order Butterworth LPF in s-domain is given by
G LPF ( s ) =
1
s + 2 LPF s + 2LPF
2
(3.23)
Under the bilinear transformation [68], the analogue LPF in (3.23) can be
transformed into digital LPF as follows:
G LPF ( z ) =
1
s 2 + 2 LPF s + 2LPF
s=
1 z 1
1+ z 1
G LPF (1 + z 1 ) 2
1 + a LPF 1 z 1 + a LPF 2 z 2
(3.24)
where the filter coefficients G LPF , a LPF 1 and a LPF 2 are easily found to be:
G LPF =
2LPF
1 + 2 LPF + 2LPF
a LPF 1 =
2( 2LPF 1)
1 + 2 LPF + 2LPF
a LPF 2 =
1 2 LPF + 2LPF
1 + 2 LPF + 2LPF
(3.25)
53
Note that the LPF in (3.25) is differed from the LPF in (3.23) due to the fact of
digital implementation consideration [68]. The LPF in (3.25) is given by
f
LPF = tan LPF
fs
(3.26)
3.5
p
A
1 s
+
Q 0
+ 1
(3.27)
54
In (3.27),
A=
1
C hp
0 =
p =
1
Lhp C hp
Rhp
Lhp
Q = Rhp
C hp
Lhp
(3.28)
where A is the gain coefficient, 0 is the series resonant frequency, p is the pole
frequency and Q is the quality factor. The detail of Z hp ( s ) derivation is presented in
Appendix E.
As illustrated by Figure 3.10, different transfer function characteristics are
possible depending on the value selected for the Rhp . The tuning of this HPF is
accomplished by the determination of 0 . The Rhp is chosen based on the desired
high-pass response and the series resonant attenuation.
0.5 Q 2.0 are typical [5].
Quality factors of
attenuation and less high-pass. In contrast, lower Q factors provide less series
attenuation and greater high-pass response. Hence, a trade off between the series
resonant and high-pass response exists.
Figure 3.11 presents an equivalent circuit of the proposed hybrid APF for
harmonics, where Z hp is the equivalent impedance of HPF and Z s is the equivalent
distribution source impedance assumed to be a simple inductor ( Ls ). In Figure 3.11,
the shunt APF is assumed to act as an ideal current source which produces the
55
compensation current that follows the compensation current reference, while the
nonlinear load is considered as a harmonic currents source. Since we are only
interested in the system performance with the harmonic components, the source
voltage can be neglected. This is because the source voltage is assumed to contain
only the fundamental frequency component.
Z hp ( j)
dB
1
C hp
Lhp
Rhp
1
Rhp C hp
Chp Lhp
Figure 3.10
is,h
ih
PCC
ihp,h
if,h
Chp
iL,h
Ls
Rhp
Lhp
Zs
Zhp
Figure 3.11
After the filter network is configured, a current divider transfer function can
be formulated. Referring to Figure 3.11, the source current to the injected current
transfer function ( H cds ( s ) ) can be derived as,
56
is ,h ( s )
H cds ( s ) =
ih ( s )
Z hp ( s )
Z hp ( s ) + Z s ( s )
2 1
s +
Q0
1
2
0
Ls Lhp C hp
R
hp
s + 1
3
L
s + (( Ls + Lhp ) C hp )s 2 + hp s + 1
hp
(3.29)
Transfer function (3.29) is important because it can be used to assess the overall filter
performance. A detailed derivation of H cds (s ) is presented in Appendix E.
A graphical plot of H cds (s ) is shown in Figure 3.12, where it has one crest
( H max ) due to the parallel resonance between Ls + Lhp and C hp . In particular, this
parallel resonance is a problem, as it enlarges harmonics around the parallel resonant
1
frequency f r =
2 ( Ls + Lhp )C hp
Hmax
H cds ( j) dB
1
2 Ls C hp
Ls
1
C hp ( Ls + Lhp )
Rhp
-20 dB/dec
1
C hp Lhp
1
Rhp C hp
Figure 3.12
( H cds (s ) )
57
3.6
Summary
overview of this work. Then, the operation of each main block is described. Next,
the overall control system is discussed in detail. Finally, the passive HPF design is
outlined.
The following statements summarise the discussions of the proposed
topology:
unique because it effectively filters harmonic currents less than 1 kHz and of
higher frequencies. Furthermore, it simultaneously supplies the power from
the PV array to the load.
In this work, the application of the extension p-q theorem is further extended
to a single-phase hybrid APF for compensation current reference estimation.
This chapter offers the theoretical analysis on the proposed topology.
CHAPTER 4
4.1
Introduction
Due to the complexity of modern power electronics system, computer
simulation has become an indispensable tool to analyse parts of circuits that is too
difficult or complex for hand calculation.
59
4.2
It consists of
distribution source, nonlinear load, shunt APF, passive HPF, overall control system
and DC source. The fixed-step solver with single-tasking mode is selected so as to
be compatible with the targeted DS1104 digital signal processor (DSP) controller
board from dSPACE. The latter also operates at fixed-size signal sample rate. The
simulation fixed-step size is chosen to be 0.2 s. Generally, smaller simulation step
size increases the accuracy of the results but it also increases the simulation time.
Figure 4.1
a DC source
4.2.1
Distribution Source
The power distribution source considered in the simulations is a 240 Vrms, 50
60
blockset from SimPowerSystems\Electrical Source library.
The isolation
transformer with turn ratio of 2:1 is constructed using the Linear Transformer
blockset from SimPowerSystems\Elements library.
(4.1)
The current and voltage signals are sensed using Current Measurement and
Voltage Measurement blocksets from SimPowerSystems\Measurements library
respectively.
Figure 4.2
4.2.2
Nonlinear Load
Figure 4.3 shows the detail of the Nonlinear Load block. It consists of a
61
Lsmooth = 1.15 mH
C d = 1000 F
RL = 250
(4.2)
The diode rectifier is constructed using the Universal Bridge blockset. The diodes
are configured as the power electronics devices in the Universal Bridge blockset.
Figure 4.3
4.2.3
consists of an interfacing inductor ( L f ), a voltage source inverter (VSI) and a DCbus capacitor ( C f ). The VSI is constructed using the Universal Bridge blockset.
The IGBTs with anti-parallel diodes are configured as the power electronics devices
in the Universal Bridge blockset.
The design expression described in Chapter 3 (Section 3.3.3) is used to
calculate the value of L f . The rated DC-bus voltage reference ( VCf ) used in the
simulation is set to 250 V, which is approximately one and a half times higher than
the amplitude of source voltage ( 2 Vs ). The maximum switching frequency of the
switching ripple ( f sw,max ) and peak-to-peak switching ripple ( I sw, p p ) of the
62
compensation current is selected to be 12.5 kHz and 1.0 A respectively. Using (3.1)
the minimum value of L f can be calculated as
L f ,min =
VCf
2 (I sw, p p ) f sw,max
250
= 10 mH
2 (1.0) 12.5k
(4.3)
Figure 4.4
T = 2 ms
(4.4)
63
where Vs is the rms value of the source voltage, I L is the peak rms value of the
reactive and harmonic load currents and T is the period of source voltage and VCf
is the maximum or minimum DC-bus voltage. Substituting (4.4) into (3.3), the size
of DC-bus capacitor can be calculated as
Cf
2Vs I L T
2 120 6 0.02
(270) (250)
2
979.07 F
(4.5)
The detail of Passive HPF block is presented in Figure 4.5. The passive
HPF consists of a capacitor ( C hp ), an inductor ( Lhp ) and an inductor bypass resistor
( Rhp ). These passive components are constructed using the Parallel RLC Branch
blockset.
Figure 4.5
64
The design procedure of the passive HPF is described in Chapter 3 (Section
3.5).
( f0 =
= 1.28 kHz).
The
Lhp = 1.76 mH
C hp = 8.8 F
(4.6)
The Rhp is chosen based on the desired high-pass response and the series
resonant attenuation. Quality factors of 0.5 Q 2.0 are typical. In this work, the Q
factor is selected as 0.707, considering the required high-pass response over a wide
frequency band. From (3.28), the Rhp can be derived as
Rhp = Q
Lhp
(4.7)
C hp
Rhp = 0.707
1.76 10 3
8.8 10 6
= 9.998
(4.8)
From (3.27), the frequency response of the HPF impedance transfer function
is illustrated in Figure 4.6. Examination of the HPF frequency response reveals that
the HPF acts as very low impedance above the resonant frequency ( f 0 ) for which it
65
is tuned. As such, it effectively shunts most harmonic quantities above the resonant
Magnitude (dB)
frequency.
f0
Frequency (Hz)
Figure 4.6
After the filter system is configured, the transfer function of source current to
injected current in (3.29) is used to assess the overall system performance. The
frequency response of the function H cds ( s ) is illustrated in Figure 4.7. There is a
crest due to the parallel resonance between Ls + Lhp and C hp . In particular, this
parallel resonance is a problem, as it enlarges harmonics around the parallel resonant
frequency ( f r =
1
2 ( Ls + Lhp )C hp
selecting the value of Q around 0.7. For the frequency response shown in Figure 4.7,
the H cds ( s ) can be evaluated at low and high frequencies. For low frequencies, it
has a 0 dB gain from 0 Hz to f r . At f r , the gain is determined by the selection of
Q . For high frequencies, the roll-off of the high frequency components above f r is
-20 dB per decade.
66
Magnitude (dB)
fr
Frequency (Hz)
Figure 4.7
function
4.2.5
67
Figure 4.8
Figure 4.9 shows the detail of the Reference Sinewave Generator block. It
is responsible to generate the reference sinewave ( sin(t ) and sin(t 90 o ) ) with
unity amplitude and synchronous with the source voltage. Before the input phase
signal is processed by the Digital Phase-Lock Loop block, a Discrete 2nd-Order
Low-Pass Filter blockset from SimPowerSystems\Discrete Control Blocks library
is adopted to eliminate the high frequency noise. The cut-off frequency of the lowpass filter is selected to be 100 Hz. There is a need for compensation of the inherent
phase delay in the low-pass filter due to the low cut-off frequency. The detail of the
Phase Delay Compensation block is presented in Figure 4.10. It is constructed
using the Unit Delay blocksets from the Simulink\Discrete library.
The Digital Phase-Lock Loop block is constructed using the Discrete
Transfer Fcn blockset.
68
output of Digital Phase-Lock Loop block is divided with the amplitude of the input
phase signal ( 2 Vs ).
sin(t ) with 90.
Figure 4.9
Figure 4.10
The coefficients calculation procedures for the digital phase-lock loop (PLL)
are outlined in Chapter 3 (Section 3.4.4) and Appendix D. For the simulation model,
the digital PLL design parameters are given by
= 0.707
n = 2 200 rad/s
Ts = 100 s
(4.9)
69
where is the damping ratio, n is the undamped frequency and Ts is the sampling
period of the discrete system.
= e 2 ( 0.707 )( 2 200)(100 )
= 0.837203188
and
(4.10)
From the characteristic equation of (3.18) and (3.22), the constant c and constant a
of digital PLL can be calculated as
c = 1 C 0 = 0.162796812
and
a=
2 + C1
= 1.08875425
c
(4.11)
70
4.2.5.2 Compensation Current Reference Estimator
Figure 4.11
71
f s = 10 kHz
(4.12)
where is the damping ratio, f LPF is the cut-off frequency and f s is the sampling
frequency of the digital Butterworth LPF. Substituting (4.12) into (3.26), the natural
undamped frequency of the digital Butterworth LPF can be calculated as
f
LPF = tan LPF
fs
5
3
= tan
= 1.570797619 10 rad/s
10k
(4.13)
Substituting (4.12) and (4.13) into (3.25), the coefficients of digital Butterworth LPF
can be calculated as
G LPF =
2LPF
1 + 2 LPF + 2LPF
= 2.46193087 10 6
a LPF 1
2( 2LPF 1)
=
1 + 2 LPF + 2LPF
= -1.995557792
and
a LPF 2 =
1 2 LPF + 2LPF
1 + 2 LPF + 2LPF
= 0.99556764
(4.14)
72
4.2.5.3 DC-Bus Voltage Controller and PV Current Estimator
Discrete 2nd-Order LPF blockset for noise filtering. The filtered signal is then
passed to a proportional-integral (PI) controller for DC-bus capacitor charging
current estimation. The proportional constant ( K p ) and integration constant ( K I )
blocks are constructed using the Gain blocksets from the Simulink\Math
Operations library. The integrator is constructed using Discrete-Time Integrator
blockset. It must be noted that when a DC source is connected to the DC-bus
capacitor, the PI controller can be removed by turning off Switch (S5) blockset.
Figure 4.12
block
The PV current is obtained by dividing the available active PV power with
the DC-bus voltage reference. The resulting DC-bus capacitor charging current is
then subtracted from the PV current and multiplied with the reference sinewave to
form the second component of compensation current reference signal.
The design procedure of the PI controller is presented in Chapter 3 (Section
3.4.3) and Appendix C. The design parameters of the PI controller are:
73
C f = 990 F
VCf ,ref = 250 VDC
Vs = 120 Vrms
T = 2 ms
(4.15)
Kp =
2C f VCf ,ref
T 2Vs
2(990)(250)
0.02 2 (120)
= 0.145840773
(4.16)
instantaneous control that forces the compensation current to follow its estimated
reference.
reference. The resulting error is sent through a hysteresis controller to determine the
appropriate gating signals. In the simulation model, the hysteresis band ( H ) is
74
chosen as 1.0 A. The hysteresis controller is constructed using Relay blockset
from Simulink\Discontinuities library.
Figure 4.13
4.3
Figure 4.14 illustrates a basic shunt APF simulation model constructed under
MATLAB/Simulink environment.
Figure 4.14
source
75
This simulation model for the basic shunt APF is similar to the model of the
proposed topology presented in Figure 4.1, except for the removal of Passive HPF
block. Therefore, the descriptions given in Section 4.2 are applicable for the basic
shunt APF. The basic shunt APF is configured to generate compensation current
equals to the reactive and harmonic load current.
4.4
Summary
CHAPTER 5
5.1
Introduction
In this chapter, the hardware implementation of a 500 VA experimental
prototype of the proposed hybrid active power filter (APF) is presented. The system
parameters used in the hardware implementation are the same used in simulation.
The general experimental set-up is presented first, followed by the descriptions on
prototype construction.
5.2
Figure 5.2 shows the actual overall experimental set-up. The experimental prototype
is supplied from a 240 Vrms, 50 Hz distribution source via a variable transformer and
a 2:1 turns ratio isolation transformer. The use of variable transformer allows the
system to be operated at lower than the rated voltage level, which is very useful
77
during the development stage. An isolation transformer is used mainly to provide
safety when using measuring equipments such as an oscilloscope.
The nonlinear load is constructed using a single-phase full-bridge diode
rectifier with DC smoothing capacitor and AC smoothing inductor. The nonlinear
load is applied in order to generate the load current to be compensated by the hybrid
APF. The diode rectifier load is purely resistive, i.e. a lamp ballast. The leakage
inductor of the isolation transformer is considered as the source inductor. The inrush
source current is limited by an additional resistor in series with the source voltage.
Distribution Source
AC
Mains
Nonlinear Load
Isolation
Transformer
PCC
240 Vrms
(50Hz)
vs
is
Full-Bridge
Diode
Rectifier
iL
Variable
Transformer
Shunt APF
Power Ground
Digital Ground
ihp
Voltage
Source
Inverter
if
Passive
HPF
Overall Control
System
VCf
Voltage
Transducer
vs
Voltage
Transducer
if
Current
Transducer
iL
Current
Transducer
ihp
Current
Transducer
Figure 5.1
+
VCf
_
4
Gate
Driver
Analogue
Prefilter
DS1104
Gating signals
PCI
PC
DC
Source
78
Rectifier Bridge
Resistive Load
Oscilloscope
Isolation
Transformer
Figure 5.2
Experimental
Prototype
Variable
Transformer
DC Source
Computer
The proposed hybrid APF is connected in parallel with the nonlinear load
being compensated. It consists of a passive high-pass filter (HPF), a shunt APF
constructed using a full-bridge voltage source inverter (VSI), an interfacing inductor,
a DC-bus capacitor and a DC source. Note that the DC-bus capacitor is supplied by
a DC source with the desired constant DC voltage level. Due to time constraint, the
DC-bus voltage controller is not implemented experimentally.
The heart of the overall control system is the dSPACE DS1104 DSP
controller board. It is programmed to realise the compensation current reference
estimation and control algorithm. It is also used to generate the required gating
signals to the VSI. The DS1104 is linked to a personal computer (PC) through a PCI
slot interface. Programming with C code is done using the dedicated ControlDesk
Source Code Editor and Microtec PowerPC C Compiler and Linker. The executable
object files and libraries are generated and loaded onto the on-board global memory
for real-time execution.
79
The Hall-Effect current and voltage transducers are employed for the
analogue signals measurement. The measured signals are sampled using the DS1104
on-board analogue-to-digital converters (ADCs) and passed on to the DSP for further
processing.
5.3
prototype. The prototype consists of interfacing inductor, gate drivers, VSI with DCbus capacitor, rectifier load, DS1104 connector board, smoothing inductor, current
and voltage transducers and passive HPF. The experimental prototype parameters
are shown in Table 5.1. The values and parameters of prototype components are the
same as those designed and simulated in Chapter 4.
1
4
2
3
66
77
8
Figure 5.3
drivers, (3) VSI with DC-bus capacitor, (4) rectifier load, (5) DS1104 connector
board, (6) smoothing inductor, (7) current and voltage transducers, (8) passive HPF
80
Table 5.1 : Experimental prototype parameters
Parameters
Symbol
Value
Source voltage
vs
Source inductor
Ls
0.76 mH
Rs
Sn
500 VA
Cd
1000 F
Lsmooth
1.15 mH
Load resistor
RL
250
1A
Interfacing inductor
Lf
10 mH
DC-bus capacitor
Cf
990 F
DC-bus voltage
VCf
250 VDC
f0
1.28 kHz
HPF inductor
Lhp
1.76 mH
HPF capacitor
Chp
8.8 F
Rhp
10
5.3.1
Nonlinear Load
The nonlinear load used in the experimental prototype is a single-phase full-
bridge diode rectifier. The diode module consists of four diodes in a package. This
diode module is of the type SKB60/08 manufactured by Semikron, which is a 60 A,
800 Vrms device. The DC smoothing capacitor ( C d ) consists of a 1000 F, 385 VDC
electrolytic capacitor (PEH200XJ4100M) manufactured by Evox Rifa.
This
capacitor is a high performance long life electrolytic capacitor, which has low
equivalent series resistance (ESR) and low equivalent series inductance (ESL).
The AC smoothing inductor ( Lsmooth ) is wound on a 3C90 ferrite core
manufactured by Ferroxcube. The 3C90 is selected because it has low power losses
and high saturation flux density, which are vital for energy storage purpose [71].
81
Furthermore, it is able to operate at frequency as high as 200 kHz. The selected core
geometry is the E-E core type ETD59, which is suitable for high power application
and simple coil winding. The specification for Lsmooth is given in Table 5.2. The
detailed design procedure for Lsmooth is presented in Appendix F.
Table 5.2 : AC smoothing inductor specification
Core
Core
Number
Saturation flux
Effective
Effective
material
type
of turns
density
length
area
Bsat
le
Ae
(turns)
(G at 100 C)
(mm)
(mm2)
(mH)
74
3400
139
368
1.15
3C90
5.3.2
ETD59
Inductance
inductor and a DC-bus capacitor. This subsection describes briefly on the shunt APF
construction.
82
Furthermore, the continuity of current during blanking time period is maintained by
the build-in anti-parallel diodes.
+
S1
G1
S3
E1
G3
E3
VCf
S2
G2
S4
E2
Figure 5.4
G4
_
E4
Its
specification is given in Table 5.3. The detailed design procedure of the 2.5 mH
inductor is presented in Appendix F.
Table 5.3 : 2.5 mH inductor specification
Core
Core
Number
Saturation flux
Effective
Effective
material
type
of turns
density
length
area
Bsat
le
Ae
(turns)
(G at 100 C)
(mm)
(mm2)
(mH)
160
3400
139
368
2.5
3C90
ETD59
Inductance
83
5.3.2.3 DC-Bus Capacitor
The DC-bus capacitor ( C f ) is constructed by arranging an array of capacitors
across the DC-bus rail, as shown in Figure 5.5. It consists of three electrolytic
capacitors connected in parallel, 330 F, 400 VDC each to give a total capacitance of
990 F. The electrolytic capacitors are of the type 2222-059-56331 manufactured
by BC Components. It is a high performance long life electrolytic capacitor, which
has low ESR and high ripple current capability. A bleed resistor (RB) is connected
across the capacitors to ensure that the high voltage is discharged when the shunt
APF is turned off.
DC-Bus
+
RB
Cf1
Cf2
Cf3
22 k (5W)
330uF
330uF
330uF
Figure 5.5
5.3.3
DC-bus capacitor
84
of 2.5 s is provided internally by the gate driver circuit. The gate driver circuit is
DS1104
Gate drive
circuit
I/O 1
GD1
I/O 2
GD2
GD1
S2
S3
GD2
S4
Gating
signals
Figure 5.6
5.3.4
The HPF capacitor ( C hp ), inductor ( Lhp ) and inductor bypass resistor ( Rhp )
are designed according to the specification used in the simulation. The C hp consists
of four metallised polypropylene film capacitor connected in parallel, 2.2 F each to
give a total capacitance of 8.8 F. The selected capacitors are of the type 2222-46816225 manufactured by BC Components.
capacitor provides a fairly high capacitance per unit volume and high pulse durability,
thus making it suitable for filtering application.
The Lhp is wound on a 3C90 ferrite core manufactured by Ferroxcube. The
specification for Lhp is given in Table 5.4. The detail design procedure for Lhp is
presented in Appendix F. The Rhp with resistance value of 10 is connected in
parallel with Lhp . This resistor is made up of an aluminium clad wire wound resistor,
type HSC200-10R manufactured by Tyco Electronics. This resistor is suitable for
applications where high wattage dissipation in a small space is required.
85
Table 5.4 : HPF inductor specification
Core
Core
Number
Saturation flux
Effective
Effective
material
type
of turns
density
length
area
Bsat
le
Ae
(turns)
(G at 100 C)
(mm)
(mm2)
(mH)
113
3400
139
368
1.76
3C90
5.4
ETD59
Inductance
For the control system, it is necessary to measure the following five analogue
signals:
(1)
(2)
Source voltage, v s
(3)
Compensation current, i f
(4)
Load current, i L
(5)
The measured signals are sampled using the DS1104 on-board ADCs and passed on
to the DSP for further processing. This section describes on the analogue signals
measurement using hall-effect voltage/current transducers.
Finally, an analogue
5.4.1
86
circuitry. Therefore, occurrence of spikes, noise etc. from the power distribution
system will be directly transmitted to the sensitive low-power circuits.
A preferable alternative is to use a Hall-Effect voltage transducer.
The
VCf or v s . Note that the earth from the LV25-P is connected to the digital ground.
R1 22k
(5W)
-15V
Proportional output
LV25-P
1
+HT
VCf or vs
2
-HT
+15V
5
4
3
RM 200
(0.5W)
Digital ground
Figure 5.7
transducer
5.4.2
Three current transducers are needed for i f , i L and ihp measurements. The
Hall-Effect current transducer type LA25-NP, manufactured by LEM is selected as
the current transducer.
isolation capability of about 2.5 kVrms at 50 Hz. It provides five selectable current
measurement ranges (5/6/8/12/25 A). In this work, the current measurement range of
8 A is selected. Figure 5.8 shows the circuitry to obtain an output proportional to
i f , i L or ihp . Note that the earth from the LA25-NP is connected to the digital
ground.
87
-15V
+15V
Proportional output
LA25-NP
1
in
1-5
if , iL or ihp
2
out
6-10
RM 200
(0.5W)
Digital ground
Figure 5.8
transducer
5.4.3
Analogue Prefilter
In order to sample a signal at a desired rate and satisfy the conditions of the
sampling theorem, the signal must be prefiltered by a low-pass analogue filter,
known as an anti-aliasing prefilter [68]. The output of the analogue prefilter will
then be band-limited and sampled properly at the desired sampling rate. In this work,
the VCf, vs, iL and ihp are sampled at 10 kHz sampling rate (fs1 = 10 kHz), while if is
sampled at 100 kHz sampling rate (fs2 = 100 kHz). Figure 5.9 shows the circuitry of
the analogue prefilter.
( fc =
1
2R C1C 2
rate ( f c1 =
1
1
f s1 5 kHz and f c 2 = f s 2 50 kHz).
2
2
Cut-off frequency, fc
R3
C1
C2
(k)
(k)
(pF)
(pF)
fc1 = 5 kHz
22
47
1000
2000
fc2 = 50 kHz
22
47
100
220
88
C2
R = R1 = R2
R3
_
Analogue
input signal
R1
R2
TL051
+
Analogue
output signal
C1
Figure 5.9
5.5
All the control algorithms, gating signals generation and protection of the
experimental prototype are performed by a DSP controller board, the DS1104 from
dSPACE [74]-[78]. This section presents the controller hardware and the software
tools for the overall control system implementation.
The DS1104 DSP controller board is used to develop, debug and execute the
control program. It is a standard board that can be plugged into a PCI slot of a PC.
The DS1104 is specially designed for the development of high-speed multivariable
digital controllers in various application fields. It is a complete real-time control
system based on a 603 PowerPC floating-point processor manufactured by Motorola,
running at 250 Mhz. For advanced I/O purposes, the controller board includes a
slave DSP subsystem based on the TMS320F240 DSP microcontroller manufactured
by Texas Instruments.
Figure 5.10 shows a block diagram that describes the main features of the
controller board. The rich selection of on-board peripherals such as ADCs, digital-
89
to-analogue converters (DACs), bits I/O, Incremental Encoder Interface, Serial
Interface, Serial Peripheral Interface , User Interrupts, Encoder Interrupts, Slave DSP
interrupt, Timers Units make the interface task with gate driver circuit easier and
more reliable.
PCI Bus
PC
PWM
1 x 3-Phase
4 x 1-Phase
PCI Interface
Interrupt Controller
32 MB
SDRAM
Timers
TMS320F240
DSP
4 Capture
Inputs
Dual Port
RAM
Serial
Peripheral
Interface
Memory Controller
PowerPC 603e
8 MB Flash
Memory
Digital I/O
14-Bit
24 Bit I/O Bus
ADC
4 Ch. 16-Bit
4 Ch. 12-Bit
DAC
8 Ch. 16-Bit
Incremental
Encoder
2 Ch.
Digital I/O
20 Bit
Serial Interface
RS232/RS485/
RS422
DS1104
Figure 5.10
5.5.2
Software Tools
Microtec PowerPC C Compiler and Linker. Other support tools include ControlDesk,
90
Platform Manager, Experiment Manager, Real-Time Library (RTLib) and a real-time
platform known as Real-Time Interface (RTI). The ControlDesk, dSPACEs wellestablish experiment software, provides all the functions to control and monitor the
DS1104 hardware.
ControlDesk software.
Figure 5.11
91
An algorithm can also be handcoded manually using C language [79], then
the code is downloaded into the global memory of DS1104. All the tools required to
generate the object files are provided by the dSPACEs software. By using the
handcoding approach, the system initialisation and I/O features are now accessible.
In this work, the handcoding approach is adopted.
5.6
Control Software
The main purpose of the software control is to generate the appropriate gating
signals to drive the switching transistors according to the estimated current reference.
This section explains the control algorithms implementation on the DS1104.
5.6.1
Figure 5.12 shows the structure of the control software for DS1104. At the
highest level, the control software consists of initialisation routine and run routines.
Upon completion of the necessary initialisation, the background service is started.
The background service is simply an infinite loop. At all time, the control processing
is done via one service routine (isr_srt0()) and one interrupt service routine
(isr_srt1()). Two timers are used, Timer 0 and Timer 1, with execution times chosen
to be 10 s and 100 s respectively. The control algorithms implemented during
Timer 1 are the reference sinewave generation, compensation current reference and
PV current estimation and system protection. The fixed-band hysteresis current
control algorithm is implemented during Timer 0.
92
Run Routines:
Timer 0, isr_srt0():
- Fixed-Band Hysteresis Current
Control
Start
Timer 1, isr_srt1():
- Reference Sinewave Generation
- Compensation Current Reference
and PV Current Estimation
- System Protection
Initialisation Routine:
- DSP Setup
- Variables Initialisation
- Peripheral Initilisation
- Set Interrupts
- Start Timers
(Timer 0, Timer 1)
- Start Background Service
host_service():
- Data Capture
Background Service
Figure 5.12
5.6.2
Initialisation Routine
5.6.3
Service Routine 0
93
The sampled value is then subtracted from the compensation current reference signal
( i f ,ref ). The resulting error ( ihysteresis ) is subjected to a comparator to determine the
gating signals (bit I/O 5 and I/O 17) when exceeds/equals the predefined upper or
lower limits (0.5 or -0.5). As long as ihysteresis is within the limits, no switching action
is taken.
5.6.4
current
estimator
subroutine
(extension_pq_theorem()
and
94
START
DSP setup
Initialise variables,
peripherals
Set interrupts
isr_srt0(),
isr_srt1()
Background loop
Figure 5.13
START
isr_srt0()
Read ADC8 for if
Start ADC8 conversion
for if
Sampling ends?
No
Yes
Calculates ihysteresis = if - if,ref
ihysteresis=>0.5
Yes
No
Yes
ihysteresis=<-0.5
No
END
Figure 5.14
95
START
isr_srt1()
Sampling ends?
No
Yes
Execute Reference Sinewave Generator
phase_lock_loop()
System fault?
Yes
No
Set Enable Signal,
bit I/O 11 to 1
Enable interrupt
END
Figure 5.15
96
5.7
Summary
CHAPTER 6
6.1
Introduction
In Chapter 4, the MATLAB/Simulink simulation of the proposed hybrid APF
98
and the proposed hybrid APF will be described. The discrepancies between the
simulation and experimental results are highlighted. The capability of the proposed
hybrid APF in handling the PV energy is evaluated. Finally, analysis on the Total
Harmonic Distortion (THD) for the proposed hybrid APF in comparison to a basic
shunt APF is carried out.
6.2
system in order to obtain the distorted load current. Figure 6.1 shows the simulated
source voltage and load current waveforms without any type of compensation. As
can be seen, the resulting load current is highly distorted. It deviates significantly
from a sinusoidal waveform. This distorted load current leads to distortion in the
source voltage waveform. This can be clearly observed by the existence of flat-top
at the peak of the source voltage waveform. The distortion in the source voltage
300
200
100
0
-100
-200
-300
6
4
2
0
-2
-4
-6
4
Figure 6.1
12
16
20
24
Time, t [ms]
28
32
36
40
current waveforms
99
The experimental source voltage and load current waveforms with similar
operating condition are shown in Figure 6.2. Measurements are done using the
Tektronix TDS 3054A 500 MHz four channel digital oscilloscope. It can be seen
that the experimental results are in close agreement with the simulation results shown
300
200
100
0
-100
-200
-300
in Figure 6.1.
6
4
2
0
-2
-4
-6
0
Figure 6.2
12
16
20
Time, t [ms]
24
28
32
36
40
current waveforms
6.3
100
The experimental PLL generated waveforms are shown in Figure 6.4. Since
the data for the PLL generated reference sinewave are stored in the DS1104, they are
captured from the on-board digital-to-analogue converters (DACs).
As can be
observed, the experimental results are in accordance with the results obtained from
300
200
100
0
-100
-200
-300
Reference sinewave
the simulation.
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
sin(t-90)
sin(t)
12
16
20
Time, t [ms]
24
28
32
36
40
Figure 6.3
300
200
100
0
-100
-200
-300
Reference sinewave
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
sin(t)
Figure 6.4
12
16
20
Time, t [ms]
sin(t-90)
24
28
32
36
40
101
6.4
3
2
1
0
-1
-2
-3
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
4
Figure 6.5
12
16
20
Time, t [ms]
24
28
32
36
40
3
2
1
0
-1
-2
-3
102
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
0
Figure 6.6
12
16
20
Time, t [ms]
24
28
32
36
40
i L ,h = i L (i L , p + i L ,q )
(6.1)
In addition, this figure also shows the reactive HPF ( ihp ,q ) current waveform. It is in
phase with the HPF current ( ihp ).
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
60
40
20
0
-20
-40
-60
3
2
1
0
-1
-2
-3
103
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
4
Figure 6.7
12
16
20
24
Time, t [ms]
28
32
36
40
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
60
40
20
0
-20
-40
-60
3
2
1
0
-1
-2
-3
104
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0
Figure 6.8
12
16
20
Time, t [ms]
24
28
32
36
40
6.5
105
compensation condition. The general arrangement of the experimental prototype
with ideal compensation condition is shown in Figure 6.9. In the ideal case, the
proposed hybrid APF is assumed to be an ideal current source. This ideal current
source is assumed to inject a compensation current ( i f ) which is equal to the
estimated compensation current reference ( i f ,ref ). The aim of this exercise is to
verify the correctness of compensation current reference calculation. This ensures
that the proposed idea is workable with the absence of unwanted noise. Therefore,
this exercise can be considered as a controlled environment type of experiment.
Distribution Source
Nonlinear Load
vs
AC
Mains
PCC
is
240 Vrms
(50Hz)
if
iL
Proposed
Hybrid APF
Full-Bridge
Diode
Rectifier
Power Ground
Figure 6.9
(6.2)
where i s is the source current after compensation, i L is the load current and i f is the
compensation current.
compensation current ( i f ) such that it cancels out the reactive and harmonic parts of
load current. In other words, i f ,ref is equivalent to the summation of i L ,q and i L ,h :
i f ,ref = iL ,q + iL ,h
(6.3)
106
Simulation based on (6.2) is carried out to verify the effectiveness of the i f ,ref
under ideal compensation condition. Figure 6.10 shows the simulation results of this
analysis. Note that the source current ( i s ) waveform is obtained mathematically by
subtracting i f from iL using (6.2). The resulting i s appears to be a pure sinusoidal
This implies that i s is perfectly free of harmonic distortion.
waveform.
The
Load Current,
iL [A]
simulation suggests that the proposed compensation scheme work very well.
3
2
1
0
-1
-2
-3
3
2
1
0
-1
-2
-3
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
4
Figure 6.10
12
16
20
24
Time, t [ms]
28
32
36
40
experimental results match very closely with the simulation results shown in Figure
6.10. It can therefore be concluded that the application of extension p-q theorem to
estimate the compensation current reference for the proposed hybrid APF work very
well.
Load Current,
iL [A]
107
3
2
1
0
-1
-2
-3
3
2
1
0
-1
-2
-3
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
0
Figure 6.11
12
16
20
Time, t [ms]
24
28
32
36
40
6.6
The simulation results of the basic shunt APF are shown in Figure 6.12.
When the shunt APF is applied, the injected compensation current ( i f ) forces the
source current ( i s ) to become a near sinusoidal waveform. It can be seen that the
source current waveform is in phase with the source voltage ( v s ) waveform,
resulting in unity power factor. Note that the source voltage, load current and source
current contain appreciable amount of high frequency harmonics. This is due to the
108
unavoidable high frequency switching ripple of the compensation current and the
presence of source inductor ( Ls ). When the high frequency switching ripple is
injected into the point of common coupling (PCC), it corrupts the source voltage,
Source Voltage,
vs [V]
300
200
100
0
-100
-200
-300
Load Current,
iL [A]
6
4
2
0
-2
-4
-6
Compensation Current,
if [A]
6
4
2
0
-2
-4
-6
Source Current,
is [A]
3
2
1
0
-1
-2
-3
4
Figure 6.12
12
16
20
24
Time, t [ms]
28
32
36
40
109
The experimental results of the basic shunt APF compensation are shown in
Figure 6.13. The trend of the waveforms is consistent with the simulation. However,
from the results, it is observed that the switching ripple of the compensation current
is about 1.5 Apeak-to-peak even though the hysteresis band ( H ) is set to be 1.0 A. The
deviation in the magnitude of switching ripple is most probably due to the effect of
Source Voltage,
vs [V]
300
200
100
0
-100
-200
-300
Load Current,
iL [A]
6
4
2
0
-2
-4
-6
Compensation Current,
if [A]
6
4
2
0
-2
-4
-6
Source Current,
is [A]
3
2
1
0
-1
-2
-3
0
Figure 6.13
12
16
20
Time, t [ms]
24
28
32
36
40
110
The ideal simulation result in Figure 6.14 illustrates the relationship between
the compensation current reference and the hysteresis band ( H ). In this case, the
compensation current reference is free of noise. The hysteresis band ( H = 1.0 A )
can be simply imposed on the compensation current to form the upper ( i f ,ref + 0.5 A )
and lower ( i f ,ref 0.5 A ) limits.
compensation current hits the upper or lower limit. As a result, the switching ripple
of compensation current can be maintained to be 1.0 Apeak-to-peak as shown in Figure
6.12.
if,ref + 0.5A
H = 1.0 A
if,ref - 0.5A
3
2
1
0
-1
-2
-3
4
Figure 6.14
12
16
20
24
Time, t [ms]
28
32
36
40
111
noise currents to form the upper ( i f ,ref + | inoise,max | +0.5 A ) and lower
( i f ,ref | inoise,min | 0.5 A ) limits. As a result, a hysteresis band which is bigger than
1.0 A is formed, as shown in Figure 6.15. Consequently, the switching ripple of
compensation current will exceed the predefined hysteresis band. This fact, in our
view, is the main reason why the experimental results differ substantially from the
simulation.
inoise, max
if,ref + |inoise, max| + 0.5A
inoise, min
> 1.0 A
Figure 6.15
12
16
20
Time, t [ms]
24
28
32
36
40
6.7
Section 6.6 clearly demonstrates that the harmonic distortion in the source
current is reduced significantly using the basic shunt APF. However, an appreciable
amount of switching ripple still remains in the source voltage, load current and
112
source current waveforms. To reduce the switching ripple, a passive HPF is placed
in parallel with the shunt APF at the PCC. The HPF provides a path for the
switching ripple to flow.
Figure 6.16 shows the simulation results with the proposed hybrid APF.
When the hybrid APF is applied, the injected compensation current ( i f ) forces the
source current ( i s ) to become a near sinusoidal waveform and in phase with the
source voltage waveform, resulting in unity power factor.
Comparing to the simulation result without HPF shown in Figure 6.12, the
switching ripple in the source current is greatly reduced. It can be concluded that the
HPF provides a path for the high frequency switching ripple to flow. This is evident
by the fact of that switching noise presence in the HPF current waveform. Hence,
the filtering performance of high frequency harmonics is improved by the proposed
topology.
Distortion is observed at the peak of source current waveform.
This
distortion occurs when the current reference has a sharp ramp (i.e. at the peak of the
load current waveform). The compensation current tends to have a delay when
tracking sharp ramp in the current reference. This problem is probably due to the
insufficient sampling in the digitally implemented hysteresis current controller. The
finite sampling time of 10 s for the hysteresis current controller may not be
sufficient to correct samples of the fast changing compensation current. As a result,
the effectiveness of the proposed compensation scheme is degraded and the
distortion occurs.
The simulation results are verified by that of experiments as shown in Figure
6.17. From the results, it is observed that the switching ripple of the compensation
current differs from the predefined hysteresis band ( H ). Again, the difference in
switching ripple is most probably due to the effect of noise currents in the
compensation current reference as previously described. The conformity of the
experimental results to the simulation results can be considered good, except for the
deviation in the switching ripple amplitude.
Source Voltage,
vs [V]
300
200
100
0
-100
-200
-300
Load Current,
iL [A]
6
4
2
0
-2
-4
-6
HPF Current,
ihp [A]
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
Compensation Current,
if [A]
6
4
2
0
-2
-4
-6
Source Current,
is [A]
113
3
2
1
0
-1
-2
-3
4
Figure 6.16
12
16
20
24
Time, t [ms]
28
32
36
40
load current, HPF current, compensation current and source current waveforms
Source Voltage,
vs [V]
300
200
100
0
-100
-200
-300
Load Current,
iL [A]
6
4
2
0
-2
-4
-6
HPF Current,
ihp [A]
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
Compensation Current,
if [A]
6
4
2
0
-2
-4
-6
Source Current,
is [A]
114
3
2
1
0
-1
-2
-3
0
Figure 6.17
12
16
20
Time, t [ms]
24
28
32
36
voltage, load current, HPF current, compensation current and source current
waveforms
40
115
6.8
The harmonic mitigation feature of the proposed topology has been clearly
demonstrated in Section 6.7.
proposed topology, i.e. the PV energy handling capability. The overall experimental
setup is the same as the one used in Section 6.7. Therefore, the results obtained in
Section 6.7 can be treated as the results for the proposed topology with zero PV
power generation.
Figure 6.18 shows the simulated load current, compensation current and
source current waveforms with 250 W PV power being injected into the proposed
hybrid APF system. Compared to Figure 6.16, the amount of source current drawn
from the distribution source is reduced by 1.0 A. This implies that 250 W of PV
power is provided by the PV array. The remaining component of the source current
corresponds to the effect of digitally implemented hysteresis current controller as
Load Current,
iL [A]
previously described.
6
4
2
0
-2
-4
-6
6
4
2
0
-2
-4
-6
3
2
1
0
-1
-2
-3
4
Figure 6.18
12
16
20
24
Time, t [ms]
28
32
36
40
116
These results demonstrate the PV power handling capability of the proposed
Load Current,
iL [A]
hybrid APF. It is further confirmed by the experimental results shown in Figure 6.19.
6
4
2
0
-2
-4
-6
6
4
2
0
-2
-4
-6
3
2
1
0
-1
-2
-3
0
Figure 6.19
12
16
20
Time, t [ms]
24
28
32
36
40
6.9
117
experimental results. However, the harmonic components (i.e. 150 Hz, 250 Hz, 350
Hz, , 2 kHz) of the experimental source current spectrum have bigger amplitude
than those obtained in the simulation. This is probably caused by the deviation of
components parameters between the simulation model and the experimental
Source Current,
is [A]
Source Current,
is [A]
1.2
1.0
0.8
0.6
0.4
0.2
0
4
6
Frequency, f [kHz]
(a)
10
12
1.2
1.0
0.8
0.6
0.4
0.2
0
0
Figure 6.20
1.25
2.50
3.75
8.75
In
comparison to Figure 6.20, the source current is almost free of harmonics. The
source current is effectively compensated under ideal compensation condition. This
indicates that our proposed compensation scheme works very well without the
influence of external disturbances, such as noise.
Source Current,
is [A]
Source Current,
is [A]
118
1.2
1.0
0.8
0.6
0.4
0.2
0
4
6
Frequency, f [kHz]
(a)
10
12
1.2
1.0
0.8
0.6
0.4
0.2
0
0
Figure 6.21
1.25
2.50
3.75
8.75
Source Current,
is [A]
Source Current,
is [A]
119
1.2
1.0
0.8
0.6
0.4
0.2
0
4
6
Frequency, f [kHz]
(a)
10
12
1.2
1.0
0.8
0.6
0.4
0.2
0
0
Figure 6.22
1.25
2.50
3.75
8.75
Source Current,
is [A]
Source Current,
is [A]
120
1.2
1.0
0.8
0.6
0.4
0.2
0
4
6
Frequency, f [kHz]
(a)
10
12
1.2
1.0
0.8
0.6
0.4
0.2
0
0
Figure 6.23
1.25
2.50
3.75
8.75
kHz)
shown in Figure 6.20 to Figure 6.23 are tabulated in Table 6.1. It can be observed
that the THD12.5 kHz obtained from the experiments is in good agreement with the
simulation results. The source current THD12.5
kHz
36.5 % with basic shunt APF. With the proposed hybrid APF, the source current
THD12.5 kHz is further reduced to 19.6 %. Thus, the harmonic filtering performance
of the proposed topology is superior compared to the basic shunt APF.
Note that the source current THD12.5
kHz
compensation condition, compared to 36.5 % with basic shunt APF and 19.6 % with
proposed hybrid APF. It can be concluded that the proposed compensation scheme
works very well in a controlled environment. However, its performance degraded
with noise and limitation in the digital implementation of hysteresis current
controller.
recommended harmonics limit imposed by IEEE Standard 519 [33] is not scrutinised
further in this work.
121
Table 6.1 : Calculated THD for the source current
Type of Compensation
(Simulation result)
THD12.5 kHz
[%]
(Experimental result)
THD12.5 kHz
[%]
Without compensation
Ideal compensation
Basic shunt APF
Proposed scheme
106.8
1.8
40.3
19.5
130.2
1.9
36.5
19.6
6.10
Summary
This chapter presents the results obtained from the simulations and
experiments.
(2)
(3)
CHAPTER 7
7.1
Conclusions
This thesis has presented the development of a new variation of a single-
proposed hybrid APF improves the harmonic filtering performance of the basic shunt
APF. Furthermore, it is capable in handling the PV energy.
123
This research work has led to two important contributions:
(1)
(2)
7.2
(1)
124
Therefore, improvement in harmonic filtering performance can be
expected by incorporating a suitable current controller, for example:
proportional-integral (PI) controller, deadbeat controller and sliding
mode controller.
(2)
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1.
Akagi, H. New Trends in Active Filters for Power Conditioning. IEEE Trans.
on Industry Applications. 1996. 32(6): 1312-1322.
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Sutanto, D., Bou-rabee, M., Tam, K. S., and Chang, C. S. Harmonic Filters
for Industrial Power Systems. Proceedings of the IEE International
Conference on Advances in Power System Control, Operation and
Management (APSCOM). November 5-8, 1991. Hong Kong: IEE. 1991. 594598.
10.
11.
Jou, H. L. and Wu, H. Y. New Single-Phase Active Power Filter. Proc. IEE
Electric Power Applications. 1994. 141(3): 129-134.
12.
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14.
Buso, S. Malesani, L., Mattavelli, P., and Veronese, R. Design and Fully
Digital Control of Parallel Active Power Filters for Thyristor Rectifiers to
Comply with IEC-1000-3-2 Standards. IEEE Trans. on Industry Applications.
1998. 34(3): 508-517.
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18.
Routimo, M., Salo, M., and Tuusa, H. A Novel Control Method for
Wideband Harmonic Compensation. Proceedings of the IEEE International
Conference on Power Electronics and Drive Systems (PEDS). November 1720, 2003. Singapore: IEEE. 2003. 799-804.
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Kim, S., Yoo, G., and Song, J. A Bifunctional Utility Connected Photovoltaic
System with Power Factor Correction and U.P.S. Facility. Proceedings of the
IEEE Conference on Photovoltaic Specialist. May 13-17, 1996. Washington,
USA: IEEE. 1996. 1363-1368.
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Wu, T. F., Shen, C. -L., Chang, C. H., and Chiu, J. Y. 1/spl phi/ 3W GridConnection PV Power Inverter with Partial Active Power Filter. IEEE Trans.
on Aerospace and Electronic Systems. 2003. 39(2): 635-646.
26.
27.
Dobrucky, B., Kim, H., Racek, V., Roch, M., and Pokorny, M. Single-Phase
Power Active Filter and Compensator using Instantaneous Reactive Power
Method. Proceedings of the Power Conversion Conference (PCC). April 2-5,
2002. Osaka, Japan: IEEE. 2002. 167-171.
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Smith, C. W., Jr. Power Systems and Harmonic Factors. IEEE Potentials.
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Singh, B., Al-Haddad, K., and Chandra, A. A Review of Active Filters for
Power Quality Improvement. IEEE Trans. on Industrial Electronics. 1999.
46(5): 960-971.
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37.
Perez, J., Cardenas, V., Pazos, F., and Ramirez, S. Voltage Harmonic
Cancellation in Single-Phase Systems using a Series Active Filter with LowOrder Controller. Proceedings of the IEEE International Power Electronics
Congress (CIEP). Oct. 20-24, 2002. Guadalajara, Mexico: IEEE. 2002. 270274.
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Martins, D. C., Demonti, R., and Barbi, I. Usage of the Solar Energy from the
Photovoltaic Panels for the Generation of Electrical Energy. Proceedings of
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50.
Sung, N. G., Lee, J. D., Kim, B. T., Park, M., and Yu, I. K. Novel Concept of
a PV Power Generation System Adding the Function of Shunt Active Filter.
Proceedings of the IEEE Transmission and Distribution Conference. Oct. 610, 2002. Yokohama, Japan: IEEE. 2002. 1658-1663.
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Norman, M., Ahsanul, A., Senan, M., and Hashim, H. Review of Control
Strategies for Power Quality Conditioners. Proceedings of the IEEE National
Conference on Power and Energy Conference (PECon). Nov. 29-30, 2004.
Kuala Lumpur, Malaysia: IEEE. 2004. 109-115.
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Power Active Filters using DSPs. Proc. IEE Electric Power Applications.
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Wu, T. F., Shen, C. L., Chiu, J. Y., and Chen, C. C. An APF with
MAPPT Scheme to Improve Power Quality. Proceedings of the IEEE
International Conference on Electrical and Electronic Technology. August
19-22, 2001. Singapore: IEEE. 2001. 620-626.
61.
Chen, C. L., Chen, E. L., and Huang, C. L. An Active Filter for Unbalanced
Three-Phase System using Synchronous Detection Method. Proceedings of
the Power Electronics Specialist Conference (PESC). June 20-25, 1994.
Taipei, Taiwan: IEEE. 1994. 1451-1455.
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Malesani, L., Mattavelli, P., and Buso, S. Dead-Beat Current Control for
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PUBLICATIONS
1.
2.
3.
4.
Tan, P. C., Jusoh, A. and Salam, Z. Some Design Considerations of a SinglePhase Hybrid Active Power Filter. Proceedings of the 1st International
National Power and Energy Conference (PECon). November 28-29, 2006.
Malaysia, Putra Jaya: IEEE. 2006. in press.
APPENDIX A
if
Lf
Rf
vt
Figure A.1
vs
vt = v s + R f i f + L f
di f
dt
(A.1)
137
The terminal voltage and the compensation current can be expressed in terms of their
DC and the switching ripple components as
vt (t ) = Vt + v sw (t )
i f (t ) = I f + i sw (t )
(A.2)
where v sw (t ) and isw (t ) are the ripple components in vt and i f , respectively. From
(A.1) and (A.2)
Vt + v sw (t ) = v s + R f [ I f + isw (t )] + L f
disw (t )
dt
(A.3)
where
Vt = R f I f
(A.4)
and
vsw (t ) = vs + R f isw (t ) + L f
disw (t )
dt
(A.5)
We know that the ripple current is high frequency component and primarily
determined by the interfacing inductor ( Ls ). Therefore, vs and R f are assumed to
have negligible effects. From (A.5),
vsw (t ) L f
disw (t )
dt
(A.6)
Figure A.2 shows the voltage ripple vsw (t ) and the resulting ripple current isw (t )
using (A.6). Assumed that the voltage ripple vsw (t ) is represented by the bipolar
DC-bus voltage ( VCf or VCf ).
138
Switching ripple
I sw, p p =
VCf
2 L f f sw
i sw
VCf
t
VCf
Tsw =
Figure A.2
1
f sw
I sw, p p =
I sw, p p =
I sw, p p =
1
Lf
Tsw
vsw (t )dt
VCf Tsw
2L f
VCf
2 L f f sw
(A.7)
L f ,min =
VCf
2 (I sw, p p ) f sw,max
(A.8)
where f sw,max maximum frequency of switching ripple and I sw, p p is the peak-topeak switching ripple of compensation current.
APPENDIX B
i L (t ) = 2 I L ,n sin(nt + n )
(B.1)
n =1
(B.2)
B1.
Derivation of p L (t )
(B.3)
140
(B.4)
n=2
DC component
AC component
141
(B.5)
142
Therefore, the instantaneous active load power can be written as
p L (t ) = Vs I L ,1 cos( 1 ) Vs I L ,1 cos(2t + + 1 )
= pL + ~
pL
(B.6)
= Vs I L ,1 cos( 1 ) Vs I L ,1 cos(2t + + 1 )
(B.7)
where
pL
and
~
pL
(B.8)
n=2
B2.
Derivation of q L (t )
The instantaneous reactive load power can be obtained by multiplying the load
current with a 90-shifted source voltage ( v s' (t ) ) as follows:
q L (t ) = v s' (t ) i L (t )
143
DC component
AC component
144
(B.10)
= q L + q~L
(B.11)
where
q L = Vs I L ,1 sin( 1 ) Vs I L ,1 sin( 2t + + 1 )
(B.12)
145
and
q~L
(B.13)
n=2
B3.
Derivation of q hp (t )
The instantaneous reactive HPF power can be obtained by multiplying the HPF
current with a 90-shifted source voltage ( v s' (t ) ) as follows:
q hp (t ) = v s' (t ) ihp (t )
= 2Vs sin(t + 90 o )
= 2Vs cos(t + )
2 I hp sin(t + 90 )
2 I hp sin(t + 90 )
]
(B.14)
DC component
It can be observed that the DC component of (B.14) is similar to the DC
component of (B.9). Therefore, the derivation of (B.10) is applicable for (B.14) by
simply replace the 1 in (B.10) with 90. Solve for the DC component of (B.14),
146
2Vs I hp cos(t + ) sin(t + 90 o )
= Vs I hp {sin( 1 ) sin(2t + + 1 )}
= Vs I hp sin( 90 o ) sin( 2t + + 90 o )
= Vs I hp { cos() cos(2t + )}
(B.15)
(B.16)
where
q hp = Vs I hp { cos() cos(2t + )}
(B.17)
q~hp = 0
(B.18)
and
APPENDIX C
balance principle for the proposed hybrid APF is described as in the following.
If the reference voltage across the DC-bus capacitor is VCf ,ref , then the reference
energy in the capacitor will be
1
ECf ,ref = C f VCf2 ,ref
2
(C.1)
ECf (t ) =
1
C f vCf2 (t )
2
(C.2)
148
Cf
2
Cf
(C.3)
Assume that the variation in DC-bus voltage within one cycle is moderate, the term
(C.4)
(C.5)
Since this energy loss must be supplied by the distribution source, the peak value of
the DC-bus capacitor charging current ( I Cf ) can be estimated as follows:
(C.6)
Therefore
I Cf =
2
T 2Vs
ECf
I Cf =
2
T 2Vs
2C f VCf ,ref
T 2Vs
(C.7)
149
= K p {VCf ,ref vCf (t )}
(C.8)
Kp =
2C f VCf ,ref
T 2Vs
(C.9)
APPENDIX D
H 1( z ) =
az 1
z 1
(D.1)
cz
z 1
(D.2)
H 2( z ) =
z 1
1
1
z
z
=
az 1 cz 1
1+
z
z 1 z 1
acz c
( z 2 z + 1) + (acz c)
2
151
acz c
z + (ac 2) z + (1 c)
2
(D.3)
Based on the closed-loop transfer function in (D.3), one can easily tell that is
a second-order system. In control system theory, the transfer function of the secondorder system can often be written in a general format as
H ( z) =
N ( z)
( z z1 )( z z 0 )
(D.4)
(D.5)
(D.6)
(D.7)
152
H ( s) =
n2
s 2 + 2 n s + 2n
(D.8)
By solving the roots of the characteristics equation in (D.8), two poles ( s 0 and s1 ) of
the system can be derived as
s 0 = n + j n 1 2 = + j
s1 = n j n 1 2 = j
(D.9)
1 2 )
1 2 )
(D.10)
(D.11)
APPENDIX E
E.1
Figure E.1 shows the layout of the second-order damped series resonant type
high-pass filter (HPF). It consists of a capacitor ( C hp ), an inductor ( Lhp ) and an
inductor bypass resistor ( Rhp ).
1
sChp
Rhp
Figure E.1
sLhp
Zhp
Using a little algebra, the HPF impedance transfer function in (3.27) can be derived
as following:
Z hp ( s ) =
1
+ ( sLhp // Rhp )
sC hp
154
sLhp Rhp
1
+
sC hp sLhp + Rhp
sLhp Rhp
1
+
sC hp sLhp + Rhp
s
+
+ 1
hp
Lhp
sC hp Rhp
+ 1
Rhp
L
hp
s
Rhp
1
C hp Lhp
C hp
s
=
C hp Lhp
s
s
+ 1
Rhp
Lhp
s
=
0
s
s
+ 1
p
A
1
+
C hp
R
hp
Lhp
1 s
+ + 1
Q 0
C hp Lhp
+ 1
(E.1)
155
where
A=
1
C hp
0 =
p =
1
Lhp C hp
Rhp
Lhp
C hp
Q = Rhp
(E.2)
Lhp
E.2
H cds ( s ) =
i s ,h ( s )
ih ( s )
Z hp ( s )
Z hp ( s ) + Z s ( s )
(E.3)
156
s
Z hp ( s ) =
s
0
s
+ 1
1 s
+
Q 0
+ 1
Z s ( s ) = sLs
s 2 C L + sC R
hp hp
hp hp
H cds ( s ) = 2
s C hp Lhp Rhp + sLhp + Rhp
+ sLs
s 2 C L + sC R
hp
hp
hp
hp
s 2 C L + sC R
hp hp
hp hp
=
2
2
( s C hp Lhp Rhp + sLhp + Rhp ) + sLs ( s C hp Lhp + sC hp Rhp )
s
C
L
sC
R
+
hp hp
hp hp
s 2 C L + sC R
hp
hp
hp
hp
=
2
3
( s C hp Lhp Rhp + sLhp + Rhp ) + ( s Ls C hp Lhp + s 2 Ls C hp Rhp )
+
s
C
L
sC
R
hp
hp
hp
hp
Lhp
+ s 2 C hp ( Ls + Lhp ) + s
+ 1
Rhp s 3
Rhp
Rhp
(E.4)
157
C hp Lhp
1
+
C hp
R
hp
Lhp
C hp Lhp
+1
s
s
s 3 Ls C hp Lhp +
+
+ 1
Rhp
Rhp
1
C
L
L
(
+
)
Lhp
hp
s
hp
1 s
+
Q 0
+ 1
Ls C hp Lhp s 2
s
s3
+ +
+ 1
p
Rhp
1
(E.5)
In (E.5),
0 =
1 =
p =
1
Lhp C hp
1
C hp ( Ls + Lhp )
Rhp
Lhp
Q = Rhp
C hp
Lhp
(E.6)
APPENDIX F
F.1
(2)
(3)
(4)
These values are found via the design calculations for the specific power electronic
converter circuit in which the inductor is to be used.
159
Step 2 Specification of winding parameters
In this work, the conductor windings of inductor is made from copper
because of it high conductivity. Round wire or Litz wire can be chosen as the type of
winding conductor. Selection of the conductor type will depend on the operating
frequency and the important of eddy current loss in the winding. After the conductor
type is selected, the allowable current density can now be estimated (e.g. 300 circular
mils/A). The wire area is chosen on the basic of a safe current density. The total
circular mil area of the wire (A) is then calculated as
A = I rms (300) circular mils
(F.1)
From the wire table in Figure F.1, the wire having the closest circular mil area to the
calculated value will be selected. And from the wire table, the diameter of the
selected wire is D. The wire area per turn (At) can then be calculated by assuming
wire area per turn is D 2 rather than D 2 4 .
160
E = L(di dt ) = N (d dt )10 8
(F.2)
(F.3)
from which
Ae =
( LI max )10 +8
NBmax
(F.4)
But the core winding area (Ae) must be chosen to accommodate the required number
of turns at the specified safe-current density and the fraction of the total core winding
area usable. Thus, assume only 75% of the core winding area Ac is usable and
assume N turns of wire, whose area per turns is At. Then
NAt = 0.75 Ac
or
Ac =
NAt
0.75
(F.5)
Ae Ac =
(F.6)
161
In (F.6), as soon as the wire area is specified (on the basic of safe operating
current density), all terms on the right-hand side are specified and the product AeAc is
fixed. A core with the required product is then selected from the vendors datasheet.
Once this core is selected, Ae is determined from the datasheet and from (F.4), N is
calculated, since all other parameters in it are already fixed.
Step 4 Specification of the air gap length
H=
0.4NI DC
l
(F.7)
H dl = 0.4NI
(F.8)
162
This states the line integration around a closed loop of length l of the dot product of
the field intensity H and element of length dl is equal to 0.4NI, where NI is the
ampere turns enclosed by the loop. When an air gap is introduced in the length path,
the field intensity is constant and parallel across the air gap. Thus
H dl = H l
i i
+ H a l a = 0.4NI
(F.9)
where Hi is the core field intensity and Ha is the air gap field intensity. If the air gap
is narrow and there is no bulging of fringing of magnetic flux as it across the air gap,
then the flux density in the core, Bi, is equal to that in air, Ba. Then, Hi = Bi / i
where i is the average core permeability and Ha = Ba / a = Bi, since Ba = Bi and
permeability of air, a is unity. Then
Bi li i + Bi l a = 0.4NI
or
Bi =
0.4NI i
0.4NI
=
li i + l a
li + i l a
(F.10)
(F.10) states that for a given NI product, the flux density in the core with an air gap
of length la is smaller than with no air gap in the ratio
li
.
li + i l a
In (F.10), the maximum flux density in core, Bi, will occur at maximum I in
the inductor. This maximum I is the maximum at the top of the current ramp. In
(F.9), Bi will be set to prevent the core from rising on the slow knee of its hysteresis
loop at maximum temperature. Thus, as soon as the number of turns N and core
length li are chosen, (F.10) permits selecting air gap length.
Figure F.1
163
164
B (Flux density)
Hysteresis loop of
gapless core
Flattened hysteresis
loop of gapped core
B
Bsaturation
B1
P1
B2
P2
H (Field strength)
Bias in oersteds
-Bsaturation
Figure F.2
F.2
The round wire made from copper is chosen as the winding conductor. The
wire area is chosen on the basic of a safe current density. As a first guess, a current
density of 300 circular mils/A is chosen. The total circular mil area of the wire (A) is
then calculated as
A = I rms (300)
165
= 5(300) = 1500 circular mils
(F.11)
From the wire table in Figure F.1, the wire having the closest circular mil area to this
is No. 18 wire (1620 circular mils). And from the wire table, the diameter of this
wire is 0.043 in/0.11 cm. In this work, the copper wire with diameter (D) of 0.125
cm is selected due to the availability. Assuming wire area per turn is D 2 rather than
D 2 4 , the wire area per turn (At) can be calculated as
At = D 2
= (0.125) 2 = 0.01563 cm2
(F.12)
3C90 (ferrite)
Core shape
E-E core
In (F.6), take Bmax = 3000 G, which is safely below saturation for ferrite
material 3C90 ( Bsaturation = 3400 G). The required Ae Ac product for the core is
1.33( LI max At )10 +8
Ae Ac =
Bmax (0.75)
= 5.633 cm4
(F.13)
Looking through a ferrite core vendors catalogue [71], a ferrite core Ferroxcube type
ETD59 is found to have the required Ae Ac product. Its Ae is quoted as 3.68 cm2; its
166
Ac is 3.66 cm2. This gives an Ae Ac product of 13.4688 cm4, which is big enough for
N=
( LI max )10 +8
Ae Bmax
(1.15 10 3 )(7.07)(10 +8 )
= 73.646
(3.68)(3000)
74 turns
(F.14)
The ETD59 bobbin has Ac of 3.66 cm2. The area per turn of wire is then
3.66 74 = 0.0495 cm2, and its diameter is
value of diameter is bigger than the diameter of the selected copper wire ( D = 0.125
cm). The ETD59 bobbin can thus handle the required 74 turns of copper wire with
D = 0.125 cm at the specified current density of 300 circular mils/A.
Now, the air gap length ( l a ) must be specified from (F.10). In that equation,
i is the permeability of the core material. The chosen Ferroxcube 3C90 material
has a i of 2300 [71]. Then for a Bmax of 3000 G, I max = 0.707 A, and N = 74
turns, from (F.10),
li + i l a =
0.4NI i
Bi
0.4(74)(7.07)(2300)
= 504.043 cm
(3000)
(F.15)
167
Since the ETD59 bobbin has a mean path length li of 13.9 cm, from (F.15),
li + i l a = 504.043
Thus,
la =
504.043 13.9
= 0.2131 cm
2300
(F.16)
The ferrite core comes in two halves. Thus, if a spacer is located between the two
halves, the air gap is actually twice the spacer thickness. Since this spacer is in series
with four legs of the ferrite core, the spacer thickness must then be
0.2131 4 = 0.05328 cm. This completes the design of the AC smoothing inductor.
F.3
168
Table F.1 : 2.5 mH inductor specification
Inductance
Core
Core
Number
Saturation flux
Wire
Air gap
material
type
of turns
density
type
length
Bsat
la
(turns)
(G at 100 C)
(cm)
(mH)
160
3400
0.468
2.5
3C90
F.4
ETD59
No. 18
The HPF inductor ( Lhp ) consists of a 1.76 mH inductor. This section will
describe the design of Lhp.
The design variables consist of the following parameters:
Inductance value, L = 1.76 mH
Rated DC current, IDC = 0 A
Rated rms current, Irms = 5 A
Operating frequency, f = 100 kHz
The design parameters of Lhp can be readily calculated following the calculation
example given by (F.11) (F.16). Table F.2 shows the specification of Lhp .
Inductance
Core
Core
Number
Saturation flux
Wire
Air gap
material
type
of turns
density
type
length
Bsat
la
(turns)
(G at 100 C)
(cm)
(mH)
113
3400
0.329
1.76
3C90
ETD59
No. 18
APPENDIX G
G.1
Opto-Coupler Circuit
VCC
VCC2
U9
R13
270R
1
2
3
4
Upper Leg
R15
Jout
10R
HCPL 3150
OUT1
VEE2
VCC
1
2
3
4
OUT2
VCC3
U10
R14
270R
1
2
3
4
Lower leg
Figure G.1
CON4
C15
0.1uF
8
7
6
5
N/C VCC
ANOD Vo
KOTODVo
N/C VEE
HCPL 3150
G.2
C14
0.1uF
8
7
6
5
N/C VCC
ANOD Vo
KOTODVo
N/C VEE
R16
10R
VEE3
Schematic of opto-couple
U8A
U7A
1
D9
3
2
R5
10K
74ACT08
R6
10K
R9
VCC
R10
20k
Upper Leg
74ACT14
D1N4148
VCC
270R
C10
C11
C12
0.001uF
0.01uF
0.01uF
U8B
D10
3
JP2
4 Header
4
3
2
1
en1
U8E
11
JP1
2
1
10
2 Header
R7
Vin+12V
Figure G.2
R11
6
10k
R12
20k
74ACT08
74ACT14
4
74ACT14
D1N4148
U7B
input1
270R
C13
0.001uF
R8
10k
Lower leg
170
Figure G.3
G.3
APPENDIX H
H.1
/**************************************************************************
TITLE
:
SINGLE-PHASE HYBRID ACTIVE POWER FILTER
Writer
172
/**************************************************************************
Timer 0 and Timer 1 Period Setting
**************************************************************************/
#define ST0 10.0e-6
/* Timer 0 = 10e-6 s */
#define ST1 100.0e-6
/* Timer 1 = 100e-6 s */
/**************************************************************************
Variables for ControlDesk's Instruments
**************************************************************************/
Float64 exec_time0, exec_time1;
/* Execution time */
Float64 pi = 3.14159265358979;
/* Define value of pi */
int n1, n2;
/* Counter */
UInt32 mask_set = 0;
volatile int iselect = 0;
Float64 iref_out;
/* DAC output signal select */
/* System Fault Protection */
int enable1 = 1;
volatile int enable2 = 0;
int enable3 = 0;
int enable4 = 0;
*/
*/
*/
*/
*/
*/
*/
*/
*/
voltage
current
current
voltage
current
173
Float64 sine_ref_syn;
Float64 sine_ref_90deg;
/**************************************************************************
Parameters of routine compensating_current_ref()
**************************************************************************/
/*------------------------------------------------------------------------Parameters for subroutine delay8()
-------------------------------------------------------------------------*/
Float64 *w8;
int D8 = 50;
/*------------------------------------------------------------------------Parameters of subroutine delay9()
-------------------------------------------------------------------------*/
Float64 *w9;
int D9 = 43;
/*------------------------------------------------------------------------Parameters of subroutine delay10()
-------------------------------------------------------------------------*/
Float64 *w10;
int D10 = 99;
/**************************************************************************
Parameters of routine extension_pq_theorem()
**************************************************************************/
Float64 vsource_adc_90deg;
Float64 Pload;
Float64 Pload_dc;
Float64 Qload;
Float64 Qload_dc;
Float64 Qhpf;
Float64 Qhpf_dc;
/*------------------------------------------------------------------------Parameters of subroutine delay4()
-------------------------------------------------------------------------*/
Float64 *w4;
int D4 = 50;
/*------------------------------------------------------------------------Parameters of subroutine fir5()
-------------------------------------------------------------------------*/
Float64 *a5, *b5, *w5;
int M5,L5;
174
/*------------------------------------------------------------------------Parameters of subroutine fir6()
-------------------------------------------------------------------------*/
Float64 *a6, *b6, *w6;
int M6,L6;
/*------------------------------------------------------------------------Parameters of subroutine fir7()
-------------------------------------------------------------------------*/
Float64 *a7, *b7, *w7;
int M7,L7;
/*------------------------------------------------------------------------Parameters of subroutine fir11()
-------------------------------------------------------------------------*/
Float64 *a11, *b11, *w11;
int M11,L11;
/*------------------------------------------------------------------------Parameters of subroutine fir12()
-------------------------------------------------------------------------*/
Float64 *a12, *b12, *w12;
int M12,L12;
/*------------------------------------------------------------------------Parameters of subroutine fir13()
-------------------------------------------------------------------------*/
Float64 *a13, *b13, *w13;
int M13,L13;
/**************************************************************************
Parameters of routine phase_lock_loop()
**************************************************************************/
Float64 y1_a;
Float64 y1_b;
Float64 y1_c;
Float64 y1_d;
Float64 y1_e;
Float64 vs_rms;
Float64 vs_rms1;
Float64 vpll;
Float64 sine_ref;
/*------------------------------------------------------------------------Parameters of subroutine integ1()
-------------------------------------------------------------------------*/
Float64 *w2, y1_c1, y1_c2;
175
/*------------------------------------------------------------------------Parameters of subroutine fir1()
-------------------------------------------------------------------------*/
Float64 *a1, *b1, *w1;
int M1,L1;
/*------------------------------------------------------------------------Parameters of subroutine pll()
-------------------------------------------------------------------------*/
Float64 *a3, *b3, *w3;
int M3,L3;
/**************************************************************************
Subroutine listing for routine compensating_current_ref()
**************************************************************************/
/*------------------------------------------------------------------------Subroutine delay8()
- 90 degree phase shifting
-------------------------------------------------------------------------*/
Float64 delay8(x)
Float64 x;
{
int i;
Float64 z8;
z8 = w8[D8];
w8[0] = x;
for (i = D8; i>=1; i--)
{
w8[i] = w8[i-1];
}
return z8;
}
/*------------------------------------------------------------------------Subroutine delay9()
- source voltage synchronisation
-------------------------------------------------------------------------*/
Float64 delay9(x)
Float64 x;
{
int i;
Float64 z9;
z9 = w9[D9];
w9[0] = x;
176
for (i = D9; i>=1; i--)
{
w9[i] = w9[i-1];
}
return z9;
}
/*------------------------------------------------------------------------Subroutine delay10()
- phase delay compensation
-------------------------------------------------------------------------*/
Float64 delay10(x)
Float64 x;
{
int i;
Float64 z10;
z10 = w10[D10];
w10[0] = x;
for (i = D10; i>=1; i--)
{
w10[i] = w10[i-1];
}
return z10;
}
/**************************************************************************
Subroutine listing for routine extension_pq_theorem()
**************************************************************************/
/*------------------------------------------------------------------------Subroutine delay4()
- delay vsource_adc with 90 degree
-------------------------------------------------------------------------*/
Float64 delay4(x)
Float64 x;
{
int i;
Float64 z;
z = w4[D4];
w4[0] = x;
for (i = D4; i>=1; i--)
{
w4[i] = w4[i-1];
}
177
return z;
}
/*------------------------------------------------------------------------Subroutine fir5()
- 2nd-order LPF, fc = 5 Hz, G = 0.5
-------------------------------------------------------------------------*/
Float64 fir5(x)
Float64 x;
{
int i, K;
Float64 y = 0;
M5 = 2;
L5 = 2;
K = (L5 <= M5) ? M5 : L5;
w5[0] = x;
a5[0] = 1.0;
a5[1] = -1.995551847;
a5[2] = 0.995561717;
b5[0] = 2.467776264e-6;
b5[1] = 2 * 2.467776264e-6;
b5[2] = 2.467776264e-6;
for (i=1; i<=M5; i++)
{
w5[0] -= a5[i] * w5[i];
}
for (i=0; i<=L5; i++)
{
y += b5[i] * w5[i];
}
for (i=K; i>=1; i--)
{
w5[i] = w5[i-1];
}
return y;
}
/* Input adder */
/* Output adder */
/* Reverse-order updating */
178
/*------------------------------------------------------------------------Subroutine fir6()
- 2nd-order LPF, fc = 5 Hz, G = 0.5
-------------------------------------------------------------------------*/
Float64 fir6(x)
Float64 x;
{
int i, K;
Float64 y = 0;
M6 = 2;
L6 = 2;
K = (L6 <= M6) ? M6 : L6;
w6[0] = x;
a6[0] = 1.0;
a6[1] = -1.995551847;
a6[2] = 0.995561717;
b6[0] = 2.467776264e-6;
b6[1] = 2 * 2.467776264e-6;
b6[2] = 2.467776264e-6;
for (i=1; i<=M6; i++)
{
w6[0] -= a6[i] * w6[i];
}
for (i=0; i<=L6; i++)
{
y += b6[i] * w6[i];
}
for (i=K; i>=1; i--)
{
w6[i] = w6[i-1];
}
return y;
}
/* Input adder */
/* Output adder */
/* Reverse-order updating */
179
/*------------------------------------------------------------------------Subroutine fir7()
- 2nd-order LPF, fc = 5 Hz, G = 0.5
-------------------------------------------------------------------------*/
Float64 fir7(x)
Float64 x;
{
int i, K;
Float64 y = 0;
M7 = 2;
L7 = 2;
K = (L7 <= M7) ? M7 : L7;
w7[0] = x;
a7[0] = 1.0;
a7[1] = -1.995551847;
a7[2] = 0.995561717;
b7[0] = 2.467776264e-6;
b7[1] = 2 * 2.467776264e-6;
b7[2] = 2.467776264e-6;
for (i=1; i<=M7; i++)
{
w7[0] -= a7[i] * w7[i];
}
for (i=0; i<=L7; i++)
{
y += b7[i] * w7[i];
}
for (i=K; i>=1; i--)
{
w7[i] = w7[i-1];
}
return y;
}
/* Input adder */
/* Output adder */
/* Reverse-order updating */
180
/*------------------------------------------------------------------------Subroutine fir11()
- 2nd-order LPF, fc = 2 kHz, G = 0.5
-------------------------------------------------------------------------*/
Float64 fir11(x)
Float64 x;
{
int i, K;
Float64 y = 0;
M11 = 2;
L11 = 2;
K = (L11 <= M11) ? M11 : L11;
w11[0] = x;
a11[0] = 1.0;
a11[1] = -0.368188532;
a11[2] = 0.1956396086;
b11[0] = 0.2068627691;
b11[1] = 2 * 0.2068627691;
b11[2] = 0.2068627691;
for (i=1; i<=M11; i++)
{
w11[0] -= a11[i] * w11[i];
}
for (i=0; i<=L11; i++)
{
y += b11[i] * w11[i];
}
for (i=K; i>=1; i--)
{
w11[i] = w11[i-1];
}
return y;
}
/* Input adder */
/* Output adder */
/* Reverse-order updating */
181
/*------------------------------------------------------------------------Subroutine fir12()
- 2nd-order LPF, fc = 2 kHz, G = 0.5
-------------------------------------------------------------------------*/
Float64 fir12(x)
Float64 x;
{
int i, K;
Float64 y = 0;
M12 = 2;
L12 = 2;
K = (L12 <= M12) ? M12 : L12;
w12[0] = x;
a12[0] = 1.0;
a12[1] = -0.368188532;
a12[2] = 0.1956396086;
b12[0] = 0.2068627691;
b12[1] = 2 * 0.2068627691;
b12[2] = 0.2068627691;
for (i=1; i<=M12; i++)
{
w12[0] -= a12[i] * w12[i];
}
for (i=0; i<=L12; i++)
{
y += b12[i] * w12[i];
}
for (i=K; i>=1; i--)
{
w12[i] = w12[i-1];
}
return y;
}
/* Input adder */
/* Output adder */
/* Reverse-order updating */
182
/*------------------------------------------------------------------------Subroutine fir13()
- 2nd-order LPF, fc = 2 kHz, G = 0.5
-------------------------------------------------------------------------*/
Float64 fir13(x)
Float64 x;
{
int i, K;
Float64 y = 0;
M13 = 2;
L13 = 2;
K = (L13 <= M13) ? M13 : L13;
w13[0] = x;
a13[0] = 1.0;
a13[1] = -0.368188532;
a13[2] = 0.1956396086;
b13[0] = 0.2068627691;
b13[1] = 2 * 0.2068627691;
b13[2] = 0.2068627691;
for (i=1; i<=M13; i++)
{
w13[0] -= a13[i] * w13[i];
}
for (i=0; i<=L13; i++)
{
y += b13[i] * w13[i];
}
for (i=K; i>=1; i--)
{
w13[i] = w13[i-1];
}
return y;
/* Input adder */
/* Output adder */
/* Reverse-order updating */
}
/**************************************************************************
Subroutine listing for routine phase_lock_loop()
**************************************************************************/
/*------------------------------------------------------------------------Subroutine reset_integ1()
- avoid saturation of integral, integ1()
-------------------------------------------------------------------------*/
183
reset_integ1()
{
n2++;
if(n2 == 200)
{
w2[0] = 0;
y1_c1 = y1_c;
n2 = 0;
}
/* Reset integ1() */
a1[0] = 1.0;
a1[1] = -1.91109177;
a1[2] = 0.914879321;
/* Filter coefficient */
b1[0] = 9.46887707e-4;
b1[1] = 2 * 9.46887707e-4;
b1[2] = 9.46887707e-4;
/* Filter coefficient */
184
/* Input adder */
/* Output adder */
/* Reverse-order updating */
}
/*------------------------------------------------------------------------Subroutine pll()
- reference sinewave signal generation
-------------------------------------------------------------------------*/
Float64 pll(x)
Float64 x;
{
int i, K;
double y = 0;
M3 = 2;
L3 = 2;
K = (L3 <= M3) ? M3 : L3;
w3[0] = x;
a3[0] = 1.0;
a3[1] = -1.822754277;
a3[2] = 0.837203188;
/* Filter coefficient */
b3[0] = 0.0;
b3[1] = 0.177245723;
b3[2] = -0.162796812;
/* Filter coefficient */
/* Input adder */
185
{
y += b3[i] * w3[i];
/* Output adder */
}
for (i=K; i>=1; i--)
{
w3[i] = w3[i-1];
}
/* reverse-order updating */
return y;
}
/**************************************************************************
Routine phase_lock_loop()
**************************************************************************/
phase_lock_loop()
{
vsource_adc1 = 450.4896276 * ds1104_adc_read_ch(5);
/* Read current ADC5 input of vsource */
y1_a = 1.414093802 * fir1(vsource_adc1);
vpll = pll(y1_a);
/* Using fir1() */
/* Using pll() */
/* Using integ1() */
reset_integ1();
/* Using reset_integ1() */
186
vcap_adc = 450.4896276 * ds1104_adc_read_ch(2);
/* Read current ADC2 input of DC-bus voltage */
if (vcap_adc >= 200)
{
enable4 = 1;
}
else
{
enable4 = 0;
}
187
Pload_dc = fir5(Pload);
/* Using fir5() */
Qload_dc = fir6(Qload);
/* Using fir6() */
Qhpf_dc = fir7(Qhpf);
/* Using fir7() */
}
/**************************************************************************
Routine compensating_current_ref()
**************************************************************************/
compensating_current_ref()
{
sine_ref_90deg = delay8(sine_ref_syn);
/* 90-degree phase shift of sine_ref */
ip_load = 1.414213562 * Pload_dc / vs_rms * sine_ref_syn;
/* Active component of load current */
iq_load = 1.414213562 * Qload_dc / vs_rms * sine_ref_90deg;
/* Reactive component of load current */
ihpw_load = iload_adc - iq_load - ip_load;
/* Harmonic component of load current */
ic_load = iq_load + ihpw_load;
/* Load's compensation current reference */
iq_hpf = 1.414213562 * Qhpf_dc / vs_rms * sine_ref_90deg;
/* Reactive component of HPF current */
ipv_ref = ipv * sine_ref_syn;
/* Active component of DC source current */
ic_ref2 = ic_load + iq_hpf + ipv_ref;
/* Compensation current + DC source current */
ic_ref1 = -1 * delay10(ic_ref2);
/* Phase delay compensation */
if(ic_ref1 >= 7.0)
ic_ref = 7.0;
/* Over current protection, upper limit = 7.0 A */
else if(ic_ref1 <= -7.0)
ic_ref = -7.0;
/* Over current protection, lower limit = -7.0 A */
else
ic_ref = ic_ref1;
188
is_compensated = iload_adc + ihpf_adc - ic_ref;
/* Calculated compensated source current (ideal case) */
if (iselect == 0)
iref_out = sine_ref_syn;
else if (iselect == 1)
iref_out = ip_load;
else if (iselect == 2)
iref_out = iq_load;
else if (iselect == 3)
iref_out = ihpw_load;
else if (iselect == 4)
iref_out = iq_hpf;
else if (iselect == 5)
iref_out = ic_load;
else if (iselect == 6)
iref_out = ic_ref;
ds1104_dac_write(5, iref_out / 10);
/* DAC5 output signal selection */
ds1104_dac_strobe();
/* Activate the previously written DAC values synchronously */
}
/**************************************************************************
Routine system_fault_protection()
**************************************************************************/
system_fault_protection()
{
if (enable1 == 1 && enable2 == 1 && enable3 == 1 && enable4 == 1)
{
ds1104_bit_io_set(DS1104_DIO11);
/* Sets I/O port 11 to '1' */
}
else
{
ds1104_bit_io_clear(DS1104_DIO11);
}
}
189
/**************************************************************************
Routine error_hook_function()
- is activated when an error message is generated
**************************************************************************/
int error_hook_function(msg_submodule_type sm, msg_no_type no)
{
enable1 = 0;
return(1);
}
/**************************************************************************
Interrupt service routine 0, isr_srt0()
- Hysteresis current controller
**************************************************************************/
isr_srt0()
{
RTLIB_TIC_START();
ds1104_adc_start(DS1104_ADC5);
190
/**************************************************************************
Interrupt service routine 1, isr_srt1()
- Reference sinewave generation
- Compensation Current Reference and DC source Current estimation
**************************************************************************/
isr_srt1()
{
ts_timestamp_type ts;
/* Time stamping function */
ds1104_begin_isr_timer1();
RTLIB_TIC_START();
/* Overload check */
/* Start execution time 1 measurement */
ds1104_adc_start(DS1104_ADC1|DS1104_ADC2|DS1104_ADC3|DS1104_ADC4);
/* Start Mux ADC & 12-bit's ADC simultaneously */
phase_lock_loop();
extension_pq_theorem();
/* Using phase_lock_loop() */
/* Using extension_pq_theorem() */
compensating_current_ref();
/* Using compensating_current_ref() */
system_fault_protection();
/* Using system_fault_protection() */
ts_timestamp_read(&ts);
host_service(1, &ts);
/* Data acquisition service using time stamping */
exec_time1 = RTLIB_TIC_READ();
ds1104_end_isr_timer1();
/* Overload check */
}
/**************************************************************************
Main Program
**************************************************************************/
void main()
{
/* Variables Initialisation */
n1 = 0;
n2 = 0;
Pload = 1;
Qload = 1;
Qhpf = 1;
/* Initialise arrays of fir1() */
a1 = (Float64 *)calloc(3, sizeof(Float64));
191
b1 = (Float64 *)calloc(3, sizeof(Float64));
w1 = (Float64 *)calloc(3, sizeof(Float64));
/* Initialise arrays of integ1() */
w2 = (Float64 *)calloc(1, sizeof(Float64));
/*
a3
b3
w3
Initialise
= (Float64
= (Float64
= (Float64
arrays of pll() */
*)calloc(3, sizeof(Float64));
*)calloc(3, sizeof(Float64));
*)calloc(3, sizeof(Float64));
Initialise
= (Float64
= (Float64
= (Float64
arrays of fir5() */
*)calloc(3, sizeof(Float64));
*)calloc(3, sizeof(Float64));
*)calloc(3, sizeof(Float64));
/*
a6
b6
w6
Initialise
= (Float64
= (Float64
= (Float64
arrays of fir6() */
*)calloc(3, sizeof(Float64));
*)calloc(3, sizeof(Float64));
*)calloc(3, sizeof(Float64));
/*
a7
b7
w7
Initialise
= (Float64
= (Float64
= (Float64
arrays of fir7() */
*)calloc(3, sizeof(Float64));
*)calloc(3, sizeof(Float64));
*)calloc(3, sizeof(Float64));
192
w13 = (Float64 *)calloc(3, sizeof(Float64));
/* DS1104 and RTLib1104 initialization */
init();
/* Announce the hook function to the message module */
msg_error_hook_set(error_hook_function);
/* Sets bits I/O 5, I/O 11 and I/O 17 to output */
ds1104_bit_io_init(DS1104_DIO5_OUT|DS1104_DIO11_OUT|DS1104_DIO17_OUT);
/* Sets the bits I/O 5, I/O 11 and I/O 17 to '0' */
ds1104_bit_io_clear(DS1104_DIO5|DS1104_DIO11|DS1104_DIO17);
/* Initialize DAC in latched mode */
ds1104_dac_init(DS1104_DACMODE_LATCHED);
/* Start timer0 with service routine isr_srt0() */
ds1104_start_isr_timer0(ST0, isr_srt0);
/* Start timer1 with interrupt service routine isr_srt1() */
ds1104_start_isr_timer1(ST1, isr_srt1);
/* Message generation */
msg_info_set(MSG_SM_USER, 0, "System Started.");
/* Background service */
while(1)
{
RTLIB_BACKGROUND_SERVICE();
}
}
H.2
_floating_point_type(64,IEEE)
_integer_type(32)
-- signals available for ControlDesk
--- signal name
type address
group "Model Root in ""DS1104.c"""
193
flt (64,IEEE)
"Execution Time 0"
READONLY
endgroup
group "Execution Time 1"
exec_time1
{
type:
alias:
flags:
}
flt (64,IEEE)
"Execution Time 1"
READONLY
endgroup
group "Signals of Phase-Lock Loop"
vsource_adc
vs_rms
sine_ref
y1_a
flt
flt
flt
flt
endgroup
group "Signals of Extension P-Q Theorem"
iload_adc
ihpf_adc
Pload
Pload_dc
Qload
Qload_dc
Qhpf
Qhpf_dc
flt
flt
flt
flt
flt
flt
flt
flt
endgroup
group "Signals of Compensation Current Reference"
sine_ref_syn
sine_ref_90deg
ip_load
iq_load
flt
flt
flt
flt
194
ihpw_load
iq_hpf
ic_load
ic_ref
is_compensated
flt
flt
flt
flt
flt
endgroup
group "Signals of Hysteresis Current Controller"
icomp_adc
i_hysteresis
enable1
enable2
enable3
enable4
flt
flt
int
int
int
int
endgroup
group "Signals of DC-Bus Voltage Regulation"
vcap_adc
flt
endgroup
group "Signals of DC Source Current"
ipv
ipv_ref
flt
flt
endgroup
group "Current Signal at DACH5"
iselect
endgroup
endgroup
int
196
I. INTRODUCTION
197
predictions of the proposed configuration will be presented.
Fig. 2. Overall system configuration and control block diagram.
2 I L ,n sin (nt + n )
(1)
n =1
(2)
ihp (t ) = 2 I hp ,n sin t + 90 o
(3)
2V
PCC I L ,n
n=2
= pL + ~
pL
(4)
The instantaneous reactive power of nonlinear load can be
written as follows:
'
(t ) iL (t )
q L (t ) = v PCC
= VPCC I L,1 sin ( 1 ) VPCC I L,1 sin (2t + + 1 )
2V
n=2
PCC I L ,n
= q L + q~L
(5)
The instantaneous reactive power of HPF can be calculated as
198
'
(t ) ihp (t )
q hp (t ) = v PCC
hp
'
(t ) denotes
and ~
php denote the variant component, and v PCC
qL
u t 90o
VPCC
(8)
i L,h (t ) = i L (t ) i L , p (t ) i L,q (t )
(9)
and
ihp , q (t ) = 2
qhp
VPCC
u t 90o
(10)
is DC-bus
decreases linearly.
When the compensation current sample i f tries to go
beyond the upper hysteresis band, S1 is turned on
and S 2 is turned off, then i f increases linearly.
199
Fig. 5. Equivalent circuit of HPF for harmonics.
factor close to 0.7. In Fig. 6, the filtering performance of highorder harmonics above 1 kHz is improved with HPF.
s
s
o
s
+ 1
p
1 s
+
Q o
+ 1
(12)
In (12),
A=
1
, o =
C
1
Lhp C hp
, p =
Rhp
Lhp
, Q = Rhp
C hp
Lhp
H cs (s )
from the
is ,h (s )
i L ,h (s )
Z hp (s )
Z s (s ) + Z hp (s )
(13)
200
the PV arrays power is successfully provided to the load and
utility.
(a)
(a)
(b)
Fig. 7. Simulated results without harmonic compensation, (a) source voltage
and (b) source current waveforms.
(b)
Fig. 9. Simulated results with proposed scheme. (a) source voltage and (b)
source current waveforms.
(a)
(a)
(b)
Fig. 8. Simulated results with shunt APF. (a) source voltage and (b) source
current waveforms.
(b)
Fig. 10. Simulated results with the proposed scheme in a case of step load
change. (a) source voltage and (b) source current.
201
TABLE II
HARMONIC CURRENT COMPONENTS
[2]
n
5
7
11
13
17
19
23
25
29
31
35
37
THD2 kHz
THD20 kHz
Load
iL(n) / iL(1)
[%]
39.95
13.40
6.31
3.51
2.21
1.88
1.19
1.14
0.82
0.70
0.57
0.47
76.83
Basic APF
is(n) / is(1)
[%]
1.60
1.55
1.26
0.91
0.55
0.48
0.22
0.14
0.22
0.26
0.11
0.02
3.58
4.39
Proposed Scheme
is(n) / is(1)
[%]
1.63
0.07
0.61
0.69
0.79
0.68
0.43
0.32
0.06
0.03
0.15
0.15
3.19
3.21
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
(a)
[12]
[13]
[14]
(b)
Fig. 11. Simulated results for the proposed scheme with 300 W active power
generation from PV arrays. (a) source voltage and (b) source current.
IV. CONCLUSION
A new single-phase two-wire hybrid APF configuration
that interconnects the hybrid APF with the PV system is
presented. The proposed scheme combines the APF with the
passive filter to improve the filtering performance of highorder harmonics. Furthermore, the proposed scheme can deal
with PV power. The derivation of compensation current
reference is simpler and clearer with the utilization of
extension p-q theorem. The simulation results show the
effectiveness of the proposed scheme for wideband harmonics
compensation and PV power handling capability.
V. REFERENCES
[1]
203
I.
INTRODUCTION
PRINCIPLE OF OPERATION
204
The VSI and the PV array are connected in parallel with the
DC-bus capacitor. In the proposed scheme, the low-order
harmonics are compensated using the shunt APF, while the
high-order harmonics are filtered by the passive HPF. It is
envisaged that this configuration is effective to improve the
filtering performance of high-order harmonics, thus achieving
wideband harmonic compensation.
The VSI is operated in the current-controlled mode (CCM).
Furthermore, the proposed hybrid APF with PV system is
connected with the distribution line at the point of common
coupling (PCC) through a filter inductor, allowing the reactive
power control. Fig. 2 shows the control system for the
proposed hybrid APF with PV system. The compensated
source current is desired to be sinusoidal to yield a maximum
power factor (PF). The extension p-q theorem is introduced to
derive the compensation current reference.
Figure 1
n =1
(1)
(2)
i hp (t ) = 2 I hp,n sin t + 90 o .
(3)
(4)
= q L + q~L .
(5)
205
The instantaneous reactive power of HPF can be calculated as
'
q hp (t ) = v PCC
(t ) i hp (t )
= q hp + q~hp ,
(6)
p L , q~L
where p L , q L and p hp represent the constant part, ~
'
(t ) denotes
and ~
p hp denote the variant component, and v PCC
pL
V PCC
qL
iL,q (t ) = 2
VPCC
u (t ) ,
(7)
u t 90o ,
(8)
i L,h (t ) = i L (t ) i L, p (t ) i L,q (t ) ,
(9)
H hp (s ) = Z hp (s ) =
i hp,q (t ) = 2
V PCC
u t 90 o ,
(10)
u (t ) ,
(11)
where PPV is the active power of PV array, I Cf is the DCbus capacitor charging current, and VCf ,ref
+ 1 . (12)
A=
1
, o =
C hp
1
Lhp C hp
, p =
R hp
Lhp
, Q = R hp
C hp
Lhp
1 s
+
Q o
In (12),
and
q hp
s
s
o
+ 1
s
p
is DC-bus
206
Higher Q factors allow more series resonant attenuation and
less high-pass. By contrast, lower Q factors provide less series
resonant attenuation and greater high-pass response. Hence, the
proper selection of Q is essentially required to satisfy the
series resonant and high-pass response performances. In this
work, the Q factor was selected as 0.69, considering the
required high-pass response over a wide frequency band.
After the hybrid APF with PV system is configured and
Z hp (s ) is known, the distribution system current to injected
i s ,h (s )
i h (s )
Z hp (s )
Z hp (s ) + Z s (s )
(13)
Figure 4. Bode magnitude diagram of the transfer function H cds (s ) for the
proposed hybrid APF system.
III.
EXPERIMENTAL RESULTS
Distribution Voltage
Source Inductance
Ls = 0.76 mH
Cd = 1000 F
Lsmooth = 1.15 mH
fsw,max = 10 kHz
H = 1.0 Apeak-to-peak
APF Inductor
Lf = 10.0 mH
Cf = 1000 F
HPF Inductor
Lhp = 1.76 mH
HPF Capacitor
Chp = 8.8 F
HPF Resistor
Rhp = 10
Load Resistor
RL = 250
207
Figure 5(a)
FigureFundamental
5(b)
is
Figure 5. Experimental
results without compensation, (a) source current waveform and (b) source(b)
current spectra.
(a)
Figure 6(a)
Figure 6(b)
Fundamental
is
Figure 6. Experimental
results with basic shunt APF, (a) source current waveform and (b) source(b)
current spectra.
(b)
Figure 7(a)
Figure 7(b)
Fundamental
is
Figure 7. Experimental
results with proposed scheme, (a) source current waveform and (b) source(b)
current spectra.
(a)
Figure 8(a)
Figure 8(b)
iL
iL
is
is
208
IV.
CONCLUSION
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
IEEE Trans. on Industry Applications, vol. 31, no. 3, pp. 590-597, MayJune 1995.
S. Khositkasame and S. Sangwongwanich, Design of harmonic current
detector and stability analysis of a hybrid parallel active filter, in Proc.
Power Conversion Conference, PCC, 1997, Nagaoka, Japan, vol. 1, pp.
181-186.
M. Routimo, M. Salo, and H. Tuusa, A novel control method for
wideband harmonic compensation, in Proc. IEEE International
Conference on Power Electronics and Drive Systems, PEDS, 2003,
Singapore, vol. 1, pp. 799-804.
S. R. Bull, Renewable energy today and tomorrow, in Proc. of the
IEEE, vol. 89, no. 8, pp. 1216-1226, Aug. 2001.
S. Kim, G. Yoo, and J. Song, A bifunctional utility connected
photovoltaic system with power factor correction and U.P.S. facility, in
Proc. IEEE Photovoltaic Specialist Conference, 1996, Washington,
USA, pp. 1363-1368.
Y. Komatsu, Application of the extension pq theory to a mains-coupled
photovoltaic system, in Proc. Power Conversion Conference, PCC,
2002, Osaka, Japan, vol. 2, pp. 816-821.
T. F. Wu, C. L. Shen, C. H. Chang, and J. Y. Chiu, 1/spl phi/ 3W
grid-connection PV power inverter with partial active power filter,
IEEE Trans. on Aerospace and Electronic Systems, vol. 39, no. 2, pp.
635-646, April 2003.
Y. Komatsu and T. Kawabata, Characteristics of three phase active
power filter using extension pq theory, in Proc. IEEE International
Symposium on Industrial Electronics, ISIE, 1997, Guimaraes, Portugal,
vol. 2, pp. 302-307.
B. Dobrucky, H. Kim, V. Racek, M. Roch, and M. Pokorny, Singlephase power active filter and compensator using instantaneous reactive
power method, in Proc. Power Conversion Conference, PCC, 2002,
Osaka, Japan, vol. 1, pp. 167-171.
P. C. Tan and Z. Salam, A new single-phase two-wire hybrid active
power filter using extension p-q theorem for photovoltaic application,
in Proc. National Power and Energy Conference, PECon, 2004,
Malaysia, pp. 126-131.
J. K. Phipps, A transfer function approach to harmonic filter design,
IEEE Industry Applications Magazine, vol. 3, no. 2, pp. 68-82, Mar.Apr. 1997.
APPENDIX K
210
Abstract
Due to the proliferation of nonlinear and switching loads from
power electronics converters, there is an increasing concern to
control and reduce the harmonic currents in distribution
power lines. These types of loads draw nonsinusoidal currents
from the mains, causing harmonic distortion. One of the
methods to reduce the problem is by using the power
electronics approach. This paper presents a single-phase
hybrid active power filter connected to a photovoltaic array.
The uniqueness of the proposed scheme is the fact that it
improves the filtering performance of the conventional shunt
active power filter, as well as simultaneously supplies the
power from the photovoltaic array to the load. The
compensation current reference estimation is based on the
extension
instantaneous
reactive-power
theorem.
Experimental results obtained from a laboratory system that
verifies the viability and effectiveness of the proposed scheme
are presented.
1 Introduction
Remarkable progress in power electronics had spurred
interest in active power filter (APF) for harmonic distortion
mitigation [1,3,5,7,8,9]. Digital controller using digital signal
processor (DSP) or microprocessor is preferable for APF
application, primarily due to its flexibility and immunity to
noise signals [1,3,8]. However, it is known that for digital
methods, the high order harmonics are not filtered effectively.
This is due to the hardware limitation of sampling rate in realtime application. Moreover, the utilisation of fast switching
transistors in APF application causes switching frequency
noise appears in the compensated source current [4]. This
switching frequency noise required additional filtering to
prevent interference with other sensitive equipment.
The idea of hybrid APF has been proposed by several
researchers [6,11,14]. In this scheme, a low cost passive highpass filter (HPF) is used in addition to the conventional APF.
The harmonic filtering task is divided between the two filters.
The APF cancels the lower order harmonics, while the HPF
211
Distribution
voltage
vu
2:1
Source
voltage
Ls
vs PCC
is
240 Vrms
50Hz
Lsmooth
Nonlinear load
iL
Rhp
Lhp
Cd
RL
ihp
Chp
Passive
HPF
PV array
Shunt APF
if
Lf
S1
S3
VCf
S2
S4
Cf
3 Operation principle
As illustrated by Figure 2, the operation principle of the
proposed hybrid APF is that it generates compensation
current (if) equal and opposite in polarity to the reactive load
current (iL,q), harmonic load current (iL,h) and reactive HPF
current (ihp,q). This compensation current is injected into the
PCC through an interfacing inductor. The compensated
source current (is) is desired to be sinusoidal and in phase
with the source voltage (vs) to yield a maximum power factor.
is = iL,p + ihp,p - iPV
VCf
PI controller
iL,q
iL,h
+
+
+
ihp,q _
pL
_ LPF
qL
_
LPF
qhp
LPF
2:1
is
vs PCC
iL
Nonlinear load
if,ref 1
Gating
signals
S1
S2
S3
S4
if
+ if,ref
_
pL+ p~L
_ ~
q + qL p , q & q
L L
hp
_L
qhp+ q~hp calculator
iL
ihp
vs
-90o
PLL
DSP Based Implementation
240 Vrms
50Hz
Passive
HPF
sin( t)
Hysteresis
current
controller
IPV
if,ref 2
cos(t)
vu
+
_
ICf
Compensation
current
estimator
PPV
VCf,ref
DC-bus Voltage
VCf,ref Controller
if
Shunt APF
PV Array
+
ihp = ihp,p + ihp,q + isw
212
Compensation current reference estimation for the singlephase APF based on extension p-q theorem has been presented
in [16]. In this work, the application of the theorem is further
extended to a single-phase hybrid APF connected to a PV
array.
For a single-phase system with nonlinear load, the load current
can be represented as
2 I L,n sin(nt + n ) .
(3)
(4)
(5)
(6)
pL , q~L
where pL , qL and php represent the constant part, ~
and ~
php denote the variant component, and v s' (t ) denotes the
qL
u (t 90o ) ,
Vs
iL, h (t ) = iL (t ) iL , p (t ) iL, q (t ) ,
(8)
(9)
ihp , q (t ) = 2
qhp
Vs
u (t 90o ) ,
(10)
(1)
n =1
v s (t ) = 2Vs sin(t + ) .
iL, q (t ) = 2
and
i L (t ) =
By obtaining the constant part in Equation (4), (5) and (6), the
active (iL,p), reactive (iL,q) and harmonics (iL,h) components of
load current and the reactive (ihp,q) component of the passive
HPF current can be readily calculated as follows:
p
(7)
iL , p (t ) = 2 L u (t ) ,
Vs
5 Experimental results
The proposed hybrid APF connected to a PV array was tested
in the laboratory with a low-power experimental prototype as
shown in Figure 4. The VSI was built using 1200 V, 25 A
IGBTs. The control system was implemented using a
dSPACE DS1104 DSP board. For the experimental system,
the leakage impedance of the transformer is assumed to be the
source impedance (Ls = 0.76 mH). The passive HPF is tuned
to the resonant frequency of 1.28 kHz. The design parameters
of the HPF are: Lhp = 1.76 mH, Chp = 8.8 F and Rhp = 10 .
A full-bridge diode rectifier with DC smoothing capacitor
(Cd), resistive load (RL) and AC smoothing inductor (Lsmooth)
was used as the nonlinear load. Other prototype parameters
are shown in Table 1.
Distribution Voltage
Cd = 1000 F
Lsmooth = 1.15 mH
fsw,max = 10 kHz
H = 1.0 Apeak-to-peak
APF Inductor
Lf = 10.0 mH
Cf = 990 F
Load Resistor
RL = 250
213
1
4
is
is
Fundamental
214
iL
is
(a) Scales: load current 2 A/div, source current 2 A/div, time 4 ms/div
iL
is
(b) Scales: load current 2 A/div, source current 2 A/div, time 4 ms/div
6 Conclusion
A single-phase hybrid APF connected to a PV array is
presented. The proposed scheme combines the APF with a
passive filter to improve the filtering performance of highorder harmonics. The compensation current reference
estimation is simpler with the utilisation of extension p-q
theorem. The experimental results show the effectiveness of
the proposed scheme for wideband harmonics compensation
and PV power handling capability.
Acknowledgements
This project was supported by the Intensification of Research
in Priority Areas (IRPA) grant from the Ministry of Science,
Technology and Innovation (MOSTI), Malaysia.
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filters for thyristor rectifiers to comply with IEC-10003-2 standards, IEEE Trans. on Industry Applications,
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suppression in distribution systems, in Proc. of the
IEEE Power Engineering Society Summer Meeting, vol.
2, pp. 800-805, (2000).