Escolar Documentos
Profissional Documentos
Cultura Documentos
Welcome
Contents
Page 5
Thierry Colette
> Interview
Page 7
Key Figures
Page 9
Scientific Activities
Page 11
Architecture & IC Design
for RF & mmW
Page 21
Architecture & IC Design
for Image Sensors
Page 31
Architecture, IC Design
& Control for Digital
SoCs
Page 49
Architecture & IC Design
for Emerging
Technologies
Page 57
Embedded Software
Page 69
Reliability & Test
Page 77
PhD Degrees Awarded
CEA-Leti / L. Godart
30 years ago, with the microelectronic revolution, raised the communication new age.
In parallel began another one: the computing science revolution. Now, we move into a
new one, which is finally the synthesis of both. With the success of the Internet, and the
new needs, e.g. in health, transportation or security, more and more computing devices
are being smart and connected, leading to new research fields: the efficient big data
management, and the integration of hardware and software know-how inside integrated
embedded systems. Furthermore, what we assist today with smartphones, tablets or
onboard computers, will be widely spread to many kinds of devices: the Internet of
Things is emerging.
Our multidisciplinary platform dedicated to Integrated Circuit Design and Embedded
Software, allows us to address this new trend. By joining these two fields of know-how,
CEA is the one of first research organization in Europe to support such an original and
global offer to the industry providing a wide range of capabilities, oriented towards the
applicative analysis and the exploration of integrated embedded architectures.
This platform includes the tools, methods and human competencies from front-end &
back-end integrated circuit design (digital, analog & mixed) in the most advanced
technologies, complex circuit emulation, hardware/software integration, to
industrial test and reliability.
We hope reading this scientific report will convince you that this wide spectrum platform
brings specific innovations, creating new opportunities to fulfill our first mission: support
and promote the industry by innovation and technology transfer.
Thierry Collette
3 locations:
MINATEC campus (Grenoble)
Integration Research Center (Gires)
PARIS-SACLAY Campus (Palaiseau)
34M budget
85% funding from contracts
37 granted patents
29 papers, journals & books
136 conferences & workshops
Scientific Activity
Publications
165 publications in 2012, including journals and Top conferences like ISSCC, VLSI Circuits
Symposium, DAC, DATE, PIERS, ESSCIRC, RTSS and ESWeek.
Experts
31 CEA experts: 2 research directors, 2 international experts
9 Researchers with habilitation qualification (to independently supervise doctoral candidates)
2 IEEE Senior Members
Scientific Committees
Editorial Boards: Journal of Low Power Electronics,
19 members of Technical Programs and Steering Committees in major conferences: ISSCC,
ESSCIRC, DAC, DATE, ESWEEK, RTNS, IJCNN, IWANN, EMSOFT
Normalization committee: AUTOSAR (Automoive Open System Architecture)
International Collaborations
Collaborations with more than 20 universities and institutes worldwide
Caltech, University of Berkeley, University of Columbia, Carnegie Mellon University, EPFL, CSEM,
UCL, Polito Torino, KIT, Chalmers University, Tongji, .
10
11
Architecture &
IC Design
For RF & mmW
12
References:
[1] Berder O., Sentieys O., Le T. N., Fontaine R., Pegatoquet A., Belleudy C., Auguin M., Tatinian W., Jacquemod G., Broekaert F., Didioui A.,
Bernier C., Benchehida K., Bourdel S., Barthelemy H., Ciais P. & Barratt C., "GRECO: GREen communicating objects." Design and Architectures
for Signal and Image Processing (DASIP), 2012 Conference on: 1-2.
[2] Didioui A., Bernier C., Morche D. & Sentieys O., "Impact of RF front-end nonlinearity on WSN Communications.", 2012 9th International
Symposium on Wireless Communication Systems, ISWCS 2012, 28 August 2012 - 31 August 2012: 875-879.
13
ADC
LO1I
ADC
LO1Q
ADC
Out_II
LO2I
LO2Q
LNA
Out_IQ
Out_QI
LO2I
LO2Q
ADC
Out_QQ
References :
[1] G.Masson et al. A 1 nJ/b 3.2-to-4.7 GHz UWB 50 Mpulses/s Double Quadrature Receiver for Communication and Localization ESSCIRC
2010
[2] Farid Bautista et al. UWB Beamforming Architecture for RTLS applications using Digital Phase-Shifters ISCAS 2011 - Rio de Janeiro
[3] Farid Bautista, Dominique Morche, Franois Dehmas and Gilles Masson "Low power beamforming RF architecture enabling fine ranging and
AOA techniques ICUWB' 2011
[4] Farid Bautista, Dominique Morche, Serge Bories, Gilles .Masson Antenna Characteristics and Ranging Robustness with Double Quadrature
Receiver and UWB Impulse Radio ICUWB 2012
[5]D.Morche, M.Pelissier, G.Masson, P.Vincent UWB : Innovative Architectures Enable Disruptive Low Power Wireless Applications DATE
2012
[6] S.Bourdel, G.Gielen, S.Damico, D.Wisland, B.Busze, D.Neyrinck, J.Jantunen D.Morche Advanced Tutorial on UWB Circuits and Systems
Workshop at ESSCIRC 2012
14
References :
[1] D. Gmez, C. Dufis, J. Altet, D. Mateo, J. L. Gonzlez, Electro-thermal coupling analysis methodology for RF circuits, Microelectronics
Journal, Vol. 43, No. 9, September 2012, pp 633641.
[2] J.L. Gonzlez, B. Martineau, D. Mateo, and J. Altet, Non-invasive monitoring of CMOS power amplifier operating at RF and mmW
frequencies using and on-chip thermal sensor, 2011 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers, pp.1-4, 57 June 2011.
[3] Deltimple N., Gonzlez J.L., Altet J., Luque Y., & Kerherv E., "Design of a fully integrated CMOS self-testable RF power amplifier using a
thermal sensor." in Proceedings of the 38th European Solid State Circuits Conference, ESSCIRC 2012, 17 September 2012 - 21 September
2012: 398-401.
15
References :
[1] A. Giry, G. Tant, Y. Lamy, C. Raynaud, P. Vincent, A Monolithic Watt-level SOI LDMOS Linear Power Amplifier with Through Silicon Via,
2013 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR), 20-23 Jan. 2013
[2] http://www.leti.fr/en/How-to-collaborate/Collaborating-with-Leti/Open-3D
[3] L. Dussopt, M.A.C Niamien, A. Giry, A. Chebihi, S. Contal, F. Fraysse, S. Aissa, O. Perrin, C. Delaveaud, "Enhanced-efficiency front-end
module with multi-standard impedance-tunable antenna," IEEE 17th International Workshop on Computer Aided Modeling and Design of
Communication Links and Networks (CAMAD), pp.328-332, 17-19 Sept. 2012
16
References :
[1] A. Siligaris, C. Mounet, B. Reig, and P. Vincent, "CPW and discontinuities modeling for circuit design up to 110 GHz in SOI CMOS
technology," in IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp. 295-298, 2007.
[2] Xiao-Lan Tan, A.-L. Franc, E. Pistono, A. Siligaris, P. Vincent, P. Ferrari, and J.M. Fournier, "Performance Improvement Versus CPW and
Loss Distribution Analysis of Slow-Wave CPW in 65 nm HR-SOI CMOS Technology," IEEE Transactions on Electron Devices, vol.59, no.5,
pp.1279-1285, May 2012.
17
References :.
[1] J.L. Gonzalez, F. Badets, B. Martineau, D. Belot,A 56-GHz LC-tank VCO with 17% tuning range in 65-nm bulk CMOS for wireless HDMI,
IEEE Trans. Microwave Theory Tech., 58 (2010).
[2] B. Martineau, V. Knopik, A. Siligaris, F. Gianesello, D. Belot,A 53-to-68 GHz 18 dB m power amplifier with an 8-way combiner in standard
65nm CMOS, in Proceedings of the IEEE International Solid-State Circuits Conference, February 2010, pp. 428429.
[3] Jos Luis Gonzlez, Baudouin Martineau, Didier Belot, On the electrical properties of slotted metallic planes in CMOS processes for RF and
millimeter-wave applications, Microelectronics Journal, Volume 43, Issue 8, August 2012, Pages 582-591.
18
Gv =
Gm Z 21 Z o Z out
2( Z out Z o + Z out Z 11 + Z 22 Z o + Z 11Z 22 Z 21Z 12 )
References :
[1] C. Bernier, J.-B. David, "BAW Filters for Ultra-Low Power Narrow-Band Applications", IEEE International Conference on IC Design &
Technology (ICICDT), 2012.
[2] L. Lolis, T. Ayed, C. Bernier, M. Pelissier, D. Dallet, J. B. Bgueret, Ultra Low Power Bandpass Sampling Architectures Using Lamb Wave
Filters, IEEE NEWCAS, 2010.
[3] A. Flament, A. Frappe, B. Stefanelli, A. Kaiser 1, A. Cathelin, S. Giraud, M. Chatras, S. Bila, D. Cros, J.-B. David, L. Leyssenne, E. Kerherve,
"A complete UMTS transmitter using BAW filters and duplexer, a 90-nm CMOS digital RF signal generator and a 0.25-m BiCMOS power
amplifier", International Journal of RF and Microwave Computer-Aided Engineering 21 (2011) 466-476.
19
Reference :
[1] Dubois, M.; De Foucauld, E.; Mounet, C.; Dia, S.; Mayor, C., A frequency measurement BIST implementation targeting gigahertz
application, 2012 IEEE International Test Conference (ITC), Page(s): 1 - 8
20
21
Architecture &
IC Design
For Image
Sensors
22
digital
bus
Vpulse
GS
rst
Vint
indium
bump
+
Vref
-
VBIAS
monostable
circuit
RS
11bit
counter
GS
IPD
MCT
PD
RS
11
analog
bus
CINT
Vref +
5 bit flash
ADC
16
pixel
towards
SRAM
pixel area
900
counter area
+ CINT area
7.2mm
9.6mm
700
area (um2)
500
counter area
300
CINT area
100
10
12
14
16
[4]
[1]
[2]
CMOS
process
0.18m
0.35m
0.18m
0.18m
Pixel pitch
30m
50m
30m
50m
Peak SNR
88dB
85dB
75dB
70dB
Power/pixel
0.5W
1.7W
10W
9.7W
Format
320x256
128x128
16x1
64x64
References :
[1] A. Peizerat, M. Arques and J.-L. Martin, Pixel-level A/D conversion: comparison of two charge packets counting techniques, in Proc., 2007
International Image Sensor Workshop.
[2] Peizerat, A.; Rostaing, J.; Zitouni, N.; Baier, N.; Guellec, F.; Jalby, R.; Tchagaspanian, M., An 88dB SNR, 30m pixel pitch Infra-Red
image sensor with a 2-step 16 bit A/D conversion, 2012 Symposium on VLSI Circuits (VLSIC), pp. 128-129
23
Linear Photon-Counting
with HgCdTe APDs
Research topics : photon counting, image sensor, infrared
F. Guellec, G. Vojetta, J. Rothman
ABSTRACT: A custom readout IC has been developed for photon counting. It features a pixel with 115V/econversion gain, 10e- noise and 13W power consumption to comply with upcoming integration in focal plane
arrays. It has been hybridized to mid-wave infrared HgCdTe Avalanche Photodiodes (APD). The circuit
performances allowed fine characterization of APD gain and excess noise as well as reproducing the Poisson
statistics of the laser pulse from measurements. Linear mode photon counting with low APD gain (40) at 80K
has been demonstrated. A 90% internal photon detection efficiency and a 800kHz dark count rate have been
evaluated. This dark count rate can be reduced at higher gain (8kHz at 200) or with short-wave infrared APD.
Infrared avalanche photodiodes (APD) using HgCdTe
compound semiconductor material are developed by CEA-Lti
since several years. These photodiodes are typically cooled at
80K and operate below the breakdown with an avalanche
mechanism only initiated by electrons resulting in a linear
amplification (M) with a very low excess noise factor (F).
For this work [1], we developed a new low-noise readout
electronic circuit in a standard 0.18m CMOS technology. It
targets single-photon detection at moderate APD gain. This
circuit will enable operation in the Short Wave infrared
(SWIR) band where the APDs exhibit a significantly reduced
gain for a given photodiode bias voltage compared to the Mid
Wave Infrared (MWIR) band. The use of SWIR APD allows
reducing the Dark Count Rate (DCR) or increasing the
operating temperature (for a given DCR).
P (n) = ( n n!) e
where
=< n > .
References :
[1] G. Vojetta, F. Guellec, L. Mathieu, et al., Linear photon-counting with HgCdTe APDs, Proc. SPIE 8375, Advanced Photon Counting
Techniques VI, 83750Y, May 2012.
23bis
Rfrences :
[1] F. Guellec, S. Dubois, E. de Borniol et al., A low-noise, 15m pixel-pitch, 640x512 hybrid InGaAs image sensor for night vision, Proc. SPIE
8298, Sensors, Cameras, and Systems for Industrial and Scientific Applications XIII, 82980C, February 2012.
[2] E. de Borniol, F. Guellec, P. Castelein, A. Rouvi, J.-A. Robo and J.-L. Reverchon, High-performance 640x512 pixel hybrid InGaAs image
sensor for night vision, Proc. SPIE 8353, Infrared Technology and Applications XXXVIII, 835307, May 2012.
24
Figure 1: Architecture of the pixel and the integration time feedback loop
V (gi ) = sV
G=
V
V
g ns Vw
t l nN ) (
(1)
gm 1 w
gm 1 w
c
N
i ng m w
1 +wg d 1s+ g
wd 3s w
+
+
g
g
g
m 1 w
d 2 s i d 4s
i
(2)
References :
[1] F. Guezzi Messaoud , A. Dupret, A. Peizerat and Y. Blanchard, A novel 3D architecture for High Dynamic Range image sensor and on-chip
data compression, Proceedings of the Sensors, Cameras, and Systems for Industrial, Scientific, and Consumer Applications XII, San Francisco,
SPIE 2011.
[2] F. Guezzi Messaoud, A. Dupret, A. Peizerat and Y. Blanchard, On-chip compression for HDR image sensors, proc.DASIP, 90-96, October
2010.
[3] Guezzi Messaoud F., Dupret A., Peizerat A. & Blanchard Y. High Dynamic Range Image Sensor with Self Adapting Integration time in 3D
Technology, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), December 9-12, Seville, Spain, 2012
25
References :
[1] L. Alacoque, L. Chotard, M. Tchagaspanian, J. Chossat, A small footprint, streaming compliant, versatile wavelet compression scheme for
cameraphone imagers, In International Image Sensor Workshop, IISW09, Bergen Norway.
[2] Verdant, A.; Dupret, A.; Tchagaspanian, M. & Peizerat, A. Computational SAR ADC for a 3D CMOS image sensor, IEEE 10th International
New Circuits and Systems Conference (NEWCAS), 2012, pp. 337-340
26
their functionality.
Table 1.
Parameters
Number of transistors
Power consumption
Window width
Non homogeneity
Sensitivity
Circuit 1
17
1W
10mV/300mV
<12.5%
Lower
Circuit 2
14
0.7W
8mV/500mV
<1%
High
References :
[1] Zhang Ming; Llaser Nicolas; Mathias Herve, Dupret Antoine, "Design and optimization of two motion detection circuits for video monitoring
system," Circuits and Systems (ISCAS), 2012 IEEE International Symposium on , vol., no., pp.1907-1910, 20-23 May 2012
[2] Faiza Ait-Kaci, Herv Mathias, Ming Zhang, Antoine Dupret,"Exploration of Analog Pre-processing Architectures for Coarse Low
Power Motion Detection", IEEE NEWCAS2011, 28th-30th Juin, Bordeaux, France, 2011.
[3] Verdant A.; Villard P., Dupret A.; Mathias H., "Architecture for a low power image sensor with motion detection based ROI," 14th IEEE
International Conference on Electronics, Circuits and Systems, 2007. ICECS 2007, pp.1023-1026, 11-14 Dec. 2007.
[4] Verdant A., Dupret A., Mathias H., Villard P., Lacassagne L., "Adaptive Multiresolution for Low Power CMOS Image Sensor," IEEE
International Conference on Image Processing, 2007. ICIP 2007, vol.5, pp.V-185-V-188,
27
References :
[1] J.-M. Tualle, A. Dupret, and M. Vasiliu, Ultra-compact sensor for diffuse correlation spectroscopy, Electronics Letters, vol. 46, no. 12, pp.
819820, 2010.
[2] Laforest T., Verdant A., Dupret A., Gigan S. & Ramaz F. Towards a real time sensor for focusing through scattering media, 2012 IEEE
Sensors, October 28-31, Taipei, Taiwan, 2012
28
References :
[1] Gavant, F.; Alacoque, L.; Dupret, A.; Ho-Phuoc, T. & David, D. (2012), Perceptual image quality assessment metric that handles arbitrary
motion blur'', SPIE Conference on Image Quality and System Performance IX, Burlingame, CA, JAN 24-26, 2012.
29
Figure 3 : Other frames (first row) and their saliency maps (third
row) provided by the model BSM1. Compressed frames (second
row)
References :
[1] Tien Ho-Phuoc, Alacoque L., Dupret A., Guerin-Dugue A., Verdant A., "A compact saliency model for video-rate implementation", 45th
Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2011, pp.244-248, 6-9 Nov. 2011.
[2] Tien Ho-Phuoc, Laurent Alacoque, Antoine Dupret, Anne Gurin-Dugu, Arnaud Verdant, A unified method for comparison of algorithms of
saliency extraction Proc. SPIE. 8293, Image Quality and System Performance IX 829315 (January 22, 2012)
[3] Tien Ho-Phuoc, Laurent Alacoque, Antoine Dupret, Compact saliency model and architectures for image sensors, IEEE Workshop on Signal
Processing Systems 2012.
[4] Tien Ho-Phuoc, Antoine Dupret, Laurent Alacoque, Saliency-Based Data Compression for Image Sensors. IEEE Sensors, 2012. Oct. 28-31,
Taipei, Taiwan
30
A New Approach of
Smart Vision Sensors
Research topics: smart imagers, adaptive processing, feedback
J. Bezine, M. Thvenin, R. Schmit, M. Duranton, M. Paindavoine (LEAD)
ABSTRACT: Todays digital image sensors are used as passive photon integrators and image processing is
essentially performed by digital processors separated from the image sensing parts. This approach imposes to
the processing part to deal with definitive pictures with possibly unadjusted capture parameters. This work
presents a self-adaptable preprocessing architecture concept with fast feedback controls on the sensing level.
These feedbacks are controlled by digital processing in order to adapt the exposition and processing parameters
to the captured scene parameters. This innovative way of designing smart vision sensors, integrating fast
feedback control enables new approaches for machine vision architectures and their applications.
Nowadays, in most image processing systems, the sensor is
separated from the image processing part, pixel values being
sent serially. First, photons are integrated for a predefined
exposition time; next, a control circuit reads and sequentially
converts the pixel values from analog to digital. Finally, pixel
values are sent to an image processor for image
enhancement or computer vision applications. Thus, image
processing systems consider pixel values after the end of full
exposure. In that way, corrections such as dynamic range
enhancement or image stabilization need to be added in
order to suppress the effects of unadjusted image capture
parameters. This is particularly true in vision applications
such as obstacle detection, or target tracking, the image
sensor being used on moving vehicles, suffering from their
vibrations and often analyzing difficult scenes (highly
contrasted or bad weather conditions).
During the last decade, image processing systems tend to
link sensing parts to the processing units. Near-pixel
processing were introduced in smart sensor, at analog or
digital level, in order to refine or adapt captured images
before final processing, thus optimizing it. To further improve
silicon and energy efficiency, this work proposes to associate
even more closely image capture and image processing by
adding fast and local feedback controls in the usual image
capture process.
[1] J. Bzine, M. Thvenin, R. Schmit, M. Duranton, M. Paindavoine, A New Approach of Smart Vision Sensors, Proc. SPIE 8436, Optics,
Photonics, and Digital Technologies for Multimedia Applications II, 84360I (June 1, 2012).
31
Architecture,
IC Design &
Control for
Digital SoCs
32
The SoC is being implemented in STMicroelectronics lowpower 28nm CMOS process. Target chip area is below
26mm. The power distribution grid of the SoC is designed to
handle power delivery in both 3D and 2D configurations. The
chip power consumption under heavy workload is upperbounded at 4W (at 1.1V, 125C), but its aggressive power
management features enables energy-proportional operation
up to a few hundreds mW average power.
References :
[1] Melpignano D., Benini L., Flamand E., Jego B., Lepley T., Haugou G., Clermidy F. & Dutoit D., "Platform 2012, a many-core computing
accelerator for embedded SoCs: Performance evaluation of visual analytics applications." 49th Annual Design Automation Conference, DAC '12,
3 June 2012 - 7 June 2012: 1137-1142.
[2] Y Thonnart, P. Vivet, F. Clermidy, "A fully-asynchronous low-power framework for GALS NoC integration, DATE 2010
33
References :
[1] Marandola, J.; Louise, S.; Cudennec, L.; Acquaviva, J.-T. & Bader, D. A. Enhancing Cache Coherent Architectures with access patterns for
embedded manycore systems System on Chip (SoC), Proc. of 2012 International Symposium on SOC, Tampere, Finland, 1 -7, 2012
[2] L. Cudennec, J. Marandola, J-Th Acquaviva and J-S Camier, Multi-core System and Method of Data Consistency, FR2970794 (A1), CEA,
January 2011.
34
Segment 1
Memory
space
Cache
Access
Controller 1
3,0 3,1
3,0
3,1
3,2
3,3
2,0
2,1
2,2
2;3
1,0
1,1
1,2
1,3
0,0
0,1
0,2
0,3
2,0 2,1
3,0 3,1
2,0 2,1
1,0 1,1
0,0 0,1
Mem Mapping
@ 0xFFF
Cache tiles
First mapping:
Mapping of cache
access controllers
in memory space
Allocation
Second mapping:
Allocation of cache
tiles to cache access
controllers
References :
[1] E. Guthmuller, I. Miro-Panades and A. Greiner, Adaptive Stackable 3D Cache Architecture for Manycores, in VLSI (ISVLSI), 2012 IEEE
Computer Society Annual Symposium on, aug. 2012, pp. 3944.
35
TAP
Controller
Unconnected
3D-Micro-Buffers
3D-Micro-Buffers
3D ANoC Router
Trst
Tck
Tms
Tdi
Tdo
DIE 2
IO
PAD
Unconnected
Config
Test
3D-Micro-Buffers
3D-Micro-Buffers
DIE 0
3D INTERCONNECTS
TSV + MICRO BUMPS
3D-Micro-Buffers
3D-Micro-Buffers
3D ANoC Router
Trst
Tck
Tms
Tdi
Tdo
JTAG SWITCH
JTAG
SW
JTAG
SW
IO
PAD
To Board
Config
JTAG
Port
TAP
Controller
Tester
JTAG
Port
Test
DIE 1
JTAG SWITCH
TAP
Controller
3D-Micro-Buffers
Unconnected
Unconnected
DIE 0
JTAG SWITCH
3D-Micro-Buffers
DIE 0
References :
[1] F. Clermidy, F. Darve, D. Dutoit, W. Lafi, P. Vivet, 3D Embedded Multi-core: Some Perspectives, DATE2011, Grenoble, March 2011.
[2] P. Vivet, D. Dutoit, Y. Thonnart and F. Clermidy, 3D NoC Using Through Silicon Via: an Asynchronous Implementation , VLSI-SOC2011,
Hong Kong, Oct2011.
[3] P. Vivet, F. Clermidy, D. Dutoit, "Design-for-Test and Fault Tolerant Architecture for a 3D NoC TSV-based Infrastructure." LPonTR
Workshop, during European Test Symposium, ETS12, Annecy, France, May 2012.
36
PGL
PUR
1
PDL
PGR
PDR
VDDS
VDD
PUR
PGL
PGR
L
BLL
VB=VDD
PDL
PDR
BLR
PW
DNW
References :
[1] C. Fenouillet-Beranger et al., "Efficient Multi-VT FDSOI technology with UTBOX for low power circuit design", SOI Conference, 2012.
[2] O. Thomas et al., "6T SRAM design for wide voltage range in 28nm FDSOI", SOI Conference, 2012.
37
1.4
FDSOI
0.059 um
VMIN [V]
1.2
1
0.8
0.4
1
1.1
1.2
1.3
1.4
A
VT
1.5
1.6
[mVum]
1.7
1.8
1.9
0.7
nominal
Minimum DRV- VTN=VTNNOM-100mV
DRV [V]
0.6
0.5
0.4
0.3
0.2
18
32
28
Technology Node [nm]
22
38
45
nominal
Minimum DRV- V =VTNNOM-100mV
TN
2
1
0
VTN-100mV
0.072 um2
0.6
AVT [mVum]
18
22
32
28
Technology Node [nm]
38
45
References :
[1] A. Makosiej, O. Thomas, A. Vladimirescu, A. Amara, "Stability and Yield-Oriented Ultra-Low-Power Embedded 6T SRAM Cell Design
Optimization", DATE 2012
[2] A. Makosiej, O. Thomas, A. Vladimirescu, A. Amara, Low-Power Embedded 6T SRAM Cell Design For 6 Yield, VARI Workshop 2012
[3] A. Makosiej, O. Thomas, A. Vladimirescu, A. Amara, CMOS SRAM Scaling Limits under Optimum Stability Constraints, ISCAS 2013
38
References:
[1] D. Soussan, A. Valentian, S. Majcherczak and M. Belleville, "A mixed LPDDR2 impedance calibration technique exploiting 28nm fullydepleted SOI back-biasing." in Proceedings of the IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2012, 30
May 2012 - 1 June 2012
39
1-of-m
TRDIC 2-of-m+1
Encoder
QDI Data
Link
3500
1-of-4
2-of-5
TRDIC 2-of-5
Data
Receiver
TRDIC
1-of-m Decoder
2-of-m+1
K Failures/second
3000
2500
2000
1500
1000
500
0
100
200
400
500
700
800
1000
References :
[1] Y. Thonnart, P. Vivet, F. Clermidy. "A fully-asynchronous low-power framework for GALS NoC integration." Proceedings of the 13th Design,
Automation and Test in Europe Conference and Exhibition, DATE 2010, Dresden, Germany, pp. 33-38.
[2] J. Pontes, N. Calazans, P. Vivet, Adding temporal redundancy to delay insensitive codes to mitigate single event effects'', Proceedings of
the IEEE 18th International Symposium on Asynchronous Circuits and Systems, ASYNC 2012, Copenhagen, Denmark, pp. 142-149.
[3] J. Pontes, N. Calazans, P. Vivet, An accurate single event effect digital design flow for reliable system level design'', Proceedings of the
15th Design, Automation and Test in Europe Conference and Exhibition, DATE 2012, Dresden, Germany, pp. 224-229.
40
(a)
Reset
Fwd
Logic
(b)
Fwd
Logic
Bwd
Logic
Reset=clk
Reset
Bwd
Logic
Bwd
Logic
Reset=clk
Fwd
Logic
Fwd
Logic
Bwd
Logic
Reset=clk
Fwd
Logic
Bwd
Logic
Source
preCTS.sdc
Reset=clk
Synthesis
Netlist.ref.v
PSync.lib
dummy.ctsspec
CTS
postCTS.sdc
Reset
C
Async.lib
SPEF
PSyncIP.lib
Netlist.final.v
Sign-off TA
GDS
DRC, LVS
SDF
Final sim.
Tape-out
Fwd
Logic
Bwd
Logic
References :
[1] Y. Thonnart, E. Beign, and P. Vivet, A pseudo-synchronous implementation flow for WCHB QDI asynchronous circuits, Proceedings of the
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems (ASYNC 2012), pp. 73-80, May 2012.
[2] Y. Thonnart, P. Vivet, F. Clermidy, A fully-asynchronous low-power framework for GALS NoC integration, Proceedings - Design,
Automation and Test in Europe, DATE 2010, pp. 33-38, March 2010.
[3] P. Vivet, D. Dutoit, Y. Thonnart, F. Clermidy, 3D NoC using through silicon via: An asynchronous implementation, 2011 IEEE/IFIP 19th
International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, pp. 232-237, October 2011.
[4] F. Clermidy, C. Bernard, R. Lemaire, J. Martin, I. Miro-Panades, Y. Thonnart, P. Vivet, N. Wehn, A 477mW NoC-based digital baseband for
MIMO 4G SDR, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, ISSCC 2010, pp. 278-279, February 2010.
[5] D. Melpignano et al., Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics
applications, Proceedings of the 49th Annual Design Automation Conference, DAC 2012, pp. 1137-1142, June 2012.
41
References :
[1] S. Foroutan, Y. Thonnart, F. Petrot, "An Iterative Computational Technique for Performance Evaluation of Networks-on-Chip." IEEE
Transactions on Computers, to appear, 2013.
[2] S. Foroutan, Y. Thonnart, R. Hersemeule, A. Jerraya, "A Markov Chain based method for NoC end-to-end latency evaluation", Proceedings
of the 2010 IEEE International Symposium on Parallel and Distributed Processing, Workshops and Phd Forum, IPDPSW, July 2010.
[3] S. Foroutan, Y. Thonnart, R. Hersemeule, A. Jerraya, "An analytical method for evaluating network-on-chip performance", Proceedings Design, Automation and Test in Europe, DATE, pp. 1629. March 2010.
[4] S. Foroutan, Y. Thonnart, R. Hersemeule, A. Jerraya, "Analytical computation of packet latency in a 2D-mesh NoC", 2009 Joint IEEE NorthEast Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA, May 2009.
42
References :
[1] N. Ventroux, T. Sassolas, A. Guerre, B. Creusillet and R. Keryell. SESAM/Par4All: A Tool for Joint Exploration of MPSoC Architectures and
Dynamic Dataflow Code Generation, HIPEAC Worshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), Paris,
France, January 2012.
[2] N. Ventroux, A. Guerre, T. Sassolas, L. Moutaoukil, C. Bechara, and R. David. SESAM: an MPSoC Simulation Environment for Dynamic
Application Processing, IEEE International Conference on Embedded Software and Systems(ICESS), Bradford, UK, July 2010.
[3] N. Ventroux, T. Sassolas, R. David, G. Blanc, A. Guerre, and C. Bechara. SESAM Extension For Fast MPSoC Architectural Exploration And
Dynamic Streaming Application, IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Madrid, Spain, September 2010.
43
References :
[1] Joshi S., Lombardot A., Belleville M., Beigne E. & Girard S., A gate level methodology for efficient statistical leakage estimation in complex
32nm circuits, Design Automation & test in Europe Conference, DATE 2013, 18-22 March 2013
[2]Joshi S., Lombardot A., Belleville M., Beigne E. & Girard S., Statistical leakage estimation in 32nm CMOS considering cells correlations'',
2012 IEEE Faible Tension Faible Consommation, FTFC 2012, Paris '.
[3] Joshi S., Lombardot A., Flatresse P., D'Agostino C., Juge A., Beigne E. & Girard S., Statistical estimation of dominant physical parameters
for leakage variability in 32 nanometer CMOS, under supply voltage variations, Journal of Low Power Electronics 8(1), 113-124, 2012.
44
RTL description
applications
cross-compiler
Design
netlist
VCD
Updated library
Modelsim
Manufacturer
library
binaries
Design
compiler
Cell delay
updater
Degradation model
fresh/aged
PrimeTime
Slack
times
Sensitive
paths
Toggle
rate
up to x4
References :
[1] C. Bertolini, O. Heron, N. Ventroux and F. Marc, Relation between HCI-induced performance degradation and applications in a RISC
processor, IEEE Int. on-line Testing Symp., pp. 67-72, July 2012.
[2] N. Ventroux, A. Guerre, T. Sassolas, L. Moutaoukil, G. Blanc, C. Bechara, and R. David SESAM: an MPSoC Simulation Environment for
Dynamic Application Processing, IEEE International Conference on Embedded Software and Systems (ICESS), Bradford, UK, July 2010.
45
We are currently developing strategies to adapt at runningtime the settings of the so-called voltage and frequency
actuators to reach the most energy efficient operating point.
References :
[1] L. Vincent, E. Beign, L. Alacoque, S. Lesecq, C. Bour, and P. Maurine, A Fully Integrated 32 nm MultiProbe for Dynamic PVT
Measurements within Complex Digital SoC, 2nd European Workshop on CMOS Variability, VARI11, 2011.
[2] L. Vincent, P. Maurine, S. Lesecq, and E. Beign, Embedding Statistical Tests for on-chip Dynamic Voltage and Temperature Monitoring,
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE, 2012.
[3] L. Vincent, S. Lesecq, P. Maurine, and E. Beign, Local Condition Monitoring in integrated circuits using a set of Kolmogorov-Smirnov
Tests, IEEE Conference on Control and Applications (CCA), 2012.
[4] L. Vincent, P. Maurine, E. Beign, and S. Lesecq, Local Environmental Variability Monitoring using Hypothesis Tests, Conf. Int. Faible
Tension Faible Consommation (FTFC), Paris, France, 2012.
[5] S. Lesecq, L. Vincent, E. Beign, Ph. Maurine, VT-state condition monitoring in integrated circuits using fusion of information from general
purpose sensors, 12th International Forum on Embedded MPSoC and Multicore MPSoC, July 9-13, Canada, 2012.
[6] S. Lesecq, L. Vincent, E. Beign, Ph. Maurine, How state estimation in integrated circuits based on statistical tests can be used to fine-tune
the control of the voltage and frequency actuators in the power management framework, VARI 2012, Nice, France.
46
47
Two power paths are available for loads power supply: the
conventional indirect power path consists in recharging the
battery with harvested energy and afterwards draining it to
fulfill the capacitor and the additional direct power path only
includes the temporary energy storage into the capacitor [1].
The direct power path has much higher power efficiency due
to fewer voltage conversion stages but is only available when
both energy is harvested and required by the loads.
Nevertheless, while applicative task period is usually fixed,
References :
[1] J.F. Christmann, E. Beign, C. Condemine, J. Willemin, C. Piguet, Energy Harvesting and Power Management for Autonomous Sensor
Nodes, IEEE/ACM Design Automation Conference (DAC), San Francisco CA, USA, 1049-1054, June 2012
[2] J.F. Christmann, E. Beign, C. Condemine, C. Piguet, Event-driven asynchronous voltage monitoring in energy harvesting platforms, IEEE
NorthEast Workshop on circuits and Systems (NEWCAS), Montral, Canada, 457-460, 2012
48
49
Neuromorphic Circuits
Beyond CMOS RF Devices
RRAM Circuits
Architecture
& IC Design
For Emerging
Technologies
50
References:
[1] A. Joubert, B. Belhadj, O. Temam and R. Hliot, "Hardware spiking neurons design: Analog or digital?", in Proceedings of the 2012 Annual
International Joint Conference on Neural Networks (IJCNN), June 2012
[2] A. Joubert, M. Duranton, B. Belhadj, O. Temam and R. Hliot, "Capacitance of TSVs in 3-D stacked chips a problem? Not for neuromorphic
systems!", in Proceedings of the 49th Annual Design Automation Conference (DAC), June 2012
[3] B. Belhadj, A. Joubert, O. Temam and R. Heliot, "Configurable conduction delay circuits for high spiking rates", in Proceedings of the 2012
IEEE International Symposium on Circuits and Systems (ISCAS), May 2012
51
References:
[1] O. Bichler, M. Suri, D. Querlioz, D. Vuillaume, B. DeSalvo and C. Gamrat, Visual Pattern Extraction Using Energy-Efficient 2-PCM Synapse
Neuromorphic Architecture, Electron Devices, IEEE Transactions on, vol. 59, no. 8, pp. 2206-2214, 2012
[2] M. Suri, O. Bichler, D. Querlioz, O. Cueto, L. Perniola, V. Sousa, D. Vuillaume, C. Gamrat and Barbara DeSalvo, Phase change memory as
synapse for ultra-dense neuromorphic systems: Application to complex visual pattern extraction, Electron Devices Meeting (IEDM), 2011 IEEE
International, pp. 4.4.1-4.4.4, 2012
52
References:
[1] O. Bichler, W. Zhao, F. Alibart, S. Pleutin, S. Lenfant, D. Vuillaume and C. Gamrat, Pavlov's Dog Associative Learning Demonstrated on
Synaptic-Like Organic Transistors, Neural Computation, vol. 25, no. 2, pp. 549-566, 2012.
[2] O. Bichler, W. Zhao, F. Alibart, S. Pleutin, D. Vuillaume and C. Gamrat, Functional Model of a Nanoparticle Organic Memory Transistor for
Use as a Spiking Synapse, Electron Devices, IEEE Transactions on, vol. 57, no. 11, p. 3115-3122, 2010.
[3] F. Alibart, S. Pleutin, O. Bichler, C. Gamrat, T. Serrano-Gotarredona, Be. Linares-Barranco and D. Vuillaume, A Memristive
Nanoparticle/Organic Hybrid Synapstor for Neuroinspired Computing, Advanced Functional Materials, vol. 22, no. 3, pp. 609-616, 2012.
53
Bias T
Ibias
Hext
VAC
pinned layer
and
(t ) :
(2)
(1)
(rad)
(s ) = kN
s(s + c )
I
100 nm
dm
dm
= 0 m H ef + m
0 I [m [m p ]]
dt
dt
r (t )
r = k d 1 + k q r r + 0 I 1 k s r r
= 0 + Nr 2
2
L C
free layer
non magnetic layer
properties and p is the spin-polarization vector. Being 3dimensional and strongly non-linear. this equation, although
accurate from a physics point of view, is too complex to be
used when studying a network where the bias current of each
oscillator is to be modulated by the output voltage of some of
the other oscillators. So our first need was a reliable, fast,
phase oriented model able to account for the impact of
bias current modulation on a STO output voltage.
The new model was derived in two steps. Thanks to a first
approximation, the LLGS was turned into a 2-dimensional set
0.02
LLGS
r,
LTI
0
-0.02
-0.04
4
4.2
4.4
4.6
4.8
x 10
-8
Time (sec)
References :
[1] P.Villard, U.Ebels, D.Houssameddine, J.Katine, D.Mauri, B.Delaet, P.Vincent, M.-C.Cyrille, B.Viala, J.-P.Michel, J.Prouve, and F.Badets, A
GHz-spintronic-based RF oscillator, IEEE Journal of Solid State Circuits, 45(1), January 2010, pp.214-223
[2] M.Zarudniev, E.Colinet, P.Villard, U.Ebels, M.Quinsat, G.Scorletti, Synchronization of a spintorque oscillator array by a radiofrequency
current, Mechatronics Journal 22 (2012) pp.552-5.55
54
References :
[1] G.M. Landauer, J.L. Gonzalez, Radiofrequency Performance of Carbon Nanotube FETs in Comparison to Classical CMOS Technology,
ESSCIRC 2011, Sept. 2011, Fringe Poster Session.
[2] G.M. Landauer, J.L. Gonzlez, "Carbon nanotube FET process variability and noise model for radiofrequency investigations," 2012 12th IEEE
Conference on Nanotechnology (IEEE-NANO), pp.1-5, 20-23 Aug. 2012.
55
Bipolar OxRRAM-based
Non-volatile SRAM (NV-SRAM)
for Information Back-up
Research topics: Resistive RAMs, NV-SRAM, Low leakage, Non-volatile, FDSOI
Hraziia (ISEP), O. Thomas, F. Clermidy, C. Angels (ISEP), A. Amara (ISEP)
ABSTRACT: One of many techniques to reduce the static power dissipation at stand-by mode is using the
concept of power gating. But this technique cannot be employed to the memory section as it leads to data loss
and affects the data integrity. The inherent non-volatile property of Resistive RAMs (RRAMs) can be exploited to
provide non-volatility when used alongside volatile Static RAMs and at the same time exploit the zero-power
consumption property of Resistive RAMs at stand-by mode for low power management.
OxRRAM devices.
The STORE operation is always successful as it will set the
OxRRAMs resistance to a low value but RON will vary under
the VT variation which will change the ROFF/RON in turn will
influence the proper restore of SRAMs logical state from
OxRRAMs. Fig. 2 depicts that the (ROFF/RON) can be increased
by having a long STORE time or increasing the WLP of the
SRAM pull-up transistor. But having a long STORE time
results in power consumption and WLP size will be limited by
the cell area and the write ability of the SRAM. Fig. 3 depicts
a worst case mismatch analysis of the hybrid cell during a
RESTORE operation. Referring to Fig.3, the maximum
achievable ROFF/RON(=4) of NV-SRAM corresponds to n = 2
which is very low from stability viewpoint. To ensure SRAM
yield of 5 (6) for reliable recovery, maximisation of the
resistance drop, RDROP in the high R/t region corresponding
to the ROFF/RON (Fig.2) for low STORE time should be the
focus. The results on Monte Carlo simulation for recovery
operation indicates that even in the worst case for SRAM
yield, the resistance ratio should be at least 10(20). Hence,
the stability analysis implies that, from the RRAM technology
point, the focus should be to maximise the ROFF/RON resistance
ratio.
Figure 2: RON vs. time during STORE operation for various WLP in
the range 80nm to 200nm range [1]
6
5
4
3
2
1
0
10
20
30
40
50
ROFF/RON
60
70
80
90
100
Rfrences :
[1] "Operation and Stability analysis of Bipolar OxRRAM-based Non-Volatile 8T-2R SRAM as a solution for Information Back-Up," Hraziia et al.,
accepted for publication in Elsevier Solid-State Electronics, 2012.
[2] Bipolar OxRRAMs based non-volatile 8T2R SRAM for information back-up, Hraziia et al., EUROSOI 2012.
56
BET =
t0
=
t0 + t1
1
P
1 + OH
PL
References :
[1] Ogun Turkyilmaz, Santhosh Onkaraiah, Marina Reyboz, Fabien Clermidy, Hraziia, Costin Anghel, Jean-Michel Portal, and Marc Bocquet.
RRAM-based FPGA for Normally Off, Instantly On Applications, NanoArch 2012.
[2] Hraziia, Costin Anghel, Andrei Vladimirescu, Amara Amara, Jean-Michel Portal, Marc Bocquet, Christophe Muller, Damien Deleruyelle,
Santhosh Onkaraiah, Marina Reyboz and Olivier Thomas. Bipolar OxRRAM-based non-volatile 8T2R SRAM for information back-up, EUROSOI
2012.
57
Embedded
Software
58
Integrated Architecture
Exploration Workflow
Research topics: HW/SW co-design, architecture exploration workflow
D. Puschini, J. Mottin, C. Fabre, N. Palix, L. Apostol, E. Vaumorin (Magillem Design Services)
ABSTRACT: Compute-intensive applications can greatly benefit from the flexibility of NoC-based heterogeneous
multi-core platforms. However, mapping applications on such MPSoC is becoming increasingly complex and
requires integrated design flows. We conducted a case study to evaluate the benefits of an integrated design
flow for the mapping space exploration of a real telecommunication application on a NoC-based heterogeneous
platform. Thanks to the flow, we simulated several virtual platforms and several mappings of our application on
each. This approach drastically lowers the required skills and the time needed for design space exploration. An
improvement of several weeks has been observed.
Embedded systems have evolved from a single processor
architecture to Multi-Processor Systems-on-Chip (MPSoC).
Designing embedded software for these increasingly complex
and heterogeneous platforms in an efficient manner is
becoming a serious challenge. Applications are particularly
difficult to program on platforms based on Network-on-Chip
(NoC) interconnection, where developers must also define
and setup the communications between the units.
Studying and optimizing the mapping of micro-code on the
different units is particularly difficult and subject to errors.
Developers usually need to define fine-grain and coherent
configuration files for every node. Thus, moving a task from
one IP core to another, impacts not only the communications
of this code but also the ones of every unit it communicates
with. Design flows for NoC-based SoC is an active research
area. One of the most challenging issues is to organize the
mapping on the cores while taking into account issues related
to communication like deadlock, bandwidth, latencies, and
non-functional properties like energy consumption.
Figure 1 shows a generic design flow for NoC-based
embedded systems.
References :
[1] Puschini D., Mottin J., Palix N., Apostol L., Fabre C., "Integrated architecture exploration workflow: A NoC-based case study," 2012 23rd
IEEE International Symposium on Rapid System Prototyping (RSP), pp.135-141, 11-12 Oct. 2012
59
References :
[1] Y. Lhuillier, D. Courouss, Embedded System Memory Allocator Optimization Using Dynamic Code Generation, 2012 workshop "Dynamic
Compilation Everywhere", in conjunction with the 7th HiPEAC conference, 2012
[2] A. Carbon, Y. Lhuillier, and H-P. Charles, Code Specialization For Red-Black Tree Management Algorithms, 3rd International Workshop on
Adaptive Self-tuning Computing Systems, 2012
60
References :
[1] Trabelsi, K.; Jan, M. & R., S. A practical approach towards static DVFS and DPM scheduling in real-time systems, in 'Proceedings of the 1st
IEEE Workshop on Power, Energy and Temperature Aware Real-Time Systems', 2012
61
References :
[1] Charles H.P., Lomller V., Data Size and Data Type Dynamic GPU Code Generation in GPU design pattern, Editor: Magoules, SAXECOBURG PUBLICATIONS, 2012
[2] Courouss, D. & Charles, H.-P. Dynamic Code Generation: An Experiment on Matrix Multiplication Proceedings Work-in-Progress Session of
LCTES 2012, 2012
[3] Alexandre Carbon, Y. L. & Charles, H.-P. Scaling down to embedded systems for dynamic compilation 2nd international workshop on
"Dynamic compilation everywhere", 2013
[4] Charles, H.-P. Basic Infrastructure for Dynamic Code Generation Workshop "Dynamic Compilation Everywhere", in conjunction with the
7th HiPEAC conference, 2012.
62
x1,4
Conventional algorithms
Table 1 : Algorithm
simulator).
1x
12x
17x
between
indirection
depths
(x86
instrumented
References :
[1] A. Carbon, Y. Lhuillier, and H-P. Charles, Just-In-Time Compilation Characterization, Poster session of the 7th International Conference on
High-Performance and Embedded Architectures and Compilers, Paris, France, January 2012.
[2] A. Carbon, Y. Lhuillier, and H-P. Charles, Adapting Dynamic Compilation to Embedded Systems, Poster session of the 8th International
Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, Fiugi, Italia, July 2012.
63
References :
[1] T. Goubier, R. Sirdey, S. Louise, V. David, Sigma-C: A programming model and language for embedded manycores, in: Algorithms and
Architectures for Parallel Processing, Vol. 7016 of Lecture Notes in Computer Science, Springer Berlin / Heidelberg, 2011, pp. 385394.
[2] P. de Oliveira Castro, S. Louise, D. Barthou, Dsl stream programming on multicore architectures, in: Programming Multi-core and Manycore Computing Systems, John Wiley and Sons, 2011.
[3] L. Cudennec, R. Sirdey, Parallelism reduction based on pattern substitution in dataflow oriented programming languages, in: Proceedings
of the 12th International Conference on Computational Science, 2012.
64
35
30
25
144
20
3
324
15
529
10
5
0
2
12
24
48
References :
[1] F. Galea and R. Sirdey, A parallel simulated annealing approach for the mapping of large process networks, PCO'12 as part of the 26th
IEEE International Parallel & Distributed Processing Symposium (IPDPS'12), Shanghai, China, 2012.
[2] T. Goubier, R. Sirdey, S. Louise and V. David, C : A Programming Model and Language for Embedded Manycores, Algorithms and
Architectures for Parallel Processing, Berlin / Heidelberg, Springer, 2011, p. 385394.
[3] R. Sirdey, Contributions l'optimisation combinatoire pour l'embarqu : des autocommutateurs cellulaires aux microprocesseurs
massivement parallles, HDR Thesis, 2011.
[4] O. Stan, R. Sirdey, J. Carlier et D. Nace, A heuristic algorithm for stochastic partitioning of process networks, 16th International
Conference on System Theory, Control and Computing (ICSTCC), 2012.
65
References :
[1] O. Stan, R. Sirdey, J. Carlier and D. Nace, "A heuristic algorithm for stochastic partitioning of process networks", Proceedings of the 16th
IEEE International Conference on System Theory, Control and Computing, Sinaia, Romania, 2012.
66
References :
[1] T. Goubier, R. Sirdey, S. Louise and V. David. C: A programming model and language for embedded manycores. ICA3PP, Lecture Notes
in Computer Science, vol. 7016, 2011.
[2] P. Dubrulle, S. Louise, R. Sirdey and V. David. A low-overhead dedicated execution support for stream applications on shared memory
CMP, Proc. of 10th ACM int. conf. on Embedded Software. pp. 143-152, 2012.
[3] L. Cudennec and R. Sirdey, Parallelism reduction based on pattern substitution in dataflow oriented programming languages, Proc. of 12th
int. conf. on Computer Science, 2012.
67
68
Tellstick
Watteco
PUTUTU framework
iRIO
Object_dongles_modules
Homes
KNX
Object_Wsan_sensors
Object_Wsan_actuators
PLUGWISE
Object_Wsan_sensors_actuators
RFXCOM
Letibee
TelosB
References :
[1] L.-F. Ducreux, C. Guyon-Gardeux, S. Lesecq, F. Pacull, S. R. Thior, Resource-based middleware in the context of heterogeneous building
automation systems, 38th Annual Conference of the IEEE Industrial Electronics Society IECON, Montreal, Canada, October 2012.
[2] H. Iris, F. Pacull, Protocol Awareness: A Step Towards Smarter Sensors, Wish workshop, Third International Conference on Sensor Device
Technologies and Applications SENSORDEVICES 2012, Rome, Italy, August 2012.
[3] F. Pacull, "Deployment management through on-remote-site dynamic compilation.", Workshop Dynamic Compilation Everywhere in
conjunction with the 7th International Conference on High-Performance and Embedded Architectures and Compilers (HIPEAC - 2012), Paris,
France.
69
Memories
Wire Diagnosis
Reliability
& Test
70
P = e
MTTF
x
=
MTTF
1 x
If 20% of the (N+1)-bit errors become correctable, then the
MTTF can be improved with 25%. This means that an MTTF of
4 years can be extended with one additional year. We
generate H-matrices of the maximized double-bit error
correcting codes (DEC) codes from scratch with the help of a
SAT-solver. If only data-bits need to be provided by a
maximized DEC decoder, the hardware overhead can be
reduced by selecting those triplets that involve a maximum
number of check-bit positions. Besides the constraints specific to a DEC code, two additional goals were imposed:
(22,12)
12
10
770
50%
100%
(26,16)
16
(36,24)
24
10
672
26%
35%
12
3250
46%
(44,32)
32
84%
12
3100
23%
31%
References :
[1] V. Gherman, S. Evain, and Y. Bonhomme, Memory Reliability Improvements based on Maximized Error-Correcting Codes, IEEE European
Test Symposium, pp. 1-6, 2012.
71
Network
with
sensors
References :
[1] W. B. HASSEN, F. AUZANNEAU, F. PERES, and A. TCHANGANI, A Distributed Diagnosis Strategy using Bayesian Network for Complex
Wiring Networks, in IFAC Workshop on Advanced Maintenance Engineering, Services and Technology (AMEST), November 2012.
72
Reference:
[1] L EL-SAHMARANY, F. AUZANNEAU and P.BONNET Nouvelle mthode de diagnostic filaire base sur le retournement temporel'', Actes du
16me Colloque International sur la Compatibilit Electromagntique (CEM 2012)', Rouen, Avril 2012.
73
step 5 for the healthy cable (Capacitance is C0) and for three
simulated aged cables (Capacitance values of aged cables are
0.2, 0.6 and 1.2 times C0) were calculated. Table I presents
the values of SC and shows the effect of ageing. When the
cable is healthy, SC is equal to 1 and when it is aged (0.2 *
C0) SC is down to 0.5127.
Table 1: Values of skewness coefficient SC for different simulated
aged cables
Simulations
SC
1.2*C0
1.09
C0
1
0.6* C0
0.7943
0.2 *C0
0.5127
SC
new
1
1 month
1.28
2 months
1.29
2 months 10 d
1.31
References :
[1] L EL-SAHMARANY, F. AUZANNEAU and P.BONNET A new method for detection and characterization of electrical cable aging, Progress In
Electromagnetics Research Symposium, in Kula Lumpur, Malaysia, March 2012.
[2] L EL-SAHMARANY, F. AUZANNEAU and P.BONNET Novel Reflectometry Method Based on Time Reversal for Cable Aging Characterization,
Portland, OR, USA, 23 - 26 September 2012.
74
Figure 2: TFC obtained with the PWVt, when the injected signal is
a Gaussian pulse of 1ns width at half-height
Width of
the injected
pulse
1ns
5ns
Figure 1: Reflectograms obtained after injecting a Gaussian pulse
of 1ns width at half-height
Correlation
coefficient
Correlation coefficient
obtained
0.57
0.96
0.65
0.94
References :
[1] M. Franchet, N. Ravot, and O. Picon,The use of the pseudo wigner ville transform for detecting soft defects in electric cables," in
IEEE/ASME International Conference on Advanced Intelligent Mechatronics, Budapest, Hungary, 3-7 jul, 2011, 2011.
[2] Franchet, M.; Ravot, N.; Grgis, N.; J., C. & Picon, O., New Advances in Monitoring the Aging of Electric Cables in Nuclear Power Plants,
Advanced Electromagnetics Symposium, AES 2012, Paris, France, 16-19 April 2012.
75
76
77
PhD Degrees
Awarded
Maud Franchet
Cline Azar
Sbastien Courroux
Olivier Bichler
Fabien Gavant
Mykhailo Zarudniev
78
PhD degrees
awarded in 2012
Maud Franchet
University: Universit Paris-Est
Reflectometry applied to soft fault detetction in bundles of wires
The research works presented in this thesis is about the topic of detecting soft faults (incipient
faults) in specic wiring structures: multiconductor transmission lines (MTL), also known as bundles
of wires. The reectometry methods, often used for the diagnosis of wiring networks, arent for now
ecient enough to detect such defects. Besides, they have been designed for single lines only,
where electromagnetic coupling between conductors (crosstalk) is mostly irrelevant. However such
phenomenon can provide more information about the state of the cable. Using this information
could enable us to detect soft faults more easily. In this work we propose a new reectometry
method, which takes advantage of crosstalk signals in order to detect incipient faults. Such a tool
has also the advantage of being well-adapted to bundles of cables.
Thanks to the preliminary study of the impact of soft faults on the characteristic parameters of a
multiconductor transmission lines and on crosstalk signals, a method called Cluster Time
Frequency Domain Reectometry , has been proposed. It is a three step process. First temporal
reectometry measurements are made at the beginning of the line under test. All the available
signals, even crosstalk ones, are recorded. A time-frequency process is then applied on them, in
order to amplify the presence of defects. Finally, a clustering algorithm, that has been specically
developed for wiring diagnosis, is used to benet from the whole available information.
Cline Azar
University: Universit de Bretagne Sud design
On the design of a distributed adaptive manycore architecture for embedded
systems
Chip design challenges emerged lately at many levels: the increase of the number of cores at the
hardware stage, the complexity of the parallel programming models at the software level, and the
dynamic requirements of current applications. Facing this evolution, this PhD thesis aims at
designing distributed adaptive manycore architecture, named CEDAR (Congurable Embedded
Distributed ARchitecture), which main assets are scalability, exibility and simplicity. The CEDAR
platform is an array of homogeneous, small footprint, RISC processors, each connected to its four
nearest neighbors. No global control exists, yet it is distributed among the cores. Two versions are
designed for the platform, along with a user-familiar programming model. A software version,
CEDAR-S, is the basic implementation where adjacent cores are connected to each other via shared
buffers. A co-processor called DMC (Direct Management of Communications) is added in the CEDARH version, to optimize the routing protocol. The DMCs are interconnected in a mesh fashion.
Two novel concepts are proposed to enhance the adaptiveness of CEDAR. First, a distributed
dynamic routing strategy, based on a bio-inspired algorithm, handles routing in a non-supervised
fashion, and is independent of the physical placement of communicating tasks. The second concept
presents dynamic distributed task migration in response to several system and application
requirements. Results show that CEDAR scores high performances with its optimized routing
strategy, compared to state-of-art networks. The migration cost is evaluated and adequate
protocols are presented. CEDAR is shown to be a promising design concept for future manycores.
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PhD degrees
awarded in 2012
Sbastien Courroux
University: Universit de Bourgogne
Wavelet-based algorthms for embedded image processing and integration into a
smart vision system.
Data at the output of a CMOS image sensor are processed through a set of operations, either for
purposes of rendering or image analysis. Increasing resolution of the sensors and reducing of the
size of the pixels make operations to be applied even more complex and require a large storage
capacity. It is increasingly difficult to reconcile these different constraints in a low-cost embedded
sensor, consisting of an analog part and a digital circuit having a single processor, low storage
capacity and low operating frequency. New methods are then investigated. One of them proposes to
use alternative data representation. The wavelet representation decomposes an image into
frequency bands, orientation and scale, simplifying the future operations of the processing chain.
In a first step, the thesis proposes to study the interest of the wavelet representation for image
processing in embedded real time context. For this, a state of the art of the algorithm methods is
established and allows defining two algorithmic chains: reconstruction of CFA images and facial
recognition. The quality of the process is demonstrated for these two processing.
In a second step, a wavelet-oriented vision system is proposed consisting of an embedded processor
and a module dedicated to the wavelet transform. The wavelet transform module adopts a so-called
'semi-folded' structure and performs effectively the wavelet decomposition at several scales using
only a few lines of internal memory. This vision system is used to speed up processing and increase
application flexibility and effectiveness of low-cost sensors.
Olivier Bichler
University: Universit Paris-Sud
Adaptive Computing Architectures Based on Nano-fabricated Components
In this thesis, we study the potential applications of emerging memory nano-devices in computing
architecture. We show that neuro-inspired architectural paradigms could provide the eciency and
adaptability required for complex image/audio processing and classication applications with a much
lower cost in terms of power consumption and silicon area than current solutions. This work is
focusing on memristive nano-devices, such as: Phase-Change Memory (PCM), Conductive-Bridging
RAM (CBRAM), resistive RAM (RRAM)... We show that these devices are particularly suitable for the
implementation of natural unsupervised learning algorithms like Spike-Timing-Dependent Plasticity
(STDP), requiring very little control circuitry. The integration of memristive devices in crossbar array
could provide the huge density required by this type of architecture (several thousand synapses per
neuron), which is impossible to match with a CMOS-only implementation.
In this work, we propose synaptic models for memristive devices and simulation methodologies for
architectural design exploiting them. Novel neuro-inspired architectures are introduced and
simulated for natural data processing. They exploit the synaptic characteristics of memristives nanodevices, along with the latest progresses in neurosciences.
Finally, we propose hardware implementations for several device types. We assess their scalability
and power eciency potential, and their robustness to variability and faults, which are unavoidable
at the nanometric scale of these devices.
80
PhD degrees
awarded in 2012
Fabien Gavant
University: Universit de Grenoble
Architectures for Image Sensors Stabilization based on Visual Perception and on the
Physiology of Hand Tremor; a Contribution
With the integration of cameras in mobile devices, their democratization and the reduction of the
imager size, the optical system dimensions and the pixels miniaturization, the pictures become more
and more subject to motion blur due to the hand tremor. In addition, the requirements in terms of
image quality become higher and higher. Hence, in order to reduce this blur, several image
stabilization systems have been developed. Nevertheless, they cannot guarantee the sharpness
quality of resulting images and in some cases, they show integration difficulties.
In order to overcome these limitations, the research work presented in this thesis proposes, first of
all, a physiological tremor model that aims at simulating realistic camera shake and secondly,
presents a study on visual perception of blur. This study enables the development of a quality
metric. Finally, stabilization algorithms and architectures exploiting these new tools are presented.
These new architectures reduce the number of external components and ensure sharp stabilized
images.
Mykhailo Zarudniev
University: Universit de Lyon Ecole Centrale de Lyon
Frequency Synthesis using Spin Torque Oscillator Coupling
Current trends in telecommunication are leading to multiple standards systems. The conventional
solution consists in using one local oscillator for each standard. The spin torque oscillator (STO) is a
new device that appears as a potential candidate for the LC-tank oscillator replacement, due to its
wide frequency accordability and its small volume. However, it exhibits poor power and phase noise
performance.
In this work, we propose to reach the technical specification of the radiofrequency applications by
coupling a large number of spin torque oscillators. An original oscillator network model that
describes qualitative properties of the oscillator synchronization is introduced. Next, the control law
architecture for an oscillator set is established in order to achieve the technical specifications.
Finally, we propose two original frequency domain design methods allowing the resolution of our
frequency synthesis problem. The first design method allows considering explicitly a performance
criterion corresponding to a desired frequency constraint. The method allows obtaining a suitable
sub-system interconnection matrix that fits the frequency specification constraint. The second
design method allows to find an interconnection matrix and to take into account simultaneously
several frequency specification constraints. The interconnection matrix obtained with the proposed
method solves the problem of frequency synthesis by coupling of spin torque oscillators.
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