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CHAPTER 1
INTRODUCTION
1.1 INTRODUCTION TO VLSI :
semiconductor
and communication technologies were being developed. Before the introduction of VLSI
technology most ICs had a limited set of functions they could perform. An electronic
circuit might consist of a CPU, ROM, RAM and other peripherals; VLSI lets IC makers add all
of these into one chip. The first semiconductor chips held two transistors each. Subsequent
advances added more transistors, and as a consequence, more individual functions or systems
were integrated over time. The first integrated circuits held only a few devices with
ten diodes, transistors, resistors and capacitors making it possible to fabricate one or more logic
gates on a single device. The fabrication of ICs began with Small Scale Integration (SSI),
improvements in technique led to devices with hundreds of logic gates, known as Medium Scale
Integration (MSI), followed by thousands of logic gates called Large Scale Integration (LSI).
Current technology has moved far past this mark having many millions of transistors fabricated
on single chip known as Very large Scale Integration (VLSI).In the course of enhancement of
technology suitable softwares like VHDL were developed during electric circuit design to work
in real time applications for military purpose by the USA. VHDL an acronym for VHSIC
hardware description language (VHSIC is an acronym for Very High Speed Integrated circuits ).
It is a hardware description language that can be used to model a digital system at many levels of
abstraction, ranging from algorithm level to gate level. It contains elements that can be used to
describe the behavior or structure of the digital system, with the provision for specifying its
timing explicitly and supporting system hierarchy
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CHAPTER 2
BLOCK DIAGRAM
LFSR is widely used as test pattern generator because of its small circuit area and excellent
random characteristics. The proposed architecture consists of a seed generator (SG) with LFSR,
a n-bit counter, a Gray encoder and an exclusive-OR array. The n-bit counter and Gray encoder
generate single input changing patterns.
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Working:
According to the design the proposed structure of TPG C[n-1:0] is the counter output and G[n1:0] is the gray encoder output. The counter and SG are controlled by test clock TCK. The initial
value of the n-bit counter is all zeroes, and it generates 2n continuous binary data periodically.
The output of NOR operation of C[m-1:0] will be the clock control signal of SG where m<=n. It
can be found that SG will generate the next seed only when C[m-1:0] are all 0 and NOR output
changes to 1. The period of the single input changing sequences will be 2m.Gray encoder in
Fig. 1 is used to encode the counters output C[n-1:0] so that two successive values of its output
G[n-1:0] will differ in only one bit. Gray encoder can be implemented by following logic.
G[0] = C[0] XOR C[1]
G[1] = C[1] XOR C[2]
G[2] = C[2] XOR C[3]
.
G[n-2] = C[n-2] XOR C[n-1]G[n-1] = C[n-1] The seed generating circuit SG is a modified
LFSR. The theory stated that the conventional LFSRs outputs cant be taken as the seed directly
because some seeds may share the same vectors. So the seed generator circuit should make sure
that any two of the signal input changing sequences do not share the same vectors or share as few
vectors as possible. The final test patterns are implemented as following logic.
V[0] = S[0] XOR G[0]
V[1] = S[1] XOR G[1]
V[2] = S[2] XOR G[2]
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Decimal Number
Binary Code
Gray Code
0000
0000
0001
0001
0010
0011
0011
0010
0100
0110
0101
0111
0110
0101
0111
0100
1000
1100
1001
1101
10
1010
1111
11
1011
1110
12
1100
1010
13
1101
1011
14
1110
1001
15
1111
1000
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CHAPTER 4
SOFT WARE TOOLS
This Chapter deals with the Software tools used in this Application
4.1 XILINX SOFTWARE:
Xilinx ISE(Integrated Software Environment) is a software tool produced by Xilinx for Synthesis
and analysis of HDL designs ,enabling the developer to synthesize(compile) their designs,
perform timing analysis ,examine RTL diagrams, simulate a designs reaction to different
stimuli, and configure the target device with the programmer
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Press Next two times in the follow-up window and then finish at last
Select New source by clicking on project in source window as shown below
Select VHDL module and name the file .Then click next
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Give port declaration as we do in entity .Then click Next and then hit Finish
VHDL Code with entity and libraries are present on the screen, Now we just have to
write the code in architecture
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Select New Source by clicking on the project in Source script and then select Test Bench
waveform and name the file .Then click Next and then select the file for which u would
like to write the test bench and then finish
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A new window appears as shown below .For combinational circuits select combinational
clock
Change the source type to behavioral in the source box and from the process window
simulate the file
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CHAPTER-5
IMPLEMENTATION
In our project we are going to implement test pattern generator by using LFSR . The power
dissipation of the test pattern generator mainly depends on the switching activities. So mainly we
concentrate on reducing the switching activities from one pattern to the other pattern. We in our
project are going to implement 8 bit pattern generator.
8 BIT PATTERN GENERATOR:
An 8bit pattern generator is used to generate 8bit single bit changing output. We are going to
implement 8bit lfsr , 8bit gray code counter, along with clock gating circuit for this pattern
generation. LFSR generate a random pattern for every clock pulse depending on the input seed.
Whenever the seed is changed the LFSR patterns differs from the previously generated patterns.
Gray code counter is used for generation of single bit changing sequences. These are generated
from the binary count value. The clock gating circuitry is a clock enabling circuit which provides
the clock input to the LFSR. This clock is activated for every 256 clock pulses. Thus LFSR
generates a pattern for every 256 clock pulses .this is a low power technique for generating Low
power TPG using lfsr. The output of lfsr is Ex-ored with the gray code counter which in turn
generates a random single bit changing pattern. In similar way we generate another 8bit pattern
by changing seed of the LFSR.
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begin
process(rst,clk)
begin
if rst='1' then
count <= (others =>'0');
elsif clk'event and clk='1' then
count<= count+'1';
end if;
end process;
bin_count<=count;
y <= count(7)&(count(7) xor count(6))&(count(6) xor count(5))&(count(5) xor count(4)) &
(count(4) xor count(3)) & (count(3) xor count(2)) & (count(2) xor count(1)) & (count(1) xor
count(0));
end Behavioral;
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begin
if rst='1' then
ctr<='0';
elsif clk'event and clk='1' then
if bin_count="00000000" then
ctr<='1';
else ctr<='0';
end if;
end if;
end process;
clkout <=ctr;
end Behavioral;
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component gray_code is
generic(n:integer:=8);
port(rst,clk:in std_logic;
bin_count:out std_logic_vector(n-1 downto 0);
y: out std_logic_vector(n-1 downto 0));
end component;
component LFSR_11_16_2013 is
port(
rst:
clk:
in std_logic;
in std_logic;
begin
uut:clk_gen1 port map(clk,rst,sig_clk);
uut2:LFSR_11_16_2013 port map(sig_clk,rst,pseu_rand);
uut3:gray_code port map(rst,clk,bin_count,y);
pattern_out<=pseu_rand xor y;
end Behavioral;
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entity top_fm57_8bit is
Port ( clk : in STD_LOGIC; rst : in STD_LOGIC;
patt_out1 : out STD_LOGIC_VECTOR (7 downto 0);
patt_out2 : out STD_LOGIC_VECTOR (7 downto 0);
product_out:out std_logic_vector(15 downto 0));
end top_fm57_8bit;
component pattern_bit is
port(clk,rst:in std_logic;
pattern_out:out std_logic_vector(7 downto 0));
end component;
component pattern_bit_2 is
port(clk,rst:in std_logic;
pattern_out:out std_logic_vector(7 downto 0));
end component;
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begin
patt_out1<=temp_out1;
patt_out2<=temp_out2;
end Behavioral;
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CHAPTER 6
SIMULATION RESULT
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2. Go to File Option and choose the correct Code path from the Change directory option
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3. Select the Project code path from the displayed window. And click Ok. It will go the source
directory.
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4. Open the Top level code from the open option in the File tab. It opens the code of that module.
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5. Then we should open script do files present in directory by typing the pwd (present working
directory) in the transcript window.
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6. Then we should open script do files present in directory by Typing the dir * do in the
transcript window.
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7. It opens the All Do files written in the project. Then select the fine named as do build.do and
copy the Transcript window with do as prefix (do build_tb_fault_new.do). Do build.do is a script
file which compiles all the modules that are involved in the given directory .
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8. After running the build.do script file, the simulation results of the project will be displayed.
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9. These are The Total simulation results of the 8 bit test pattern generator.
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Rst
-- For reset all signals to initial position and start from new next rising edge of the
clock.
Pattern_out1: This is the output from the low power Test pattern generator . it is a single bit
changing pattern with reduced switching activities. It is given as an input to the multiplier.
Pattern_out2: This is the output from the Test pattern generator . It is a single bit changing
pattern with reduced switching activities . It is given as second input to the 8 bit multiplier or
ALU.
Product: This is a final output for the 8bit . We are implementing 4bit shift add multiplier with
the input taken from the pattern generators.
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Above figure shown is the block diagram for N bit test pattern generator. Here Gray code is used
for reducing the switching activities and LFSR is used for random pattern generation scheme.
Additional to this we are going to implement Clock gating technique.
The new clock is generated depending on the binary count. For a 4 bit pattern generation new
clock is generated for every 16 clock pulse. In the similar manner for 8 bit pattern generation
new clock is generated for every 256 clock pulses.
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Rst
-- For reset all signals to initial position and start from new next rising edge of the
clock.
Pseu_rand: This is the LFSR (linear feedback shift register) output. It is activated for every 16
clock pulses. so a new pattern will be generated for every 16 clk pulses.
Y: this signal gives the output of gray code counter
Sig_clk: This is the clock gated signal given as an input clock for LFSR. So LFSR is triggered on
the Rising edge of this clock.
Pattern out : This signal is the output of the LP-Test pattern generator. By applying XOR
operation on Pseu_rand and Y, this output is obtained which is a single bit changing pattern.
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Other pattern generator is implemented in the similar manner as explained above except the
Initial seed in the lfsr is modified to generate the different patterns. The simulation results for 8
Bit LFSR, Gray code counter, Binary counter , multiplier are shown below.
Binary counter :
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8 Bit ALU :
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CHAPTER-7
ADVANTAGES,DISADVANTAGES AND APPLICATIONS
ADVANTAGES:
Economical
Fault Coverage
Controllability
Obsevability
DIS ADVANTAGES:
APPLICATIONS:
Pattern Generators
Counters
Encryption
Compression
Checksums
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CHAPTER:8
FUTURE SCOPE AND CONCLUSION
Future scope:
Concept of LFSR and Cellular automata can be combined in order to get better degree
of randomness and cover more number of faults with few number of patterns
Conclusion:
An efficient test pattern generator (TPG) method had been proposed to reduce the test power and
uses a modified pseudo-random pattern generator to produce seeds and then operates with the
single input changing generator and an exclusive-OR array, thus pseudo-random signal input
changing sequences are generated, which greatly minimize circuit switching activities and test
power. The experimental result shows 30.87% reduction in test power. Test Pattern generator
also reduces the instantaneous power violation compared to conventional LFSR
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CHAPTER 9
REFERENCES
BOYE and Tian-Wang Li, A novel BIST scheme for low power
testing, 2010 IEEE.
www.Wikipedia.com
http://www.hindawi.com/journals/vlsi/2011/948926/
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