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Tutorial 16
Instructor Biographies
Cheryl Tulkoff has over 22 years of experience in electronics manufacturing with an emphasis on
failure analysis and reliability. She has worked throughout the electronics manufacturing life cycle
beginning with semiconductor fabrication processes, into printed circuit board fabrication and
assembly, through functional and reliability testing, and culminating in the analysis and evaluation
of field returns. She has also managed no clean and RoHS-compliant conversion programs and
has developed and managed comprehensive reliability programs.
Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech. She is a
published author, experienced public speaker and trainer and a Senior member of both ASQ and
IEEE. She holds leadership positions in the IEEE Central Texas Chapter, IEEE WIE (Women In
Engineering), and IEEE ASTR (Accelerated Stress Testing and Reliability) sections. She chaired
the annual IEEE ASTR workshop for four years and is also an ASQ Certified Reliability Engineer.
Dr. Viktor Tiederle has over 29 years of experience in interconnection technology for
microelectronic devices. He has worked in nearly all areas from development to production with the
emphasis on quality and reliability. He started with his work in thick film technology and soldering
techniques in SMD ceramics in the early 1980s. Later we worked in wire bonding technique as well
as in adhesive technology and developing micromechanical devices for automotive applications.
Since more than 10 years he is responsible for many projects within the automotive as well as
other industrial segments, for example in photovoltaic.
Viktor earned his Diploma of Physics at the Technical University of Munich and Stuttgart. After
some years of industrial work he received his Dr.-Eng. degree with a studying Design of
Experiments used for wire bonding technique in several applications. Viktor works in several
working groups in the automotive industry for qualifying components for the use in such hazard
environments.
3/16/2012
Tutorial Outline
MODULE 1: INTRODUCTIONS
MODULE 2: COMPONENTS
Selection
Critical Components
Electrostatic Discharge
Plating Material
Miscellaneous
Lifetime
3/16/2012
Why DfR?
Architectural Design for Reliability, R. Cranwell and R. Hunter, Sandia Labs, 1997
3/16/2012
Mechanical Designer
PCB Layout
Other aspects of
electronic packaging
3/16/2012
10
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Reality (continued)
Predicting reliability is becoming
problematic
Standard MTBF calculations can tend to be
inaccurate
A physics-of-failure (PoF)
approach can be timeintensive and not always
definitive (limited insight
into performance during
operating life)
11
12
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3/16/2012
Process Variability
confidence bounds
100
Airplanes
Mean
Service 10
life, yrs.
Computers
laptop/palm
cell phones
1.0
0.1
Technology
0.5 m
0.25 m
130 nm
1995
65 nm
2005
35 nm
2015
Year produced
Known trends for TDDB, EM and HCI degradation
(ref: extrapolated from ITRS roadmap)
15
IC Wearout (continued)
10
FIT (000)
Dielectric
breakdown
failure rate vs.
feature size
Future
In design
6
4
Estimated
In
production
2
0
Measured
180
130
90
65
45
Feature size, nm
16
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17
Cycles to failure
-40 to 125C
QFP: >10,000
3/16/2012
SJ Wearout (cont.)
Design change: More silicon, less plastic
Increases mismatch in coefficient of thermal
expansion (CTE)
19
IPC
Specification body for electronic OEMs
20
10
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Reliability engineer?
Depends. Many classic reliability engineers
provide NO value in the DfR / PoF process due to
over-emphasis on statistical techniques and
environmental testing
22
11
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Component Selection
The process of creating the bill of
materials (BOM) during the virtual design
process
Before physical layout
23
24
12
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Critical Components
Most small to mid-size organizations do not have the resources to
perform a thorough part selection assessment on every part
Does not excuse performing this activity
Requires focusing on components critical to the design
25
Memory devices
Non-volatile memory has limited data retention time and
write cycles
26
13
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Electronic modules
Part is a miniature assembly (no longer a commodity item)
Power components
Fuses
Susceptible to quality issues
Electrolytic capacitors
Depending on environment, wear out can initiate far before
20 years
27
Popcorning
Qualcomm
Sonoscan
28
14
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29
Cogiscan
15
3/16/2012
Material issues
Solutions
31
Temperature Sensitivity
32
16
3/16/2012
Use ESD Protection on all susceptible parts (not just System I/Os)
Box or System I/O
ESD Rating < Class 2 IEC 1000-4-2 (4000V) MANDATORY
34
17
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18
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Critical Components
JEDEC JESD201
How to Mitigate?
There are three basic approaches to
mitigation
Data Gathering and Monitoring
Part Manufacturer Mitigation
Steps offered by your suppliers
38
19
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Few to no military/avionics
manufacturers are using this approach
39
Nickel underplate between the tin plating and the copper leadframe
Some question about effectiveness (IBM vs. TI)
Some question about minimum thickness
40
20
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41
OEM Mitigation
Four Options
Procurement, Re-packaging, Post-plate or dip, Conformal
coat
Procurement / Design
Select only components with SnPb or Pd plating
May require complete change in circuit design if alternative
component required
Rarely performed (functionality trumps reliability)
21
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Buckling
Based on calculations (Leidecker, NASA)
Not experimentally proven
Limitations
Insufficient coverage at leads (gravity)
Problems with conformal coat may
outweigh possible risk avoidance
Leadframe
Current status:
Conformal Coating
Tin Whisker
Conformal Coating
Component Selection
(Lifetime)
DfR (Miscellaneous)
Components taller then 1 inch
Use of staking compound to adhere to board
44
22
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45
46
23
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Drivers
Cracking/separation of coating/termination
Poor manufacturing
Thermal shock
47
Newer, polymeric
capacitors are available
Significant reduction in ESR
Less derating
No risk of ignition
48
24
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Electrolytic Capacitors
Voltage
Maintain a minimum of 25-33% of rated
voltage (maintains the dielectric)
Temperature
Maintain adequate distance from hot
components
Power resistors, IGBTs, etc.
Seems to accelerate time to failure and can
induce explosive rupturing
Ripple Current
Up to 100% or greater of rated ripple current
Need to calculate/measure case temperature rise
Equivalency on bill of materials is often not maintained
Separable Connectors
Separable Connectors
One of the most common failure sites
First thing maintenance checks (plug / unplug)
25
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Material specifications
Contact specifications
50-100 grams contact force
Minimum of 2 contacts; 4
preferred
Adequate contact wipe
0.010 min.
No mating with tin plating
51
52
26
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Component Lifetime
53
Minimum Guarantee
Units
Endurance
100,000
Store cycles
1,000,000
Store cycles
Data retention
100
Years
54
27
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55
56
28
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57
Relays/Switches (continued)
Selection of appropriate plating
Idle for long periods of time: Gold contacts
Numerous cycles: AgCd contacts
Temperature rise
Wide range of contact resistance in specifications
58
29
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Wearout of Relays/Switches
59
60
30
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Component Ratings
Definition
A specification provided
by component
manufacturers that guides
the user as to the
appropriate range of
stresses over which the
component is guaranteed
to function
Typical parameters
Voltage
Current
Power
Temperature
61
Derating
Goals of derating
Maintain critical parameters during operation (i.e., functionality)
Provide a margin of safety from deviant lots
Achieve desired operating life (i.e., reliability)
62
31
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63
Derating Failures
Where are the derating mistakes?
Problem #1: Designers do not derate
Failure to perform component stress analysis
32
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Failure to Derate
Analog / Power Designs
Derating is typically overlooked during
transient events
Especially turn-on, turn-off
Digital
Excessive number of components and
connections tends to limit attempts to perform
component stress analysis
65
Manufacturers viewpoint
Ratings are based on specific design rules based on materials,
process, and reliability testing
The reality
Ratings can be driven by tradition and market forces as much as
science
Best practice
Based on data from field returns
Based on test to failure qualification (especially for new
suppliers)
66
33
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67
34
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Manuf.
Rating
Test
Results
Stress
OEM was concerned with voltage rating of tantalum capacitors
after 2 reflows and use on low resistance line
Performed step stress surge test (SSST)
Derived voltage derating based on a sub-ppm failure rate
69
35
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Robustness - Components
o
Concerns
o
Drivers
o
NAMICS
AVX
Three manifestations
o
o
o
36
3/16/2012
Variations in voltage or
temperature will drive crack
propagation
Induces a different failure
mode
o
DfR
Actions: Design
o
o
o
o
74
74
37
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Actions: Manufacturing
o
Solder reflow
o
o
o
o
Wave soldering
o
Touch up
o
Eliminate
75
75
76
38
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Cell Phones:
Laptop Computers:
Desktop Computers:
Medical (External):
Medical (Internal):
High-End Servers:
Industrial Controls:
Appliances:
Automotive:
Avionics (Civil):
Avionics (Military):
Telecommunications:
18 to 36 months
24 to 36 months
24 to 60 months
5 to 10 years
7 years
7 to 10 years
7 to 15 years
7 to 15 years
10 to 15 years (warranty)
10 to 20 years
10 to 30 years
10 to 30 years
77
Identify Field
Environment
MIL HDBK310
78
39
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Manufacturing
Transportation
Storage
Field
79
40
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Measure when
Certain aspects of your environment are unique
Strong relationship with customer
82
41
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Problem
Sulfur reacts with silver
Induces creeping corrosion
83
Occurred primarily in
environments with high
sulfur levels
Rubber manufacturing
Gasoline refineries
Waste treatment plants
84
42
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Findings
Analysis identified copper as
the creeping element (not
silver)
Cross-sections identified
corrosion sites near areas with
no or minimal immersion silver
Galvanic reaction was initiating
and accelerating corrosion
behavior
85
Failure #2
Industry test environments are limited to 70%RH (chamber
limitations)
Actual use environment can be more severe
Telcordia
86
43
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87
Alternatives to PoF
Step 1: Rules of Thumb
Step 2: Best Practice
Follow part selection guidelines
Step 3: Norris-Landsberg
88
44
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90
45
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Norris-Lanzberg (SAC)
N. Pan et al, An Acceleration Model For Sn-Ag-Cu Solder Joint Reliability Under Various Thermal Cycle Conditions.
pp. 876-883, SMTAI, September 2005, Chicago, IL
92
46
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Long-Term Reliability
Rules of Thumb, Best Practices, and
Norris-Landzberg are not always sufficient
Good first pass
93
94
47
3/16/2012
Increased Warpage
Solder Mask Discoloration
Pad Cratering
Blistering
Delamination
Land
Separation
PTH Cracks
95
95
o
o
o
96
96
48
3/16/2012
IR-240~250
Board thickness
60mil
Tg140 Dicy
All HF materials OK
60mil
60~73mil
Tg150 Dicy
NP150, TU622-5
All HF materials OK
60~73mil
73~93mil
IR-260
Tg150 Dicy
HF- middle and high Tg materials OK
Tg170 Dicy
HF middle and high Tg materials OK
73~93mil
93~130mil
Phenolic Tg170
IS410, IT180, PLC-FR-370 Turbo, TU7227
HF middle and high Tg materials OK
93~120mil
121~160mil
Phenolic Tg170
IS410, IT180, PLC-FR-370 Turbo
TU722-7
HF high Tg materials OK
131mil
PhenolicTg170 + Filler
IS415, 370 HR, 370 MOD, N4000-11
HF material - TBD
161mil
161mil
1.Copper
2.Copper
3.Twice
98
98
49
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99
100
50
3/16/2012
PCB Delamination
Additional Observations
Drivers
Sequential Lamination
Limited information
Controlled depth drilling
102
51
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Moisture Absorption
103
Yes
DfR customer found improvement after 48 hrs
at 125C
A number of companies now require 5 24
hour bake before reflow
IBM found improvement with coupons with
nominal copper
DfR observed more rapid degradation of boards
exposed to moisture, even after multiple reflows
Some customers specifying maximum moisture
absorption
52
3/16/2012
105
106
106
53
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54
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Voids
Can cause large stress concentrations, resulting
in crack initiation.
Etch pits
109
109
Overstress cracking
CTE mismatch places PTH in
compression
Pressure applied during "bed-of-nails"
can compress PTH
In-circuit testing (ICT) rarely performed
at operating temperatures
Fatigue
Circumferential cracking of the copper
plating that forms the PTH wall
Driven by differential expansion between
the copper plating (~17 ppm) and the
out-of-plane CTE of the printed board
(~70 ppm)
Industry-accepted failure model: IPCTR-579
110
110
55
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111
111
112
112
56
3/16/2012
CAF: Examples
A
A:A Cross-Section
113
113
LF
Laminate Load
Bearing
Capability
LF limit
PbSn
PbSn limit
PCB deflection
114
57
3/16/2012
Review/perform ICT strain evaluation at fixture mfg and in process: 500 us, IPC
9701 and 9704 specs, critical for QFN, CSP, and BGA
http://www.rematek.com/download_center/board_stress_analysis.pdf
To reduce the pressures exerted on a PCB, the first and simplest solution is to
reduce the probes forces, when this is possible.
Secondly, the positioning of the fingers/stoppers must be optimized to control
the probe forces. But this is often very difficult to achieve. Mechanically, the
stoppers must be located exactly under the pressure fingers to avoid the
creation of shear points
115
115
116
116
58
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Pad Cratering
Intel (2006)
Drivers
117
117
118
59
3/16/2012
Alternative approach
Require reporting of fracture toughness and
elastic modulus
119
60
3/16/2012
Dont use ROSE or Omegameter test as single option (at all? Risk from dirty IPA)
Sampling criteria
121
122
61
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123
124
62
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126
63
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127
Relationship Management. Ideally, you choose a strategy that allows you to partner
with your PCB suppliers for success. This is especially critical is you have low
volumes, low spend, or high technology and reliability requirements for your PCBs.
Some good practices include:
Monthly conference calls with your PCB commodity team and each PCB
supplier. The PCB supplier team should members equivalent to your team
members.
QBRs (quarterly business reviews) which review spend, quality, and
performance metrics, and also include state of the business updates which
address any known changes like factory expansion, move, or relocation, critical
staffing changes, new equipment/capability installation etc.
The sharing is done from both sides with you sharing any data which you think would help strengthen
the business relationship business growth, new product and quoting opportunities, etc. At least twice
per year, the QBRs should be joint onsite meetings which alternate between your site and the supplier
factory site. The factory supplier site QBR visit can double as the annual on site visit and audit that you
perform.
64
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129
130
65
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131
66
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0 Frame conditions
1 Establishing processes
2 Design of experiments
3 Monitoring
-
Capability
Design Index
Outlier
Expectations of customer
reputation of manufacturer!
customer satisfaction?
- e.g. automotive:
15 years thereof 2 years warranty
Increasing functionality
/ complexity of product
reduction of tests?
67
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Introduction
Verification
Production
Step 3
Step 2
Process known?
Monitoring established?
Watching cpk
Outlier detection
Design Index DI
Sensitive variables
known?
Running with
optimum
parameters?
Step 1
Investigation
with DoE
Target
-
Procedure
Step 1: Design of Experiments (DoE[1])
Step 2: Process control including statistical calculation (SPC[2] / DI[3])
Step 3: Detecting potential field failures
68
3/16/2012
Introduction of processes
Key questions
-
Time frame
Parameter
(input factor)
Ei
Production
process
Disturbing
S
parameter i
Result
(Target parameter)
Zj
Missing
parameter
i: input
j: output
69
3/16/2012
75
80
85
90
Measured value
statistical spread
95 100 105
Factor [units]
110
115
120
No dependence
Quadratic dependence
Step 1 / Procedure
Process to be investigated?
Calculation of results
-
Dependence of parameters
Prediction
Example
Reflow soldering process
Parameters:
-
Reflow Oven
Atmosphere
Solder paste
Mask type
Profile
Type
Delivery
70
3/16/2012
Reflow Oven
Atmosphere
Profile
Type
Delivery
Solder paste
Mask type
Limits and Experimental plan
Jun
Jul
Aug
Sep
Okt
Nov
Oven
Oven Profile
Normal old
Normal new
Normal new
Normal new
Nitrogen new
Nitrogen new
Solder paste
Type
delivery Mask typeTombstoneBridges Total failure
A
glass
big
46
6
53
A
glass
big
29
12
43
big
B
glass
11
12
25
B
cartridge small
32
15
47
B
glass
small
12
3
16
B
glass
small
2
2
6
Reason ?
40
30
20
10
0
Jun
tombstone
Jul
Solder bridge
Aug
Sep
not soldered
Oct
Nov
other failure
71
3/16/2012
21
L: B" to A"
18
P: "new" to old"
17
O: Nitrogen to normal
0
4
2
10 12 14 16 18 20 22
Additional information:
Data not complete
Model contains not all input factors
12.5
S: "small" to "big"
9.5
6
P: old" to "new"
L: A" to B" 0
0
4
6
8
10
Estimated Main Effects
12
14
Additional information:
Model describes the data nearly complete
that means: there are no other input factors
72
3/16/2012
Optimized
-
Parameter Delivery
glass
Mask type
small
Profile
new
Oven
Solder paste
Nitrogen
Normal
43 ppm
25 ppm
Introduction
Verification
Production
Step 2
Capability study done?
Machine
cmk
Process
cpk
Design Index DI
73
3/16/2012
Design-Index
Count
Count
Speclow
Spechigh
cpk
x
USL
s
Speclow A
B Spechigh
Capability index
Mean value
Upper specification limit
Standard deviation
DI
Design index
M = (A + B)
xmi
USL
xiCL
25
20
15
10
5
0
10
45
Measurement at RT
35
Different results at
LT and HT
25
15
5
0
10
30
CLT = 2,27
CRT = 2,23
1,39
CHT = 2,45
25
20
15
10
5
0
0
Spec-max
Worst Case / min
Gauss
5
PAT / max
PAT / min
Parameter
DI =
10
74
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Variation
1,0
0,5
Temperature
Voltage
0,0
-0,5
-1,0
-1,5
Within the
limits
LTU1 LTU2 LTU3 LTU4 LTU5 LTU6 RTU1RTU2RTU3RTU4RTU5RTU6HTU1HTU2HTU3HTU4HTU5HTU6
Error bars: distribution with DI = 1,59
Parameter1
lower specification limit
upper specification limit
95% of values
Firma B / Produkt A / LT: -40C; RT: +25C; HT: +95C / U1: 3,1V; U2: 3,3V; U3: 3,4V
3,6
Variation
3,4
3,2
Temperature
Voltage
3,0
2,8
2,6
2,4
2,2
2,0
LTU1
Parameter2
LTU2
RTU1
RTU2
HTU1
HTU2
Partly outside
of limits
DI = 0,82
Introduction
Verification
Production
Step 3
Monitoring established?
Watching cpk
Outlier detection
75
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Task
- Search for outliers
Procedure
-
Step 3 - Task
Distribution
process, product
Drift behavior
product
product
50
45
40
35
30
25
20
15
10
5
0
0,0
A)
0,1
0,2
Spec-max
Worst Case / min
Gauss
0,3
0,4
PAT / max
PAT / min
DDJ
B)
0,5
0,6
0,7
0,8
76
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Step 3 / Procedure
Statistical calculation
-
robust mean
{61}
Identification of outlier
BauelementParameter
BE-1
8,24
BE-2
9,67
BE-3
9,19
BE-4
8,81
BE-5
9,76
18,0
BE-6
BE-7
8,57
BE-8
9,04
BE-9
9,15
BE-10
8,79
BE-11
9,54
BE-12
9,33
BE-13
9,3
BE-14
8,97
BE-15
8,51
BE-16
9,08
BE-17
8,91
BE-18
8,87
BE-19
8,92
BE-20
8,79
BE-21
9,54
BE-22
8,5
BE-23
8,53
BE-24
9,55
BE-25
8,48
BE-26
9,66
BE-27
9,12
BE-28
9,46
BE-29
9,14
BE-30
8,97
77
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Measurements with
normal distribution
(approximately)
2 measurements outside
of calculated limits
Anzahl: 231
Special investigation
necessary:
high potential of failure?
No delivery!
78
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Reason
measurement at limit
of resolution
(quantification)
Outlier
All measurements
within
specification limits
Capability index
okay (2,11)
3 not normal
values
79
3/16/2012
Conclusions
PoF is a powerful tool that can leverage the value of DfR activities
Contact Information
RELNETyX
Cheryl Tulkoff,
ctulkoff@dfrsolutions.com
Mobile: 512-913-8624
info@dfrsolutions.com
www.dfrsolutions.com
Austin, TX
80