Verilog Examples

Asynchronous reset D- FF
1 //----------------------------------------------------2 // Design Name : dff_async_reset

3 // File Name
: dff_async_reset.v
4 // Function
: D flip-flop async reset
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module dff_async_reset (
8 data , // Data Input
9 clk
, // Clock Input
10 reset , // Reset input
11 q
// Q output
12 );
13 //-----------Input Ports--------------14 input data, clk, reset ;
15
16 //-----------Output Ports--------------17 output q;
18
19 //------------Internal Variables-------20 reg q;
21
22 //-------------Code Starts Here--------23 always @ ( posedge clk or negedge reset)
24 if (~reset) begin
25
q <= 1'b0;
26 end else begin
27
q <= data;
28 end
29
30 endmodule //End Of Module dff_async_reset
You could download file dff_async_reset.v here
Synchronous reset D- FF
1 //----------------------------------------------------2 // Design Name : dff_sync_reset

3 // File Name
: dff_sync_reset.v
4 // Function
: D flip-flop sync reset
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module dff_sync_reset (
8 data
, // Data Input
9 clk
, // Clock Input
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q
// Q output
);
//-----------Input Ports--------------input data, clk, reset ;
//-----------Output Ports--------------output q;
//------------Internal Variables-------reg q;
//-------------Code Starts Here--------always @ ( posedge clk)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule //End Of Module dff_sync_reset
Asynchronous reset T - FF
1 //----------------------------------------------------2 // Design Name : tff_async_reset

3 // File Name
: tff_async_reset.v
4 // Function
: T flip-flop async reset
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module tff_async_reset (
9 clk
, // Clock Input
11 q
// Q output
12 );
19 //-------------Code Starts Here--------20 always @ ( posedge clk or negedge reset)
22
q <= 1'b0;
23 end else if (data) begin
24
q <= ! q;
25 end
26
27 endmodule //End Of Module tff_async_reset
You could download file tff_async_reset.v here
Synchronous reset T - FF
1 //----------------------------------------------------2 // Design Name : tff_sync_reset

3 // File Name
: tff_sync_reset.v
4 // Function
: T flip-flop sync reset
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module tff_sync_reset (
9 clk
, // Clock Input
11 q
// Q output
12 );
19 //-------------Code Starts Here--------20 always @ ( posedge clk)
22
q <= 1'b0;
23 end else if (data) begin
24
q <= ! q;
25 end
26
27 endmodule //End Of Module tff_async_reset
Regular D Latch
1 //---------------------------------------------------2 // Design Name : dlatch_reset

3 // File Name
: dlatch_reset.v
4 // Function
: DLATCH async reset
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module dlatch_reset (
8 data
, // Data Input
9 en
, // LatchInput
11 q
// Q output
12 );
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//-----------Input Ports--------------input data, en, reset ;

//-----------Output Ports--------------output q;
//------------Internal Variables-------reg q;
//-------------Code Starts Here--------always @ ( en or reset or data)
if (~reset) begin
q <= 1'b0;
end else if (en) begin
q <= data;
end
8-Bit Simple Up Counter
1 //---------------------------------------------------2 // Design Name : up_counter

3 // File Name
: up_counter.v
4 // Function
: Up counter
5 // Coder
: Deepak
6 //---------------------------------------------------7 module up_counter
(
8 out
, // Output of the counter
9 enable , // enable for counter
10 clk
, // clock Input
11 reset
// reset Input
12 );
13 //----------Output Ports-------------14
output [7:0] out;
15 //------------Input Ports-------------16
input enable, clk, reset;
17 //------------Internal Variables-------18
reg [7:0] out;
19 //-------------Code Starts Here------20 always @(posedge clk)
21 if (reset) begin
22
out <= 8'b0 ;
23 end else if (enable) begin
24
out <= out + 1;
25 end
26
27
28 endmodule
8-Bit Up Counter With Load
1 //---------------------------------------------------2 // Design Name : up_counter_load

3 // File Name
: up_counter_load.v
4 // Function
: Up counter with load
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module up_counter_load
(
8 out
9 data
, // Parallel load for the counter
10 load
, // Parallel load enable
11 enable
, // Enable counting
12 clk
, // clock input
13 reset
// reset input
14 );
15 //----------Output Ports-------------16 output [7:0] out;
17 //------------Input Ports-------------18 input [7:0] data;
19 input load, enable, clk, reset;
20 //------------Internal Variables-------21 reg [7:0] out;
22 //-------------Code Starts Here------23 always @(posedge clk)
24 if (reset) begin
25
out <= 8'b0 ;
26 end else if (load) begin
27
out <= data;
29
out <= out + 1;
30 end
31
32 endmodule
8-Bit Up-Down Counter
1 //---------------------------------------------------2 // Design Name : up_down_counter

3 // File Name
: up_down_counter.v
4 // Function
: Up down counter
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module up_down_counter
(
8 out
9 up_down , // up_down control for counter
10 clk
, // clock input
11 data
, // Data to load
12 reset
// reset input
13 );
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//----------Output Ports-------------output [7:0] out;

//------------Input Ports-------------input [7:0] data;
input up_down, clk, reset;
//------------Internal Variables-------reg [7:0] out;
//-------------Code Starts Here------always @(posedge clk)
if (reset) begin // active high reset
out <= 8'b0 ;
end else if (up_down) begin
out <= out + 1;
end else begin
out <= out - 1;
end
endmodule
Random Counter (LFSR)
1 //---------------------------------------------------2 // Design Name : lfsr

3 // File Name
: lfsr.v
4 // Function
: Linear feedback shift register
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module lfsr
(
8 out
9 enable
, // Enable for counter
10 clk
, // clock input
11 reset
// reset input
12 );
13
18 input enable, clk, reset;
21 wire
linear_feedback;
22
23 //-------------Code Starts Here------24 assign linear_feedback = ! (out[7] ^ out[3]);
25
26 always @(posedge clk)
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if (reset) begin // active high reset

out <= 8'b0 ;
end else if (enable) begin
out <= {out[6],out[5],
out[4],out[3],
out[2],out[1],
out[0], linear_feedback};
end
endmodule // End Of Module counter
You could download file lfsr.v here
LFSR Up/Down
1 `define WIDTH 8
2 module lfsr_updown (
3 clk
,
// Clock input
4 reset
,
// Reset input
5 enable
,
// Enable input
6 up_down
,
// Up Down input
7 count
,
// Count output
8 overflow
// Overflow output
9 );
10
11 input clk;
12 input reset;
13 input enable;
14 input up_down;
15
16 output [`WIDTH-1 : 0] count;
17 output overflow;
18
19 reg [`WIDTH-1 : 0] count;
20
21 assign overflow = (up_down) ? (count == {{`WIDTH1{1'b0}}, 1'b1}) :
22
(count == {1'b1,
{`WIDTH-1{1'b0}}}) ;
23
25 if (reset)
26
count <= {`WIDTH{1'b0}};
27 else if (enable) begin
28
if (up_down) begin
29
count
<=
{~(^(count
&
`WIDTH'b01100011)),count[`WIDTH-1:1]};
30
end else begin
31
count <= {count[`WIDTH-2:0],~(^(count &
`WIDTH'b10110001))};
32
end
33 end
34
35 endmodule
Random Counter (LFSR)
1 //---------------------------------------------------2 // Design Name : lfsr

3 // File Name
: lfsr.v
4 // Function
: Linear feedback shift register
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module lfsr
(
8 out
9 enable
, // Enable for counter
10 clk
, // clock input
11 reset
// reset input
12 );
13
18 input enable, clk, reset;
21 wire
linear_feedback;
22
23 //-------------Code Starts Here------24 assign linear_feedback = ! (out[7] ^ out[3]);
25
27 if (reset) begin // active high reset
28
out <= 8'b0 ;
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out <= {out[6],out[5],
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out[4],out[3],
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out[2],out[1],
33
out[0], linear_feedback};
34 end
35
36 endmodule // End Of Module counter
You could download file lfsr.v here
LFSR Up/Down
1 `define WIDTH 8
2 module lfsr_updown (
3 clk
,
// Clock input
4 reset
,
// Reset input
5 enable
,
// Enable input
6 up_down
,
// Up Down input
7 count
,
// Count output
8 overflow
// Overflow output
9 );
10
11 input clk;
12 input reset;
13 input enable;
14 input up_down;
15
16 output [`WIDTH-1 : 0] count;
17 output overflow;
18
19 reg [`WIDTH-1 : 0] count;
20
21 assign overflow = (up_down) ? (count == {{`WIDTH1{1'b0}}, 1'b1}) :
22
(count == {1'b1,
{`WIDTH-1{1'b0}}}) ;
23
25 if (reset)
26
count <= {`WIDTH{1'b0}};
27 else if (enable) begin
28
if (up_down) begin
29
count
<=
{~(^(count
&
`WIDTH'b01100011)),count[`WIDTH-1:1]};
30
end else begin
31
count <= {count[`WIDTH-2:0],~(^(count &
`WIDTH'b10110001))};
32
end
33 end
34
35 endmodule
You could download file lfsr_updown.v here
1 module tb();
2 reg clk;
3 reg reset;
4 reg enable;
5 reg up_down;
6
7 wire [`WIDTH-1 : 0] count;
8 wire overflow;
9
10 initial begin
11
$monitor("rst %b en %b updown %b cnt %b overflow
%b",
12
reset,enable,up_down,count, overflow);
13
clk = 0;
14
reset = 1;
15
enable = 0;
16
up_down = 0;
17
#10 reset = 0;
18
#1 enable = 1;
19
#20 up_down = 1;
20
#30 $finish;
21 end
22
23 always #1 clk = ~clk;
24
25 lfsr_updown U(
26 .clk
( clk
),
27 .reset
( reset
),
28 .enable
( enable
),
29 .up_down ( up_down ),
30 .count
( count
),
31 .overflow ( overflow )
32 );
33
34 endmodule
Gray Counter
1 //---------------------------------------------------2 // Design Name : gray_counter

3 // File Name
: gray_counter.v
4 // Function
: 8 bit gray counterS
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module gray_counter (
8
out
, // counter out
9
enable , // enable for counter
10
clk
, // clock
11
rst
// active hight reset
12
);
13
14
//------------Input Ports-------------15
input clk, rst, enable;
16
//----------Output Ports---------------17
output [ 7:0] out;
18
//------------Internal Variables-------19
wire [7:0] out;
20
reg [7:0] count;
21
//-------------Code Starts Here---------
22
always @ (posedge clk)
23
if (rst)
24
count <= 0;
25
else if (enable)
26
count <= count + 1;
27
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assign out = { count[7], (count[7] ^ count[6]),
(count[6] ^
29
count[5]),(count[5] ^ count[4]),
(count[4] ^
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count[3]),(count[3] ^ count[2]),
(count[2] ^
31
count[1]),(count[1] ^ count[0]) };
32
33 endmodule
One Hot Counter
1 //---------------------------------------------------2 // Design Name : one_hot_cnt

3 // File Name
: one_hot_cnt.v
4 // Function
: 8 bit one hot counter
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module one_hot_cnt (
8 out
9 enable
, // enable for counter
10 clk
, // clock input
11 reset
// reset input
12 );
15
16 //------------Input Ports-------------17 input enable, clk, reset;
18
21
22 //-------------Code Starts Here------23 always @ (posedge clk)
24 if (reset) begin
25
out <= 8'b0000_0001 ;
27
out <= {out[6],out[5],out[4],out[3],
28
out[2],out[1],out[0],out[7]};
29 end
30
31 endmodule
Divide by 2 Counter
1 //---------------------------------------------------2 // Design Name : clk_div

3 // File Name
: clk_div.v
4 // Function
: Divide by two counter
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7
8 module clk_div (clk_in, enable,reset, clk_out);
9
//
--------------Port
Declaration----------------------10 input
clk_in
;
11 input
reset
;
12 input
enable
;
13 output
clk_out
;
14
//--------------Port
data
type
declaration------------15 wire
clk_in
;
16 wire
enable
;
17
//--------------Internal
Registers---------------------18 reg
clk_out
;
19
//--------------Code
Starts
Here----------------------20 always @ (posedge clk_in)
21 if (reset) begin
22
clk_out <= 1'b0;
24
clk_out <= ! clk_out ;
25 end
26
27 endmodule
Divide By 3 Counter
This module divides the input clock frequency by 3
1 //---------------------------------------------------2 // Design Name : divide_by_3

3 // File Name
: divide_by_3.v
4 // Function
: Divide By 3
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------
7 module divide_by_3 (
8 clk_in
, //Input Clock
9 reset
, // Reset Input
10 clk_out
// Output Clock
11 );
12 //-----------Input Ports--------------13 input clk_in;
14 input reset;
15 //-----------Output Ports--------------16 output clk_out;
17 //------------Internal Variables-------18 reg [1:0] pos_cnt;
19 reg [1:0] neg_cnt;
20 //-------------Code Start----------------21 // Posedge counter
22 always @ (posedge clk_in)
23 if (reset) begin
24
pos_cnt <= 0;
25 end else begin
26
pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;
27 end
28 // Neg edge counter
29 always @ (negedge clk_in)
30 if (reset) begin
31
neg_cnt <= 0;
32 end else begin
33
neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;
34 end
35
36 assign clk_out = ((pos_cnt ! = 2) && (neg_cnt
2));
37
38 endmodule
39
40 // Testbench to check the divide_by_3 logic
41 module test();
42 reg reset, clk_in;
43 wire clk_out;
44 divide_by_3 U (
45
.clk_in (clk_in),
46
.reset (reset),
47
.clk_out (clk_out)
48 );
49
50 initial begin
51
clk_in = 0;
52
reset = 0;
53
#2 reset = 1;
54
#2 reset = 0;
55
#100 $finish;
56 end
57
58 always #1 clk_in = ~clk_in;
59
60 endmodule
Divide By 4.5 Counter
! =
1 //---------------------------------------------------2 // Design Name : clk_div_45

3 // File Name
: clk_div_45.v
4 // Function
: Divide by 4.5
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module clk_div_45 (
8 clk_in, // Input Clock
9 enable, // Enable is sync with falling edge of clk_in
10 clk_out // Output Clock
11 );
12
13
//
--------------Port
clk_in
;
15 input
enable
;
16 output
clk_out
;
17
18
//--------------Port
data
type
declaration------------19 wire
clk_in
;
20 wire
enable
;
21 wire
clk_out
;
22
23
//--------------Internal
Registers---------------------24 reg
[3:0] counter1
;
25 reg
[3:0] counter2
;
26 reg
toggle1
;
27 reg
toggle2
;
28
29
//--------------Code
Starts
Here----------------------30 always @ (posedge clk_in)
31 if (enable == 1'b0) begin
32
counter1 <= 4'b0;
33
toggle1 <= 0;
34 end else if ((counter1 == 3 && toggle2) || (~toggle1
&& counter1 == 4)) begin
35
counter1 <= 4'b0;
36
toggle1 <= ~toggle1;
37 end else
begin
38
counter1 <= counter1 + 1;
39 end
40
41 always @ (negedge clk_in)
42 if (enable == 1'b0) begin
43
counter2 <= 4'b0;
44
toggle2 <= 0;
45 end else if ((counter2 == 3 && ~toggle2) || (toggle2
&& counter2 == 4)) begin

46
counter2 <= 4'b0;
47
toggle2 <= ~toggle2;
48 end else
begin
49
counter2 <= counter2 + 1;
50 end
51
52 assign
clk_out = (counter1 <3 && counter2 < 3) &
enable;
53
54 endmodule
Single Port RAM Synchronous Read/Write
1 //---------------------------------------------------2 // Design Name : ram_sp_sr_sw

3 // File Name
: ram_sp_sr_sw.v
4 // Function
: Synchronous read write RAM
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module ram_sp_sr_sw (
8 clk
, // Clock Input
9 address
, // Address Input
10 data
, // Data bi-directional
11 cs
, // Chip Select
12 we
, // Write Enable/Read Enable
13 oe
// Output Enable
14 );
15
16 parameter DATA_WIDTH = 8 ;
17 parameter ADDR_WIDTH = 8 ;
18 parameter RAM_DEPTH = 1 << ADDR_WIDTH;
19
20 //--------------Input Ports----------------------21 input
clk
;
22 input [ADDR_WIDTH-1:0] address
;
23 input
cs
;
24 input
we
;
25 input
oe
;
26
27 //--------------Inout Ports----------------------28 inout [DATA_WIDTH-1:0] data
;
29
30 //--------------Internal variables---------------31 reg [DATA_WIDTH-1:0] data_out ;
32 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
33 reg
oe_r;
34
35 //--------------Code Starts Here-----------------36
37 // Tri-State Buffer control
38 // output : When we = 0, oe = 1, cs = 1
39 assign data = (cs && oe && ! we) ? data_out : 8'bz;
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// Memory Write Block

// Write Operation : When we = 1, cs = 1
begin : MEM_WRITE
if ( cs && we ) begin
mem[address] = data;
end
end
// Memory Read Block
// Read Operation : When we = 0, oe = 1, cs = 1
begin : MEM_READ
if (cs && ! we && oe) begin
data_out = mem[address];
oe_r = 1;
end else begin
oe_r = 0;
end
end
endmodule // End of Module ram_sp_sr_sw
Single Port RAM Asynch Read, Synch Write
1 //---------------------------------------------------2 // Design Name : ram_sp_ar_sw

3 // File Name
: ram_sp_ar_sw.v
4 // Function
: Asynchronous read write RAM
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module ram_sp_ar_sw (
8 clk
, // Clock Input
9 address
, // Address Input
10 data
11 cs
, // Chip Select
12 we
13 oe
// Output Enable
14 );
15
19
20 //--------------Input Ports----------------------21 input
clk
;
22 input [ADDR_WIDTH-1:0] address ;
23 input
cs
;
24 input
we
;
25
;
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input
oe
//--------------Inout Ports----------------------inout [DATA_WIDTH-1:0] data

;
//--------------Internal variables---------------reg [DATA_WIDTH-1:0]
data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
//--------------Code Starts Here-----------------// Tri-State Buffer control
// output : When we = 0, oe = 1, cs = 1
assign data = (cs && oe && ! we) ? data_out : 8'bz;
begin : MEM_WRITE
end
end
always @ (address or cs or we or oe)
begin : MEM_READ
end
end
endmodule // End of Module ram_sp_ar_sw
Single Port RAM Asynchronous Read/Write
1 //---------------------------------------------------2 // Design Name : ram_sp_ar_aw

3 // File Name
: ram_sp_ar_aw.v
4 // Function
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module ram_sp_ar_aw (
8 address
, // Address Input
9 data
10 cs
, // Chip Select
11 we
12 oe
// Output Enable
13 );
15
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;
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;
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;
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parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports----------------------input [ADDR_WIDTH-1:0] address ;
input
cs
input
we
input
oe
//--------------Inout Ports----------------------inout [DATA_WIDTH-1:0] data

;
//--------------Internal variables---------------reg [DATA_WIDTH-1:0]
data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
//--------------Code Starts Here-----------------// Tri-State Buffer control
// output : When we = 0, oe = 1, cs = 1
assign data = (cs && oe && ! we) ? data_out : 8'bz;
always @ (address or data or cs or we)
begin : MEM_WRITE
end
end
always @ (address or cs or we or oe)
begin : MEM_READ
end
end
endmodule // End of Module ram_sp_ar_aw
Dual Port RAM Synchronous Read/Write
1 //---------------------------------------------------2 // Design Name : ram_dp_sr_sw

3 // File Name
: ram_dp_sr_sw.v
4 // Function
: Synchronous read write RAM
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------
-7 module ram_dp_sr_sw (
8 clk
, // Clock Input
9 address_0 , // address_0 Input
10 data_0
, // data_0 bi-directional
11 cs_0
, // Chip Select
12 we_0
13 oe_0
, // Output Enable
15 data_1
16 cs_1
, // Chip Select
17 we_1
18 oe_1
// Output Enable
19 );
20
21 parameter data_0_WIDTH = 8 ;
24
25 //--------------Input Ports----------------------26 input [ADDR_WIDTH-1:0] address_0 ;
27 input cs_0 ;
28 input we_0 ;
29 input oe_0 ;
30 input [ADDR_WIDTH-1:0] address_1 ;
31 input cs_1 ;
32 input we_1 ;
33 input oe_1 ;
34
35 //--------------Inout Ports----------------------36 inout [data_0_WIDTH-1:0] data_0 ;
37 inout [data_0_WIDTH-1:0] data_1 ;
38
39 //--------------Internal variables---------------40 reg [data_0_WIDTH-1:0] data_0_out ;
41 reg [data_0_WIDTH-1:0] data_1_out ;
42 reg [data_0_WIDTH-1:0] mem [0:RAM_DEPTH-1];
43
44 //--------------Code Starts Here-----------------45 // Memory Write Block
46 // Write Operation : When we_0 = 1, cs_0 = 1
47 always @ (posedge clk)
48 begin : MEM_WRITE
49
if ( cs_0 && we_0 ) begin
50
mem[address_0] <= data_0;
51
end else if (cs_1 && we_1) begin
52
53
end
54 end
55
56
57
59 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
60 assign data_0 = (cs_0 && oe_0 &&
! we_0) ?
data_0_out : 8'bz;
61
62 // Memory Read Block

63 // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 =
1
65 begin : MEM_READ_0
66
if (cs_0 && ! we_0 && oe_0) begin
67
data_0_out <= mem[address_0];
68
end else begin
69
data_0_out <= 0;
70
end
71 end
72
73 //Second Port of RAM
! we_1) ?
data_1_out : 8'bz;
77 // Memory Read Block 1
1
81
if (cs_1 && ! we_1 && oe_1) begin
82
83
end else begin
84
data_1_out <= 0;
85
end
86 end
87
88 endmodule // End of Module ram_dp_sr_sw
Dual Port RAM Asynchronous Read/Write
1 //---------------------------------------------------2 // Design Name : ram_dp_ar_aw

3 // File Name
: ram_dp_ar_aw.v
4 // Function
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module ram_dp_ar_aw (
9 data_0
10 cs_0
, // Chip Select
11 we_0
12 oe_0
, // Output Enable
14 data_1
15 cs_1
, // Chip Select
16 we_1
17 oe_1
// Output Enable
18 );
19
23
24 //--------------Input Ports----------------------25 input [ADDR_WIDTH-1:0] address_0 ;
26 input cs_0 ;
27 input we_0 ;
28 input oe_0 ;
29 input [ADDR_WIDTH-1:0] address_1 ;
30 input cs_1 ;
31 input we_1 ;
32 input oe_1 ;
33
34 //--------------Inout Ports----------------------35 inout [DATA_WIDTH-1:0] data_0 ;
36 inout [DATA_WIDTH-1:0] data_1 ;
37
38 //--------------Internal variables---------------39 reg [DATA_WIDTH-1:0] data_0_out ;
40 reg [DATA_WIDTH-1:0] data_1_out ;
41 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
42
43 //--------------Code Starts Here-----------------44 // Memory Write Block
45 // Write Operation : When we_0 = 1, cs_0 = 1
46 always @ (address_0 or cs_0 or we_0 or data_0
47 or address_1 or cs_1 or we_1 or data_1)
48 begin : MEM_WRITE
49
if ( cs_0 && we_0 ) begin
50
51
end else if (cs_1 && we_1) begin
52
53
end
54 end
55
! we_0) ?
data_0_out : 8'bz;
59
60 // Memory Read Block
1
62 always @ (address_0 or cs_0 or we_1 or oe_0)
64
if (cs_0 && ! we_0 && oe_0) begin
65
66
end else begin
67
data_0_out <= 0;
68
end
69 end
70
71 //Second Port of RAM
! we_1) ?
data_1_out : 8'bz;
75 // Memory Read Block 1
1
77 always @ (address_1 or cs_1 or we_1 or oe_1)
79
if (cs_1 && ! we_1 && oe_1) begin
80
81
end else begin
82
data_1_out <= 0;
83
end
84 end
85
86 endmodule // End of Module ram_dp_ar_aw
ROM/EPROM - Loading from File
1 //---------------------------------------------------2 // Design Name : rom_using_file

3 // File Name
: rom_using_file.v
4 // Function
: ROM using readmemh
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module rom_using_file (
8 address , // Address input
9 data
, // Data output
10 read_en , // Read Enable
11 ce
// Chip Enable
12 );
13 input [7:0] address;
14 output [7:0] data;
15 input read_en;
16 input ce;
17
18 reg [7:0] mem [0:255] ;
19
20 assign data = (ce && read_en) ? mem[address] : 8'b0;
21
22 initial begin
23
$readmemb("memory.list", mem); // memory_list is
memory file
24 end
25
26 endmodule
You could download file rom_using_file.v here
You can find the rom model and testbench here and memory_list file
here.
rom_using_case
1 //---------------------------------------------------2 // Design Name : rom_using_case

3 // File Name
: rom_using_case.v
4 // Function
: ROM using case
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module rom_using_case (
8 address , // Address input
9 data
, // Data output
10 read_en , // Read Enable
11 ce
// Chip Enable
12 );
13 input [3:0] address;
14 output [7:0] data;
15 input read_en;
16 input ce;
17
18 reg [7:0] data ;
19
20 always @ (ce or read_en or address)
21 begin
22
case (address)
23
0 : data = 10;
24
1 : data = 55;
25
2 : data = 244;
26
3 : data = 0;
27
4 : data = 1;
28
5 : data = 8'hff;
29
6 : data = 8'h11;
30
7 : data = 8'h1;
31
8 : data = 8'h10;
32
9 : data = 8'h0;
33
10 : data = 8'h10;
34
11 : data = 8'h15;
35
12 : data = 8'h60;
36
13 : data = 8'h90;
37
14 : data = 8'h70;
38
15 : data = 8'h90;
39
endcase
40 end
41
42 endmodule
Synchronous FIFO
1 //---------------------------------------------------2 // Design Name : syn_fifo

3 // File Name
: syn_fifo.v
4 // Function
: Synchronous (single clock) FIFO
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module syn_fifo (
8 clk
, // Clock input
9 rst
, // Active high reset
10 wr_cs
, // Write chip select
11 rd_cs
, // Read chipe select
12 data_in , // Data input
13 rd_en
, // Read enable
14 wr_en
, // Write Enable
15 data_out , // Data Output
16 empty
, // FIFO empty
17 full
// FIFO full
18 );
19
20 // FIFO constants
21 parameter DATA_WIDTH = 8;
22 parameter ADDR_WIDTH = 8;
23 parameter RAM_DEPTH = (1 << ADDR_WIDTH);
24 // Port Declarations
25 input clk ;
26 input rst ;
27 input wr_cs ;
28 input rd_cs ;
29 input rd_en ;
30 input wr_en ;
31 input [DATA_WIDTH-1:0] data_in ;
32 output full ;
33 output empty ;
34 output [DATA_WIDTH-1:0] data_out ;
35
36 //-----------Internal variables------------------37 reg [ADDR_WIDTH-1:0] wr_pointer;
38 reg [ADDR_WIDTH-1:0] rd_pointer;
39 reg [ADDR_WIDTH :0] status_cnt;
40 reg [DATA_WIDTH-1:0] data_out ;
41 wire [DATA_WIDTH-1:0] data_ram ;
42
43 //-----------Variable assignments--------------44 assign full = (status_cnt == (RAM_DEPTH-1));
45 assign empty = (status_cnt == 0);
46
47 //-----------Code Start--------------------------48 always @ (posedge clk or posedge rst)
49 begin : WRITE_POINTER
50
if (rst) begin
51
wr_pointer <= 0;
52
end else if (wr_cs && wr_en ) begin
53
wr_pointer <= wr_pointer + 1;
54
end
55 end
56
57 always @ (posedge clk or posedge rst)
58 begin : READ_POINTER
59
if (rst) begin
60
rd_pointer <= 0;
61
end else if (rd_cs && rd_en ) begin
62
rd_pointer <= rd_pointer + 1;
63
end
64 end
65
67 begin : READ_DATA
68
if (rst) begin
69
data_out <= 0;
70
end else if (rd_cs && rd_en ) begin
71
data_out <= data_ram;
72
end
73 end
74
76 begin : STATUS_COUNTER
77
if (rst) begin
78
status_cnt <= 0;
79
// Read but no write.
80
end else if ((rd_cs && rd_en) &&
! (wr_cs &&
wr_en)
81
&& (status_cnt ! = 0)) begin
82
status_cnt <= status_cnt - 1;
83
// Write but no read.
84
end else if ((wr_cs && wr_en) &&
! (rd_cs &&
rd_en)
85
&& (status_cnt ! = RAM_DEPTH)) begin
86
status_cnt <= status_cnt + 1;
87
end
88 end
89
90 ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
91 .address_0 (wr_pointer) , // address_0 input
92 .data_0
(data_in)
93 .cs_0
(wr_cs)
, // chip select
94 .we_0
(wr_en)
, // write enable
95 .oe_0
(1'b0)
, // output enable
96 .address_1 (rd_pointer) , // address_q input
97 .data_1
(data_ram)
98 .cs_1
(rd_cs)
, // chip select
99 .we_1
(1'b0)
, // Read enable
100 .oe_1
(rd_en)
// output enable
101 );
102
103 endmodule
Asynchronous FIFO
Note: This code is written in Verilog 2001.
1
//==========================================
2 // Function : Asynchronous FIFO (w/ 2
asynchronous clocks).
3 // Coder
: Alex Claros F.
4 // Date
: 15/May/2005.
5 // Notes
: This implementation is based
on the article
6 //
'Asynchronous FIFO in
Virtex-II FPGAs'
7 //
writen by Peter Alfke. This
TechXclusive
8 //
article can be downloaded
from the
9 //
Xilinx website. It has some
minor modifications.
10
//=========================================
11
12 `timescale 1ns/1ps
13
14 module aFifo
15
#(parameter
DATA_WIDTH
= 8,
16
ADDRESS_WIDTH = 4,
17
FIFO_DEPTH
= (1 <<
ADDRESS_WIDTH))
18
//Reading port
19
(output reg
[DATA_WIDTH-1:0]
Data_out,
20
output
reg
Empty_out,
21
input
wire
ReadEn_in,
22
input
wire
RClk,
23
//Writing port.
24
input wire
[DATA_WIDTH-1:0]
Data_in,
25
output
reg
Full_out,
26
input
wire
WriteEn_in,
27
input
wire
WClk,
28
29
input
wire
Clear_in);
30
31
//
32
reg
[DATA_WIDTH-1:0]
Mem [FIFO_DEPTH-1:0];
33
wire
[ADDRESS_WIDTH-1:0]
pNextWordToWrite, pNextWordToRead;
34
wire
EqualAddresses;
35
wire
NextWriteAddressEn, NextReadAddressEn;
36
wire
Set_Status, Rst_Status;
37
reg
Status;
38
wire
PresetFull, PresetEmpty;
39
40
// 41
//Data ports logic:
42
//(Uses a dual-port RAM).
43
//'Data_out' logic:
44
always @ (posedge RClk)
45
if (ReadEn_in & ! Empty_out)
46
Data_out <=
Mem[pNextWordToRead];
47
48
//'Data_in' logic:
49
always @ (posedge WClk)
50
if (WriteEn_in & ! Full_out)
51
Mem[pNextWordToWrite] <=
Data_in;
52
53
//Fifo addresses support logic:
54
//'Next Addresses' enable logic:
55
assign NextWriteAddressEn =
WriteEn_in & ~Full_out;
56
assign NextReadAddressEn = ReadEn_in
& ~Empty_out;
57
58
//Addreses (Gray counters) logic:
59
GrayCounter GrayCounter_pWr
60
(.GrayCount_out(pNextWordToWrite),
61
62
.Enable_in(NextWriteAddressEn),
63
.Clear_in(Clear_in),
64
65
.Clk(WClk)
66
);
67
68
GrayCounter GrayCounter_pRd
69
(.GrayCount_out(pNextWordToRead),
70
.Enable_in(NextReadAddressEn),
71
.Clear_in(Clear_in),
72
.Clk(RClk)
73
);
74
75
76
//'EqualAddresses' logic:
77
assign
EqualAddresses
=
(pNextWordToWrite == pNextWordToRead);
78
79
//'Quadrant selectors' logic:
80
assign
Set_Status
=
(pNextWordToWrite[ADDRESS_WIDTH-2]
~^
pNextWordToRead[ADDRESS_WIDTH-1]) &
81
^
pNextWordToRead[ADDRESS_WIDTH-2]);
82
83
assign
Rst_Status
=
^
pNextWordToRead[ADDRESS_WIDTH-1]) &
84
~^
pNextWordToRead[ADDRESS_WIDTH-2]);
85
86
//'Status' latch logic:
87
always @ (Set_Status, Rst_Status,
Clear_in) //D Latch w/ Asynchronous Clear &
Preset.
88
if (Rst_Status | Clear_in)
89
Status = 0; //Going 'Empty'.
90
else if (Set_Status)
91
Status = 1; //Going 'Full'.
92
93
//'Full_out' logic for the writing
port:
94
assign PresetFull = Status &
EqualAddresses; //'Full' Fifo.
95
96
always @ (posedge WClk, posedge
PresetFull) //D Flip-Flop w/ Asynchronous
Preset.
97
if (PresetFull)
98
Full_out <= 1;
99
else
100
Full_out <= 0;
101
102
//'Empty_out' logic for the reading
port:
103
assign PresetEmpty = ~Status &
EqualAddresses; //'Empty' Fifo.
104
105
always @ (posedge RClk, posedge
PresetEmpty) //D Flip-Flop w/ Asynchronous
Preset.
106
if (PresetEmpty)
107
Empty_out <= 1;
108
else
109
Empty_out <= 0;
110
111 endmodule
Content Addressable Memory (CAM)
1 //---------------------------------------------------2 // Design Name : cam

3 // File Name
: cam.v
4 // Function
: CAM
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module cam (
8 clk
, // Cam clock
9 cam_enable , // Cam enable
10 cam_data_in , // Cam data to match
11 cam_hit_out , // Cam match has happened
12 cam_addr_out // Cam output address
13 );
14
15 parameter ADDR_WIDTH = 8;
16 parameter DEPTH
= 1 << ADDR_WIDTH;
17 //------------Input Ports-------------18 input
clk;
19 input
cam_enable;
20 input [DEPTH-1:0]
cam_data_in;
21 //----------Output Ports-------------22 output
cam_hit_out;
23 output [ADDR_WIDTH-1:0] cam_addr_out;
24 //------------Internal Variables-------25 reg [ADDR_WIDTH-1:0] cam_addr_out;
26 reg
cam_hit_out;
27 reg [ADDR_WIDTH-1:0] cam_addr_combo;
28 reg
cam_hit_combo;
29 reg
found_match;
30 integer
i;
31 //-------------Code Starts Here------32 always @(cam_data_in) begin
33
cam_addr_combo
= {ADDR_WIDTH{1'b0}};
34
found_match
= 1'b0;
35
cam_hit_combo
= 1'b0;
36
for (i=0; i<DEPTH; i=i+1) begin
37
if (cam_data_in[i] && ! found_match) begin
38
found_match
= 1'b1;
39
cam_hit_combo
= 1'b1;
40
cam_addr_combo = i;
41
end else begin
42
found_match
= found_match;
43
cam_hit_combo
= cam_hit_combo;
44
cam_addr_combo = cam_addr_combo;
45
end
46
end
47 end
PARITY
48
49
50
51
52
53
54
55
56
57
58
59
60
// Register the outputs

always @(posedge clk) begin
if (cam_enable) begin
cam_hit_out <= cam_hit_combo;
cam_addr_out <= cam_addr_combo;
end else begin
cam_hit_out <= 1'b0;
cam_addr_out <= {ADDR_WIDTH{1'b0}};
end
end
endmodule
Using Assign
1 //---------------------------------------------------2 // Design Name : parity_using_assign

3 // File Name
: parity_using_assign.v
4 // Function
: Parity using assign
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module parity_using_assign (
8 data_in
, // 8 bit data in
9 parity_out
// 1 bit parity out
10 );
11 output parity_out ;
12 input [7:0] data_in ;
13
14 wire parity_out ;
15
16 assign parity_out = (data_in[0] ^ data_in[1]) ^
17
(data_in[2] ^ data_in[3]) ^
18
19
(data_in[6] ^ data_in[7]);
20
21 endmodule
You could download file parity_using_assign.v here
Using function- I
1 //---------------------------------------------------2 // Design Name : parity_using_function

3 // File Name
: parity_using_function.v
4 // Function
: Parity using function
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module parity_using_function (
8 data_in
, // 8 bit data in
9 parity_out
// 1 bit parity out
10 );
13
15
16 function parity;
17
input [31:0] data;
18
begin
19
parity = (data_in[0] ^ data_in[1]) ^
20
21
22
(data_in[6] ^ data_in[7]);
23
end
24 endfunction
25
26
27 assign parity_out = parity(data_in);
28
29 endmodule
You could download file parity_using_function.v here
Using function- II
1 //---------------------------------------------------2 // Design Name : parity_using_function2

3 // File Name
: parity_using_function2.v
4 // Function
: Parity using function
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module parity_using_function2 (
8 data_in
, // 8 bit data in
9 parity_out
// 1 bit parity out
10 );
13
15 function parity;
16
input [31:0] data;
17
integer i;
18
begin
19
parity = 0;
20
for (i = 0; i < 32; i = i + 1) begin
21
parity = parity ^ data[i];
22
end
23
end
24 endfunction
25
26 always @ (data_in)
27 begin
28
parity_out = parity(data_in);
29 end
30
31 endmodule
You could download file parity_using_function2.v here
And the Practical One
1 //---------------------------------------------------2 // Design Name : parity_using_bitwise

3 // File Name
: parity_using_bitwise.v
4 // Function
: Parity using bitwise xor
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module parity_using_bitwise (
8 data_in
, // 8 bit data in
9 parity_out
// 1 bit parity out
10 );
13
14 assign parity_out = ^data_in;
15
16 endmodule
SERIAL CRC
Below code is 16-bit CRC-CCITT implementation, with following features
Width = 16 bits
Truncated polynomial =
0x1021
Initial value = 0xFFFF
Input data
reflected
Output CRC is NOT

reflected
No XOR is performed
on the output CRC
1 //----------------------------------------------------2 // Design Name : serial_crc_ccitt

3 // File Name
: serial_crc.v
4 // Function
: CCITT Serial CRC
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module serial_crc_ccitt (
8 clk
,
9 reset
,
10 enable ,
11 init
,
12 data_in ,
13 crc_out
14 );
15 //-----------Input Ports--------------16 input clk
;
17 input reset
;
18 input enable ;
19 input init
;
20 input data_in ;
21 //-----------Output Ports--------------22 output [15:0] crc_out;
23 //------------Internal Variables-------24 reg
[15:0] lfsr;
25 //-------------Code Start----------------26 assign crc_out = lfsr;
27 // Logic to CRC Calculation
is
NOT
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
if (reset) begin
lfsr <= 16'hFFFF;
end else if (enable) begin
if (init) begin
lfsr <= 16'hFFFF;
end else begin
lfsr[0] <= data_in ^ lfsr[15];
lfsr[1] <= lfsr[0];
lfsr[2] <= lfsr[1];
lfsr[3] <= lfsr[2];
lfsr[4] <= lfsr[3];
lfsr[5] <= lfsr[4] ^ data_in ^ lfsr[15];
lfsr[6] <= lfsr[5];
lfsr[7] <= lfsr[6];
lfsr[8] <= lfsr[7];
lfsr[9] <= lfsr[8];
lfsr[10] <= lfsr[9];
lfsr[11] <= lfsr[10];
lfsr[12] <= lfsr[11] ^ data_in ^ lfsr[15];
lfsr[13] <= lfsr[12];
lfsr[14] <= lfsr[13];
lfsr[15] <= lfsr[14];
end
end
endmodule
Parallel CRC
Below code is 16-bit CRCCCITT implementation, with
following features
Width = 16 bits
Truncated polynomial =
0x1021
Initial value = 0xFFFF
Input data
reflected
Output CRC is NOT

reflected
is
NOT
No XOR is performed
on the output CRC
//----------------------------------------------------2 // Design Name : parallel_crc_ccitt

3 // File Name
: parallel_crc.v
4 // Function
: CCITT Parallel CRC
5 // Coder
: Deepak Kumar Tala
6 //----------------------------------------------------7 module parallel_crc_ccitt (
8 clk
,
9 reset
,
10 enable ,
11 init
,
12 data_in ,
13 crc_out
14 );
15 //-----------Input Ports--------------16 input clk
;
17 input reset
;
18 input enable ;
19 input init
;
21 //-----------Output Ports--------------22 output [15:0] crc_out;
23 //------------Internal Variables-------24 reg [15:0]
crc_reg;
25 wire [15:0] next_crc;
26 //-------------Code Start----------------27 assign crc_out = crc_reg;
28 // CRC Control logic
30 if (reset) begin
31
crc_reg <= 16'hFFFF;
33
if (init) begin
34
crc_reg <= 16'hFFFF;
35
end else begin
36
crc_reg <= next_crc;
37
end
38 end
39 // Parallel CRC calculation
40 assign next_crc[0] = data_in[7] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[11];
41 assign next_crc[1] = data_in[1] ^ crc_reg[5];
45 assign next_crc[5] = data_in[7] ^ data_in[5] ^ data_in[0] ^ crc_reg[4] ^
crc_reg[9] ^ crc_reg[11];
48 assign next_crc[8] = data_in[3] ^ crc_reg[0] ^ crc_reg[7];
52
53 endmodule
Not Gate
1 //---------------------------------------------------2 // Design Name : not_switch

3 // File Name
: not_switch.v
4 // Function
: NOT Gate Using Switch Primitives
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module not_switch (out, in);
8
output out;
9
input
in;
10
11
supply1 power;
12
supply0 ground;
13
14
pmos (out, power, in);
15
nmos (out, ground, in);
16
17 endmodule
You could download file not_switch.v here
Two Input XOR
1 module nor2_switch (a,b,y);

2 input a, b;
3 output y;
4
5 supply1 power;
6 supply0 ground;
7
8 wire connect;
9
10 nmos (y,ground,a);
11 nmos (y,ground,b);
12 pmos (y,connect,b);
13 pmos (power,connect,a);
14
15 endmodule
You could download file xor_switch.v here
Two Input NAND
1 module nand_switch(a,b,out);
2 input a,b;
3 output out;
4
5 supply0 vss;
6 supply1 vdd;
7 wire net1;
8
9 pmos p1 (vdd,out,a);
10 pmos p2 (vdd,out,b);
11 nmos n1 (vss,net1,a);
12 nmos n2 (net1,out,b);
13
14 endmodule
2:1 Mux
1 //---------------------------------------------------2 // Design Name : mux21_switch

3 // File Name
: mux21_switch.v
4 // Function
: 2:1 Mux using Switch Primitives
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module mux21_switch (out, ctrl, in1, in2);
8
9
output out;
10
input ctrl, in1, in2;
11
wire
w;
12
13
supply1 power;
14
supply0 ground;
15
16
pmos N1 (w, power, ctrl);
17
nmos N2 (w, ground, ctrl);
18
19
cmos C1 (out, in1, w, ctrl);
20
cmos C2 (out, in2, ctrl, w);
21
22 endmodule
D Latch
Transimission Gate
1 module not_switch (out,

in);
2
output out;
3
input
in;
4
5
supply1 power;
6
supply0 ground;
7
8
pmos (out, power,
in);
9
nmos (out, ground,
in);
10
11 endmodule
12
13
module
d_latch_switch(clk,d,q);
14 input clk,d;
15 output q;
16
17 wire clkn, net1, qn;
18
19
not_switch
i1
(clkn,clk);
20
21 pmos p1 (d,q,clkn);
22 nmos n1 (d,q,clk);
23
24 pmos p2 (q,net1,clk);
25 nmos n2 (q,net1,clkn);
26
27 not_switch i2 (qn,q);
28
not_switch
i3
(net1,qn);
29
30 endmodule
1
module
t_gate_switch
(L,R,nC,C);
2 inout L;
3 inout R;
4 input nC;
5 input C;
6
7
//Syntax:
keyword
unique_name
(drain.
source, gate);
8 pmos p1 (L,R,nC);
9 nmos p2 (L,R,C);
10
11 endmodule
You could download

t_gate_switch.v here
file
!((a+b+c).d)
1
module
misc1
(a,b,c,d,y);
2 input a, b,c,d;
3 output y;
4
5 wire net1,net2,net3;
6
7 supply1 vdd;
8 supply0 vss;
9
10 // y = !((a+b+c).d)
11
12 pmos p1 (vdd,net1,a);
13 pmos p2 (net1,net2,b);
14 pmos p3 (net2,y,c);
15 pmos p4 (vdd,y,d);
16
17 nmos n1 (vss,net3,a);
18 nmos n2 (vss,net3,b);
19 nmos n3 (vss,net3,c);
20 nmos n4 (net3,y,d);
21
22 endmodule
Half Adder
1 //---------------------------------------------------2 // Design Name : half_adder_gates

3 // File Name
: half_adder_gates.v
4 // Function
: CCITT Serial CRC
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module half_adder_gates(x,y,sum,carry);
8 input x,y;
9 output sum,carry;
10
11 and U_carry (carry,x,y);
12 xor U_sum (sum,x,y);
13
14 endmodule
You could download file half_adder_gates.v here
Full Adder
1 //---------------------------------------------------2 // Design Name : full_adder_gates

3 // File Name
: full_adder_gates.v
4 // Function
: Full Adder Using Gates
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module full_adder_gates(x,y,z,sum,carry);
8 input x,y,z;
9 output sum,carry;
10 wire and1,and2,and3,sum1;
11
12 and U_and1 (and1,x,y),
13
U_and2 (and2,x,z),
14
U_and3 (and3,y,z);
15 or U_or
(carry,and1,and2,and3);
16 xor U_sum (sum,x,y,z);
17
18 endmodule
Full Subtracter
1 //---------------------------------------------------2 // Design Name : full_subtracter_gates

3 // File Name
: full_subtracter_gates.v
4 // Function
: Full Subtracter Using Gates
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7
module
full_subtracter_gates(x,y,z,difference,borrow);
8 input x,y,z;
9 output difference,borrow;
10
11 wire inv_x,borrow1,borrow2,borrow3;
12
2:1 Mux
13
14
15
16
17
18
19
20
not (inv_x,x);
and U_borrow1 (borrow1,inv_x,y),
U_borrow2 (borrow2,inv_x,z),
U_borrow3 (borrow3,y,z);
xor U_diff (difference,borrow1,borrow2,borrows);
endmodule
1 //---------------------------------------------------2 // Design Name : mux_2to1_gates

3 // File Name
: mux_2to1_gates.v
4 // Function
: 2:1 Mux using Gate Primitives
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module mux_2to1_gates(a,b,sel,y);
8 input a,b,sel;
9 output y;
10
11 wire sel,a_sel,b_sel;
12
13 not U_inv (inv_sel,sel);
14 and U_anda (asel,a,inv_sel),
15
U_andb (bsel,b,sel);
16 or U_or (y,asel,bsel);
17
18 endmodule
You could download file mux_2to1_gates.v here
4:1 Mux
1 //---------------------------------------------------2 // Design Name : mux_4to1_gates

3 // File Name
: mux_4to1_gates.v
4 // Function
: 4:1 Mux Using Gates
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module mux_4to1_gates(a,b,c,d,sel,y);
8 input a,b,c,d;
9 input [1:0] sel;
10 output y;
11
12 wire mux_1,mux_2;
13
14 mux_2to1_gates U_mux1 (a,b,sel[0],mux_1),
15
U_mux2 (c,d,sel[0],mux_2),
16
U_mux3 (mux_1,mux_2,sel[1],y);
17
18 endmodule
2 To 4 Decoder
Two Input OR
1
module
decoder_2to4_gates
(x,y,f0,f1,f2,f3);
2 input x,y;
3 output f0,f1,f2,f3;
4
5 wire n1,n2;
6
7 not i1 (n1,x);
8 not i2 (n2,y);
9 and a1 (f0,n1,n2);
10 and a2 (f1,n1,y);
11 and a3 (f2,x,n2);
12 and a4 (f3,x,y);
13
14 endmodule
1 //---------------------------------------------------2 // Design Name : or2_input

3 // File Name
: or2_input.v
4 // Function
: 2 Input OR Gate Using UDP
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 primitive or2_input (c,a,b);
8
output c;
9
input a,b;
10
table
11
//a b : c
12
1 ? : 1;
13
? 1 : 1;
14
0 0 : 0;
15
0 x : x;
16
x 0 : x;
17
endtable
18 endprimitive
You could download file or2_input.v here
Two Input XOR
1 primitive xor2_input (c,a,b);

2
output c;
3
input a,b;
4
table
5
0 0 : 0;
6
0 1 : 1;
7
1 0 : 1;
8
1 1 : 0;
9
x 1 : x;
10
1 x : x;
11
x 0 : x;
12
0 x : x;
13
x x : x;
14
endtable
15 endprimitive
2:1 Mux
1
primitive
mux_21_udp(out, sel, i0,
i1);
2 output out;
3 input sel, i0, i1;
4 table
5
// sel i0 i1
out
6
0
0
?
:
0 ; // 1
7
0
1
?
:
1 ; // 2
8
1
?
0
:
0 ; // 3
9
1
?
1
:
1 ; // 4
10
?
0
0
:
0 ; // 5
11
?
1
1
:
1 ; // 6
12 endtable
13 endprimitive
equential Logic Using UDP
D Latch
1 primitive latch_udp(q, clock, data) ;

2 output q; reg q ;
3 input clock, data;
4 table
5
// clock data
q
q+
6
0
1
: ? : 1 ;
7
0
0
: ? : 0 ;
8
1
?
: ? : - ; // - = no change
9 endtable
10 endprimitive
You could download file latch_udp.v here
D Flip Flop
1 //---------------------------------------------------2 // Design Name : dff_udp

3 // File Name
: dff_udp.v
4 // Function
: D Flip Flop
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 primitive dff_udp (q,clk,d);
8
input clk,d;
9
output q;
10
reg q;
11
table
12
// clk d : q : q+
13
r 0 : ? : 0 ;
14
r 1 : ? : 1 ;
15
f ? : ? : - ;
16
? * : ? : - ;
17
endtable
18 endprimitive
You could download file dff_udp.v here
SR Flip Flop
1 primitive srff_udp (q,s,r);

2 output q;
3 input s,r;
4
5 reg q;
6
7 initial q = 1'b1;
8
9 table
10
// s r q q+
11
1 0 : ? : 1 ;
12
f 0 : 1 : - ;
13
0 r : ? : 0 ;
14
0 f : 0 : - ;
15
1 1 : ? : 0 ;
16 endtable
17
18 endprimitive
You could download file srff_udp.v here
JK Flip Flop
1 //---------------------------------------------------2 // Design Name : jkff_udp

3 // File Name
: jkff_udp.v
4 // Function
: JK Flip Flop Using UDP
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 primitive jkff_udp (q,clk,j,k);
8
input clk,j,k;
9
output q;
10
reg q;
11
table
12
// clk j k : q : q+
13
r 0 0 : ? : - ;
14
r 0 1 : ? : 0 ;
15
r 1 0 : ? : 1 ;
16
r 1 1 : 0 : 1 ;
17
r 1 1 : 1 : 0 ;
18
f ? ? : ? : - ;
19
? * ? : ? : - ;
20
? ? * : ? : - ;
21
endtable
22 endprimitive
Verilog Code
1
2
3
4
5
6
7
8
module hello_pli ();

initial begin
$hello;
#10 $finish;
end
endmodule
Verilog UART Model
1 //---------------------------------------------------2 // Design Name : uart

3 // File Name
: uart.v
4 // Function
: Simple UART
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module uart (
8 reset
,
9 txclk
,
10 ld_tx_data
,
11 tx_data
,
12 tx_enable
,
13 tx_out
,
14 tx_empty
,
15 rxclk
,
16 uld_rx_data
,
17 rx_data
,
18 rx_enable
,
19 rx_in
,
20 rx_empty
21 );
22 // Port declarations
23 input
reset
;
24 input
txclk
;
25 input
ld_tx_data
;
26 input [7:0] tx_data
;
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
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57
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65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
input
tx_enable
output
tx_out
output
tx_empty
input
rxclk
input
uld_rx_data
output [7:0] rx_data
input
rx_enable
input
rx_in
output
rx_empty
;
;
;
;
;
;
;
;
;
// Internal Variables
reg [7:0]
tx_reg
reg
tx_empty
reg
tx_over_run
reg [3:0]
tx_cnt
reg
tx_out
reg [7:0]
rx_reg
reg [7:0]
rx_data
reg [3:0]
rx_sample_cnt
reg [3:0]
rx_cnt
reg
rx_frame_err
reg
rx_over_run
reg
rx_empty
reg
rx_d1
reg
rx_d2
reg
rx_busy
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
// UART RX Logic
always @ (posedge rxclk or posedge reset)
if (reset) begin
rx_reg
<= 0;
rx_data
<= 0;
rx_sample_cnt <= 0;
rx_cnt
<= 0;
rx_frame_err <= 0;
rx_over_run
<= 0;
rx_empty
<= 1;
rx_d1
<= 1;
rx_d2
<= 1;
rx_busy
<= 0;
end else begin
// Synchronize the asynch signal
rx_d1 <= rx_in;
rx_d2 <= rx_d1;
// Uload the rx data
if (uld_rx_data) begin
rx_data <= rx_reg;
rx_empty <= 1;
end
// Receive data only when rx is enabled
if (rx_enable) begin
// Check if just received start of frame
if ( ! rx_busy && ! rx_d2) begin
rx_busy
<= 1;
rx_sample_cnt <= 1;
rx_cnt
<= 0;
end
84
// Start of frame detected, Proceed with rest of
data
85
if (rx_busy) begin
86
rx_sample_cnt <= rx_sample_cnt + 1;
87
// Logic to sample at middle of data
88
if (rx_sample_cnt == 7) begin
89
if ((rx_d2 == 1) && (rx_cnt == 0)) begin
90
rx_busy <= 0;
91
end else begin
92
rx_cnt <= rx_cnt + 1;
93
// Start storing the rx data
94
if (rx_cnt > 0 && rx_cnt < 9) begin
95
rx_reg[rx_cnt - 1] <= rx_d2;
96
end
97
if (rx_cnt == 9) begin
98
rx_busy <= 0;
99
// Check if End of frame received
correctly
100
if (rx_d2 == 0) begin
101
rx_frame_err <= 1;
102
end else begin
103
rx_empty
<= 0;
104
rx_frame_err <= 0;
105
// Check if last rx data was not
unloaded,
106
rx_over_run <= (rx_empty) ? 0 :
1;
107
end
108
end
109
end
110
end
111
end
112
end
113
if ( ! rx_enable) begin
114
rx_busy <= 0;
115
end
116 end
117
118 // UART TX Logic
119 always @ (posedge txclk or posedge reset)
120 if (reset) begin
121
tx_reg
<= 0;
122
tx_empty
<= 1;
123
tx_over_run
<= 0;
124
tx_out
<= 1;
125
tx_cnt
<= 0;
126 end else begin
127
if (ld_tx_data) begin
128
if ( ! tx_empty) begin
129
tx_over_run <= 0;
130
end else begin
131
tx_reg
<= tx_data;
132
tx_empty <= 0;
133
end
134
end
135
if (tx_enable && ! tx_empty) begin
136
tx_cnt <= tx_cnt + 1;
137
if (tx_cnt == 0) begin
138
tx_out <= 0;
139
end
140
if (tx_cnt > 0 && tx_cnt < 9) begin
141
tx_out <= tx_reg[tx_cnt -1];
142
end
143
if (tx_cnt == 9) begin
144
tx_out <= 1;
145
tx_cnt <= 0;
146
tx_empty <= 1;
147
end
148
end
149
if ( ! tx_enable) begin
150
tx_cnt <= 0;
151
end
152 end
153
154 endmodule
Verilog Round Robin Arbiter Model
1 //--------------------------------------------------2 // A four level, round-robin arbiter. This was

3 // orginally coded by WD Peterson in VHDL.
4 //--------------------------------------------------5 module arbiter (
6
clk,
7
rst,
8
req3,
9
req2,
10
req1,
11
req0,
12
gnt3,
13
gnt2,
14
gnt1,
15
gnt0
16 );
17
//
--------------Port
clk;
19 input
rst;
20 input
req3;
21 input
req2;
22 input
req1;
23 input
req0;
24 output
gnt3;
25 output
gnt2;
26 output
gnt1;
27 output
gnt0;
28
29
//--------------Internal
Registers----------------------
30 wire
[1:0]
gnt
;
31 wire
comreq
;
32 wire
beg
;
33 wire
[1:0]
lgnt
;
34 wire
lcomreq
;
35 reg
lgnt0
;
36 reg
lgnt1
;
37 reg
lgnt2
;
38 reg
lgnt3
;
39 reg
lasmask
;
40 reg
lmask0
;
41 reg
lmask1
;
42 reg
ledge
;
43
44
//--------------Code
Starts
Here----------------------45 always @ (posedge clk)
46 if (rst) begin
47
lgnt0 <= 0;
48
lgnt1 <= 0;
49
lgnt2 <= 0;
50
lgnt3 <= 0;
51 end else begin
52
lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 &
~req2 & ~req1 & req0)
53
| (~lcomreq & ~lmask1 & lmask0 & ~req3 &
~req2 & req0)
54
| (~lcomreq & lmask1 & ~lmask0 & ~req3 &
req0)
55
| (~lcomreq & lmask1 & lmask0 & req0 )
56
| ( lcomreq & lgnt0 );
57
lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
58
| (~lcomreq & ~lmask1 & lmask0 & ~req3 &
~req2 & req1 & ~req0)
59
req1 & ~req0)
60
| (~lcomreq & lmask1 & lmask0 & req1 &
~req0)
61
| ( lcomreq & lgnt1);
62
lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 &
~req1)
63
| (~lcomreq & ~lmask1 & lmask0 & req2)
64
req2 & ~req1 & ~req0)
65
~req1 & ~req0)
66
67
lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 &
~req2 & ~req1)
68
| (~lcomreq & ~lmask1 & lmask0 & req3 &
~req2)
69
| (~lcomreq & lmask1 & ~lmask0 & req3)
70
~req2 & ~req1 & ~req0)
71
72 end
73
74 //--------------------------------------------------75 // lasmask state machine.

76 //--------------------------------------------------77 assign beg = (req3 | req2 | req1 | req0) &
~lcomreq;
79 begin
80
lasmask <= (beg & ~ledge & ~lasmask);
81
ledge
<= (beg & ~ledge & lasmask)
82
| (beg & ledge & ~lasmask);
83 end
84
85 //--------------------------------------------------86 // comreq logic.
87 //--------------------------------------------------88 assign lcomreq = ( req3 & lgnt3 )
89
| ( req2 & lgnt2 )
90
| ( req1 & lgnt1 )
91
| ( req0 & lgnt0 );
92
93 //--------------------------------------------------94 // Encoder logic.
95 //--------------------------------------------------96 assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
97
98 //--------------------------------------------------99 // lmask register.
100 //--------------------------------------------------101 always @ (posedge clk )
102 if( rst ) begin
103
lmask1 <= 0;
104
lmask0 <= 0;
105 end else if(lasmask) begin
106
lmask1 <= lgnt[1];
107
lmask0 <= lgnt[0];
108 end else begin
109
lmask1 <= lmask1;
110
lmask0 <= lmask0;
111 end
112
113 assign comreq = lcomreq;
114 assign gnt
= lgnt;
115 //--------------------------------------------------116 // Drive the outputs
117 //--------------------------------------------------118 assign gnt3
= lgnt3;
119 assign gnt2
= lgnt2;
120 assign gnt1

121 assign gnt0
122
123 endmodule
= lgnt1;
= lgnt0;
You could download file arbiter.v here
Testbench Code
1 `include "arbiter.v"
2 module top ();
3
4 reg
clk;
5 reg
rst;
6 reg
req3;
7 reg
req2;
8 reg
req1;
9 reg
req0;
10 wire
gnt3;
11 wire
gnt2;
12 wire
gnt1;
13 wire
gnt0;
14
15 // Clock generator
16 always #1 clk = ~clk;
17
18 initial begin
19
$dumpfile ("arbiter.vcd");
20
$dumpvars();
21
clk = 0;
22
rst = 1;
23
req0 = 0;
24
req1 = 0;
25
req2 = 0;
26
req3 = 0;
27
#10 rst = 0;
28
repeat (1) @ (posedge clk);
29
req0 <= 1;
30
31
req0 <= 0;
32
33
req0 <= 1;
34
req1 <= 1;
35
36
req2 <= 1;
37
req1 <= 0;
38
39
req3 <= 1;
40
req2 <= 0;
41
42
req3 <= 0;
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

req0 <= 0;
#10 $finish;
end
// Connect the DUT
arbiter U (
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
);
endmodule
Pri-Encoder - Using if-else Statement
1 //---------------------------------------------------2 // Design Name : pri_encoder_using_if

3 // File Name
: pri_encoder_using_if.v
4 // Function
: Pri Encoder using If
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module pri_encoder_using_if (
8 binary_out , // 4 bit binary output
9 encoder_in , // 16-bit input
10 enable
// Enable for the encoder
11 );
12 output [3:0] binary_out ;
13 input enable ;
14 input [15:0] encoder_in ;
15
16 reg [3:0] binary_out ;
17
18 always @ (enable or encoder_in)
19 begin
20
binary_out = 0;
21
if (enable) begin
22
if (encoder_in[0] == 1) begin
23
binary_out = 1;
24
end else if (encoder_in[1] == 1) begin
25
binary_out = 2;
26
27
binary_out = 3;
28
29
binary_out
30
end else if
31
binary_out
32
end else if
33
binary_out
34
end else if
35
binary_out
36
end else if
37
binary_out
38
end else if
39
binary_out
40
end else if
41
binary_out
42
end else if
43
binary_out
44
end else if
45
binary_out
46
end else if
47
binary_out
48
end else if
49
binary_out
50
end else if
51
binary_out
52
end
53
end
54 end
55
56 endmodule
= 4;
(encoder_in[4] == 1) begin
= 5;
= 6;
= 7;
= 8;
= 9;
= 10;
= 11;
= 12;
= 13;
= 14;
= 15;
You could download file pri_encoder_using_if.v here
Encoder - Using assign Statement
1 //---------------------------------------------------2 // Design Name : pri_encoder_using_assign

3 // File Name
: pri_encoder_using_assign.v
4 // Function
: Pri Encoder using assign
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module pri_encoder_using_assign (
10 enable
11 );
12
14 input enable ;
16
17 wire [3:0] binary_out ;

18
19 assign binary_out = ( ! enable) ? 0 : (
20
(encoder_in[0]) ? 0 :
21
22
23
24
25
26
27
28
29
30
(encoder_in[10]) ? 10 :
31
(encoder_in[11]) ? 11 :
32
(encoder_in[12]) ? 12 :
33
(encoder_in[13]) ? 13 :
34
(encoder_in[14]) ? 14 : 15);
35
36 endmodule
Decoder - Using case Statement
1 //---------------------------------------------------2 // Design Name : decoder_using_case

3 // File Name
: decoder_using_case.v
4 // Function
: decoder using case
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module decoder_using_case (
8 binary_in
, // 4 bit binary input
9 decoder_out , // 16-bit out
10 enable
// Enable for the decoder
11 );
12 input [3:0] binary_in ;
13 input enable ;
14 output [15:0] decoder_out ;
15
16 reg [15:0] decoder_out ;
17
18 always @ (enable or binary_in)
19 begin
20
decoder_out = 0;
21
if (enable) begin
22
case (binary_in)
23
4'h0 : decoder_out = 16'h0001;
24
25
26
27
28
4'h5 :
29
4'h6 :
30
4'h7 :
31
4'h8 :
32
4'h9 :
33
4'hA :
34
4'hB :
35
4'hC :
36
4'hD :
37
4'hE :
38
4'hF :
39
endcase
40
end
41 end
42
43 endmodule
decoder_out
decoder_out
decoder_out
decoder_out
decoder_out
decoder_out
decoder_out
decoder_out
decoder_out
decoder_out
decoder_out
=
=
=
=
=
=
=
=
=
=
=
16'h0020;
16'h0040;
16'h0080;
16'h0100;
16'h0200;
16'h0400;
16'h0800;
16'h1000;
16'h2000;
16'h4000;
16'h8000;
You could download file decoder_using_case.v here
Decoder - Using assign Statement
1 //---------------------------------------------------2 // Design Name : decoder_using_assign

3 // File Name
: decoder_using_assign.v
4 // Function
: decoder using assign
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module decoder_using_assign (
8 binary_in
, // 4 bit binary input
9 decoder_out , // 16-bit out
10 enable
// Enable for the decoder
11 );
12 input [3:0] binary_in ;
13 input enable ;
14 output [15:0] decoder_out ;
15
16 wire [15:0] decoder_out ;
17
18 assign decoder_out = (enable) ? (1 << binary_in) :
16'b0 ;
19
20 endmodule
Mux : Using assign Statement
1 //----------------------------------------------------
2 // Design Name : mux_using_assign

3 // File Name
: mux_using_assign.v
4 // Function
: 2:1 Mux using Assign
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module mux_using_assign(
8 din_0
, // Mux first input
9 din_1
, // Mux Second input
10 sel
, // Select input
11 mux_out
// Mux output
12 );
13 //-----------Input Ports--------------14 input din_0, din_1, sel ;
15 //-----------Output Ports--------------16 output mux_out;
17 //------------Internal Variables-------18 wire mux_out;
19 //-------------Code Start----------------20 assign mux_out = (sel) ? din_1 : din_0;
21
22 endmodule //End Of Module mux
You could download file mux_using_assign.v here
Mux : Using if Statement
1 //---------------------------------------------------2 // Design Name : mux_using_if

3 // File Name
: mux_using_if.v
4 // Function
: 2:1 Mux using If
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module mux_using_if(
8 din_0
9 din_1
10 sel
, // Select input
11 mux_out
// Mux output
12 );
17 //------------Internal Variables-------18 reg mux_out;
19
20
21
22
23
24
25
26
27
28
29
//-------------Code Starts Here--------always @ (sel or din_0 or din_1)

begin : MUX
if (sel == 1'b0) begin
mux_out = din_0;
end else begin
mux_out = din_1 ;
end
end
endmodule //End Of Module mux
You could download file mux_using_if.v here
Mux : Using case Statement
1 //---------------------------------------------------2 // Design Name : mux_using_case

3 // File Name
: mux_using_case.v
4 // Function
: 2:1 Mux using Case
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module mux_using_case(
8 din_0
9 din_1
10 sel
, // Select input
11 mux_out
// Mux output
12 );
17 //------------Internal Variables-------18 reg mux_out;
19 //-------------Code Starts Here--------20 always @ (sel or din_0 or din_1)
21 begin : MUX
22 case(sel )
23
1'b0 : mux_out = din_0;
24
1'b1 : mux_out = din_1;
25 endcase
26 end
27
28 endmodule //End Of Module mux
Encoder - Using if-else Statement
1 //---------------------------------------------------2 // Design Name : encoder_using_if

3 // File Name
: encoder_using_if.v
4 // Function
: Encoder using If
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module encoder_using_if(
10 enable
11 );
12 //-----------Output Ports--------------13 output [3:0] binary_out ;
14 //-----------Input Ports--------------15 input enable ;
17 //------------Internal Variables-------18 reg [3:0] binary_out ;
19 //-------------Code Start----------------20 always @ (enable or encoder_in)
21 begin
22
binary_out = 0;
23
if (enable) begin
24
if (encoder_in == 16'h0002) begin
25
binary_out = 1;
26
end if (encoder_in == 16'h0004) begin
27
binary_out = 2;
28
29
binary_out = 3;
30
31
binary_out = 4;
32
33
binary_out = 5;
34
35
binary_out = 6;
36
37
binary_out = 7;
38
39
binary_out = 8;
40
41
binary_out = 9;
42
43
binary_out = 10;
44
45
binary_out = 11;
46
47
binary_out = 12;
48
49
binary_out = 13;
50
51
binary_out = 14;
52
53
binary_out = 15;
54
end
55
end
56 end
57
58 endmodule
You could download file encoder_using_if.v here
Encoder - Using case Statement
1 //---------------------------------------------------2 // Design Name : encoder_using_case

3 // File Name
: encoder_using_case.v
4 // Function
: Encoder using Case
5 // Coder
: Deepak Kumar Tala
6 //---------------------------------------------------7 module encoder_using_case(
8 binary_out , // 4 bit binary Output
9 encoder_in , // 16-bit Input
10 enable
11 );
13 input enable ;
15
16 reg [3:0] binary_out ;
17
18 always @ (enable or encoder_in)
19 begin
20
binary_out = 0;
21
if (enable) begin
22
case (encoder_in)
23
16'h0002 : binary_out = 1;
24
16'h0004 : binary_out = 2;
25
16'h0008 : binary_out = 3;
26
16'h0010 : binary_out = 4;
27
16'h0020 : binary_out = 5;
28
16'h0040 : binary_out = 6;
29
16'h0080 : binary_out = 7;
30
16'h0100 : binary_out = 8;
31
16'h0200 : binary_out = 9;
32
16'h0400 : binary_out = 10;
33
16'h0800 : binary_out = 11;
34
16'h1000 : binary_out = 12;
35
16'h2000 : binary_out = 13;
36
16'h4000 : binary_out = 14;
37
16'h8000 : binary_out = 15;
38
endcase
39
end
40 end
41
42 endmodule

Verilog Examples

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Verilog Examples

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Asynchronous reset D- FF

1 //----------------------------------------------------2 // Design Name : dff_async_reset

You could download file dff_async_reset.v here

1 //----------------------------------------------------2 // Design Name : dff_sync_reset

1 //----------------------------------------------------2 // Design Name : tff_async_reset

You could download file tff_async_reset.v here

1 //----------------------------------------------------2 // Design Name : tff_sync_reset

1 //---------------------------------------------------2 // Design Name : dlatch_reset

//-----------Input Ports--------------input data, en, reset ;

8-Bit Simple Up Counter

1 //---------------------------------------------------2 // Design Name : up_counter

8-Bit Up Counter With Load

1 //---------------------------------------------------2 // Design Name : up_counter_load

1 //---------------------------------------------------2 // Design Name : up_down_counter

//----------Output Ports-------------output [7:0] out;

Random Counter (LFSR)

1 //---------------------------------------------------2 // Design Name : lfsr

if (reset) begin // active high reset

You could download file lfsr.v here

Random Counter (LFSR)

1 //---------------------------------------------------2 // Design Name : lfsr

You could download file lfsr.v here

You could download file lfsr_updown.v here

1 //---------------------------------------------------2 // Design Name : gray_counter

One Hot Counter

1 //---------------------------------------------------2 // Design Name : one_hot_cnt

1 //---------------------------------------------------2 // Design Name : clk_div

1 //---------------------------------------------------2 // Design Name : divide_by_3

Divide By 4.5 Counter

1 //---------------------------------------------------2 // Design Name : clk_div_45

&& counter2 == 4)) begin

1 //---------------------------------------------------2 // Design Name : ram_sp_sr_sw

// Memory Write Block

Single Port RAM Asynch Read, Synch Write

1 //---------------------------------------------------2 // Design Name : ram_sp_ar_sw

//--------------Inout Ports----------------------inout [DATA_WIDTH-1:0] data

Single Port RAM Asynchronous Read/Write

1 //---------------------------------------------------2 // Design Name : ram_sp_ar_aw

//--------------Inout Ports----------------------inout [DATA_WIDTH-1:0] data

Dual Port RAM Synchronous Read/Write

1 //---------------------------------------------------2 // Design Name : ram_dp_sr_sw

62 // Memory Read Block

Dual Port RAM Asynchronous Read/Write

1 //---------------------------------------------------2 // Design Name : ram_dp_ar_aw

ROM/EPROM - Loading from File

1 //---------------------------------------------------2 // Design Name : rom_using_file

You could download file rom_using_file.v here

1 //---------------------------------------------------2 // Design Name : rom_using_case

1 //---------------------------------------------------2 // Design Name : syn_fifo

Note: This code is written in Verilog 2001.

Content Addressable Memory (CAM)

1 //---------------------------------------------------2 // Design Name : cam

// Register the outputs

1 //---------------------------------------------------2 // Design Name : parity_using_assign

You could download file parity_using_assign.v here

1 //---------------------------------------------------2 // Design Name : parity_using_function

You could download file parity_using_function.v here

1 //---------------------------------------------------2 // Design Name : parity_using_function2

You could download file parity_using_function2.v here

And the Practical One

1 //---------------------------------------------------2 // Design Name : parity_using_bitwise

Below code is 16-bit CRC-CCITT implementation, with following features

Initial value = 0xFFFF

Output CRC is NOT