2.

00 Introduction
“Design of a 2.10 Purpose

Debug Module The purpose of doing this project is to

study and design a debug module for
the MIPS-LITE processor.
for Mips
2.20 Scope
Processor”.
The scope of the project is to analyze
the instruction format and set of the
MIPS-LITE processor and feed the
Abstract: values such as Opcode, Source and
Destination operands by the Debug
This project describes about the design
module and display the Processor
and application of a functional verification
result in the LCD display.
methodology to MIPS-LITE processor.
The processor is a simplified version of Top Level Block diagram
MIPS architecture, with single-cycle The hardware block diagram is
instructions. The instruction set of the shown below. The pin description is
processor specified as input to this shown in following table.
project. The data path and control units
of the processor are defined to realize all Processor module: The processor is
the five steps of instruction fetch,
a simple version of MIPS processor.
decode, operand fetch, executes, and
The detail design of this single cycle
store. The verification will be done
MIPS processor is explained in
concurrently along with the design of the
Reference-1.The signals of the
various modules of the processor. A
Debug module will be designed to test processor module is given in Table-1.

the processor on single instruction

entered through a keyboard in machine
language. The cache and external
peripherals such as PWM and TIMER
will be added to the system to increase
the functionality..
 Debug Module: The Debug module
is used to feed instruction to the
3.0 PROCESSOR MODULE PIN instruction ROM as well as in single
DESCRIPTION instruction format to the processor.
The instruction machine code is
S.NO NAME I/O WIDTH DESCRIPTION
1. RST EXT I 1 ACTIVE LOW RESET keyed in through the keyboard. The

2. MASTER I 1 CLOCK
result of the processor ALU available
CLOCK
3. HALT I 1 PRCOESSOR
in special function register is
PROC EXCEPTION HALT,
ACTIVE HIGH
displayed on a LCD module. The
4. WAIT I 1 PROCESSOR WAIT,
ACTIVE LOW
signals of the debug module are
5. BUSY O 1 PROCESSOR BUSY,
ACTIVE HIGH
shown in Table-2.
6. ADD_IM O 10 ADDRESS OF
INSTRUCTION ROM
7. DATA_IM I 37 DATA OF DEBUG MODULE PIN
INSTRUCTION ROM DESCRIPTION
8. ADD_DM O 16 ADDRESS OUTPUT
FOR DATA MEMORY
S. NAME I/ WI DESCRIPTION
9. DATA_DM O 16 DATA OUTPUT FOR N O D
DATA MEMORY O T
10. READ_DM O 1 READ CONTROL H
SIGNAL OF DATA 1 RST EXT I 1 ACTIVE LOW RESET
MEMORY 2 MASTER I 1 CLOCK
11. WRITE_D O 1 WRITE CONTROL CLOCK
M SIGNAL OF DATA 3 HALT PROC O 1 PRCOESSOR EXCEPTION HALT,
ACTIVE HIGH
MEMORY
4 WAIT O 1 PROCESSOR WAIT, ACTIVE LOW
12. SFR_ENA I 1 SPECIAL FUNCTION 5 BUSY I 1 PROCESSOR BUSY, ACTIVE HIGH
BLE REGISTER ENABLE 6 SFR_ENABL O 1 SPECIAL FUNCTION REGISTER
13. SFR_REA I 1 SPECIAL FUNCTION E ENABLE
D REGISTER READ 7 SFR_READ O 1 SPECIAL FUNCTION REGISTER
14. SFR_DATA O 16 SPECIAL FUNCTION READ
REGISTER DATA 8 SFR_DATA I 16 SPECIAL FUNCTION REGISTER
DATA
15. OPCODE O 1 READ SIGNAL OF EXT. 9 IR MEMORY O 37 INSTRUCTION MEMORY DATA
READ INSTRUCTION ROM DATA
16. ADDRESS O 10 PROCESSOR BUSY, 10 IR MEMORY O 1 INSTRUCTION MEMORY WRITE
COUNTER ACTIVE HIGH WRITE
17. PWM_OUT O 1 PWM OUTPUT 11 IR MEMORY O 10 INSTRUCTION MEMORY ADDRESS
ADDRESS
12 LCD_EN O 1 LCD ENABLE
13 LCD_RS O 1 LCD COMMAND-DATA CONTROL
14 LCD_DATA O 8 LCD DATA
15 KBD_CLK I 1 KEYBOARD CLOCK
16 KBD_DATA I 1 KEYBOARD DATA
17 ADDRESS O 1 KEYBOARD DATA
COUNTER
Program Memory Module: The
program memory stores the
instruction to be used by the
processor. The debug module loads
the instruction. The instruction is
keyed in by the user using a
keyboard unit.

PROGRAM MEMORY MODULE

S NAME I/ WID DESCRIPTION

. O TH
N
O
1. MEMORY I 1 MEMORY WRITE SIGNAL
WRITE OF DEBUG MOD
2. IR MEMORY I 37 INSTRUCTION MEMORY
DATA DATA FROM DEBUG
3. OPCODE Read I 1 OPCODE READ FROM
PROCESSOR
4. IR MEMORY I 1O PROCESSOR ADDRESS
ADDRESS
Major components unit becomes high, the decoder is
identification resetted.

Keyboard Unit Control Unit

The input signals for keyboard are

keyboard clock, keyboard data,
keyboard enable signal from the
control unit and a system clock (10
times keyboard clock). When
keyboard enable signal is low the
keyboard data ‘1’ or ‘0’ keyed in by
This is the important block in the
the user is stored and forwarded to
module. This controls the keyboard
the following unit. The keyed data is
unit using buffer signal whether the
latched in the following unit by a
data is to be transferred or not. It also
trigger signal.
controls the temporary register using
Temporary Register the enable signal to latch the data to
respective fields. Based on the

This register is used to store the data category signal generated by the

coming from the keyboard unit and decoder unit, the state signals i.e.,

when enable signal from control unit the next fields to be selected are

is high, then data in it is latched to the generated.

respective fields. First, opcode is

Field Selector
latched to opcode decoder when
buffer signal is high.
When the field signals are generated
Opcode Decoder from the control unit, then field
selector generates the enable signal

The data latched from register is in order to select respective field

decoded and one of the eight where data is to be written. This field

categories is selected based on selector block interfaces the

which the next field signals are keyboard unit with the LCD unit.

selected. When reset from control When the opcode is decoded then
depending on categories selected,
the next field to be displayed is
decided by this block.
LCD Unit
It displays every data entered through
the keyboard and the data from field
selector. The data from temporary
register is connected to LCD unit.
Description:
The “Control unit” is the brain of the
system. It senses the “Complete”
signal generated by the “Opcode
temp register” and asserts the “Latch
decoder” signal to latch data into the
“Opcode Decoder”. It then senses the
“Category Signal” and asserts the “A,
B, C, D” signals as required for the
opcode (entered) and the WR signal
to latch data into the internal registers
of the “Opcode temp register”. The
ABCD signals decide which internal
register the data will be written to. It
then asserts the “Clear” signal to
clear the “Temp latch” inside the
“Opcode temp register”. This process
goes on till all the relevant data (for
e.g. SRC1 addr., SRC2 addr. , Target
addr. or IMMD data) has been taken
and stored in the internal registers of
the “Opcode temp register”. Then the
“Control Unit” asserts the “Memory
Write” signal to write the contents of
the internal registers of the “Opcode
temp register” into the program
memory. It also increments the
contents of the “Address counter”,
generates the “INTrst” to reset all the
blocks for the next opcode entry and
then re-initializes itself. This is for
data entry into the system.
When data or result has to be
retrieved from the SFRs (special
function registers) then the “Control
unit” will first sense the “Busy” signal
coming from the processor. This
signal tells the “Control unit” the state
of the processor. When the “Control
unit” senses that the processor has
executed the opcodes and stored the
results into the SFR, it enables the
“SFR read” signal along with the
“SFR en” signal to read the data from
the SFRs. These signals tell the “LCD
unit” that it has to take data from the
SFRs.
Input parameters
RST Ext
The power ON system reset signals
the beginning of the control
operation.
System Clock
The system clock is 10 MHz. This is
the operating clock of the control unit.
Complete
Indicates that the 6 bit OPCODE means “Enter Src1”, “Enter Src2”,
keyed in by the user is ready in the “Enter Tar” and “Enter Imm”
“Opcode temp register”. respectively.
Category
The category signal indicates the WR
types of Instructions. From the set of Signal to latch data into the internal
21 instructions the category are as registers (Opcode, Src1, Src2, Tar
follows. and Imm field of the Instruction
Cat1 =NOP, Ret, End, Cat2 = register) in “Opcode temp register”.
ALU R_type, Cat3 = Conditional
branch , Cat4 = R_Type Store, Clear
Cat5 = Memory Load, Cat6 The clear signal clears the registers
=Memory store, Cat7 = R_type store, (Src1, Src2, Tar and Imm field of the
Cat8 = PWM, Cat9 = Instruction register) in “Opcode temp
register” at the end of instruction
execution before a fresh Instruction is
Busy entered.
Indicates that the processor is busy
executing the instruction. The
dissertation of the busy signal by the Memory Write
processor indicates that the SFR data The Memory Write signal is used to
as a result of the last instruction is write the contents of the internal
ready for display. registers of the “Opcode temp
register” into the program memory.
Output parameters

Latch Decoder INCRaddr

Indicates that the Opcode Decoder
will latch the OPCODE data collected
by the “Opcode temp register”.
A, B, C, D
The ABCD signals decide which
internal register the data keyed in will
be written to. The “A, B, C, D” signals
The signal is used to increment the
contents of the “Address Counter”
which is used as the Memory address
of program memory.
RSTint
INTrst is used to reset all the blocks
of the debug module for the next
opcode entry and to re-initialize itself.

SFR read, SFR en

SFR read” signal along with the “SFR
en” signal are used to read the data
from the SFRs. These signals are
also used in the “LCD unit” to take
data from the SFRs and display.

Proc Halt
The control unit asserts the Proc Halt
to halt the processor.

Wait
The control unit asserts the Wait
signal in following the execution of
the instruction and keying in of new
instruction by the user.
Description

In the design only data and command

in binary form is given as input.
Hence only two keys of keyboard unit
that are 0 & 1. Whenever any key is
pressed on keyboard, keyboard unit
get data in the form of scan code
(PS2 keyboard). That means for ‘0’
key keyboard sends “01101001”(69h)
serially on Kbd_data input because
“01101001” is scan code of ‘0’.
Similarly “01110000” is scan code of
‘1’.

Keyboard unit fetch the scan code on

system clock frequency. Keyboard
unit checks the fetch scan code is of
0 or 1 according to that it assert data
signal high (for ‘1’) or low (for ‘0’)
respectively. Keyboard unit also
generate one trigger pulse (Trig) to
indicate that valid data is on the data
line. Trigger pulse is as long as one
keyboard clock cycle. If RST_int or
RST_ext is high then unit goes into System clock
reset state. The system clock is 10 MHz. This is
the operating clock of the keyboard
There are two state machines for controller unit.
operation of keyboard unit. First state
machine operate on system clock
and use to check start bit of scan
code. Second machine operate on
keyboard clock, which actually fetch Output parameters
the data and assert data signal. Both
FSM generate interdependent signals Trigger
like reset, start, break etc. Keyboard unit generate trigger pulse
Input parameters to indicate that valid data is on the
data line. Trigger pulse is as long as
RST Ext one keyboard clock cycle.
The power ON system reset signals
the beginning of the total system Data
operation. When only two keys of keyboard unit,
that are 0 & 1 are pressed, keyboard
RST Int sends the scan code
RST Int is used to reset all the blocks “01101001”(69h) and scan code
of the debug module for the next “01110000”(70h) respectively serially
opcode entry and to re-initialize itself. on Kbd_data. The keyboard unit
decodes these scan code and sends
KBD clock only high (1) and low (0) for key ‘1’
The power ON system reset signals and ‘0’ respectively.
the beginning of the total system
operation.

KBD data
INTrst is used to reset all the blocks
of the debug module for the next
opcode entry and to re-initialize itself.
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