Stabilization Methods for Integrated High Voltage

Charge Pumps
Lufei Shen, Ferdinand Keil, Klaus Hofmann
Integrated Electronic Systems Lab, Technische Universitt (TU) Darmstadt, Germany
Lufei.Shen, Klaus.Hofmann@ies.tu-darmstadt.de, ferdinandkeil@googlemail.com
AbstractCharge pump circuits are currently becoming a
realistic alternative to the switching regulators in high voltage
generation applications, especially in fully integrated circuit
systems. This paper discusses several stabilization methods to
improve voltage performance and robustness of integrated high
voltage charge pumps. All the discussion and measurements are
based on a monolithic integrated high voltage charge pump chip
adopting an innovative circuit architecture and advanced clock
scheme to overcome drawbacks of conventional charge pump
circuit architectures. The possibility to integrate the stabilizing
parts into the entire circuit system is also analyzed.

The proposed charge pump architecture was implemented

in Balios without feedback regulations. After more than 1000
hours continuous operation of the 2nd chip Balios, some
measurement results were reported in Fig. 2 and 3. Due to the
low overall power consumption at about 140 mW, Balios has
no self-heating problems, while the average overall power
efficiency is round 10%.

Keywordshigh voltage; charge pump; feedback; regulation

I.

INTRODUCTION

On-chip high voltage generators as important circuit

building blocks provide the essential high voltage DC bias
voltage for portable integrated circuit systems. Charge pump
circuit architectures are considered to be the most promising
solution to realize the full integration of the high voltage
generation function, comparing the switching converters with
discrete inductors [1]. Many novel charge pump architectures
for high voltage generation are proposed and verified in silicon
[2] [3]. To enhance the voltage performance and to maintain
the robustness of integrated charge pump circuits, effective
stabilization methods are thus demanded to be applied.
II.

Fig. 1. Chip foto of the 40 stage 4-phase charge pump Balios with on-chip
4-phase clock generators

In Fig. 2 and 3, the influences of clock frequency and DC

power supply on the voltage performance of the charge pump
circuit are illustrated, respectively. The measurement results
demonstrate that if the charge pump circuit is designed at some
certain DC supply voltage and clock frequency, the output
voltage can be regulated by changing the applied DC supply
voltage or clock frequency.

HIGH VOLTAGE CHARGE PUMP

A. Integrated High Voltage Charge Pump Balios with OnChip Clock Generation
The charge pump architecture adopted in this paper is based
on advanced high voltage triple-well CMOS processes. Using
dynamic bulk-biasing technique at MOS switches and 4-phase
clock schemes with dead time techniques, this architecture
overcomes the drawbacks of Pelliconi charge pumps [4] [5]
such as body effect problems of MOS-switches, reverse current
problems at each stage etc.
The 2nd chip after the already in [6] presented 1st test chip
was received in August of 2013 with codename Balios. (See
Fig. 1.) It was fabricated in the 120 V H35 CMOS process of
AMS and consists of 40 stage cascaded proposed charge pump
architecture, 4-phase on-chip clock generators and large clock
buffers, which totally amount to 4.4 mm X 4 mm = 17.6 mm.

Fig. 2. Output voltage of the 2nd Chip Balios with external clock signals
under 3.7 V DC supply at Rload = 1M and Cload = 16 pF

Fig. 3. Output voltage of Balios with external 20 MHz clock signal under
various DC supply voltages at Rload = 1M and Cload = 16 pF

978-1-4799-4558-0/14/$31.00 2014 IEEE

978-1-4799-4558-0/14/$31.00 2014 IEEE

III.

STABILIZATION METHODS

Since the voltage performance of the charge pump circuit

will be influenced by many factors such as changes of load
current, noise at DC voltage supply, mismatching of integrated
capacitors, unbalanced delays in the clock distribution, etc.,
feedback regulation is necessary to stabilize the output voltage
of the charge pump.

C
I out
Vout = VDD + N VCLK

C + C S (C + C S ) 2 f

(1)

The output voltage of the charge pump is usually a function

of DC power supply, pumping capacitor value, clock
frequency, load current and stage number. Equation (1) shows
the relationship between the output voltage of the Pelliconi
charge pump and these above mentioned parameters [6]. Once
the circuit is designed, namely with fixed pumping capacitor C
and its parasitic capacitor Cs and the stage number N, the only
changeable parameters are DC power supply VDD, clock
frequency f, and load current Iout. (Load current Iout can be
controlled by high voltage linear regulators at the load side, but
linear regulators have low power efficiency and consume alone
already large static current, which is not suitable for low power
and low output current applications.) In this paper we discuss
mostly the feedback regulation regarding DC power supply
VDD and clock frequency f.

Fig. 4. Feedback regulation by adjusting DC power supply

Fig. 5. Feedback regulation by adjusting clock freqeuncy

Fig. 4 explains the principle of the feedback regulation by

adjusting the DC power supply of the charge pump circuit. The
low voltage boost buck charge pump circuit provides the
suitable DC power supply voltage between e.g. 3 V and 5 V
from the available 3.7 V battery voltage. This step-up or step-

down voltage generation depends on the control voltage Vctrl,

which is generated from the feedback voltage Vfb and the
reference voltage Vref with the aid of the error amplifier. Once
the feedback voltage Vfb is determined by fixed voltage divider
for required output voltage Vout, this concept can realize the
stabilization of the output voltage of the charge pump circuit.
Fig. 5 presents the principle of the feedback regulation by
adjusting the clock frequency of the charge pump circuit. The
low voltage charge pump is to provide stable DC supply
voltage for the high voltage charge pump, which can be
omitted, if the battery voltage remains stable during the
operation of the high voltage charge pump. The voltage
controlled oscillator speeds up or slows down the clock
frequency according to the control voltage Vvco, which is
produced at the error amplifier by comparison between
reference voltage Vref and the feedback voltage Vfb. The
feedback voltage Vfb is defined by the required output voltage
Vout. Thus, the stabilization of the output voltage of the charge
pump can be achieved.

Fig. 6. Other stabilization methods

Due to the adopted low voltage isolated transistors in the

integrated charge pump circuit and the maximum operating
voltage of the high voltage semiconductor technology, some
other stabilization methods are essential to ensure the robust
operation of the circuit and protect the circuit from permanent
damage. The adopted charge pump circuit architecture employs
triple-well low voltage isolated transistors, whose horizontal
breakdown voltage between Drain and Source(Gate) terminals
is still low voltage e.g. maximal 5.5 V, even if their vertical
breakdown voltage from each terminal of the transistors to the
substrate reaches the high reverse breakdown voltage between
the underlying deep NWELL and the p-substrate [5][7]. The
high voltage transistors are not applicable in the proposed
charge pump architecture because of their tied Source and Bulk
terminals. For this reason, the DC voltage supply should be
lower than 5.5 V to avoid the Drain-Source breakdown voltage
of these low voltage isolated transistors, and any drastic
changes of the load current, which induces short-time voltage
difference higher than 5.5 V between the output voltage and
the voltage potential at the pumping capacitors of the last stage,
should be avoided. Besides, the high voltage semiconductor
processes can not withstand voltage higher than their maximum
operating voltages. The output voltage of the charge pump
circuit should not exceed this voltage limitation at any time
during the operation.
Fig. 6 demonstrates three possible stabilization methods for
the robustness of charge pump circuits, assuming that the DC
power supply voltage is within the tolerable range.
In Case (a), the high-capacitance load capacitors can not
only smooth the output voltage by reducing the voltage
ripple, but also decrease abrupt voltage drop at the
output. Because of the adequate charge amount at those

large load capacitors, abrupt changes of load currents

can be controlled, so that only small voltage difference
under the safe limit will be caused. The long charge or
discharge time also provides the charge pump circuit
enough time to reach the new stable condition at higher
or lower voltages. However, this method can only
handle slight changes of load currents. In extreme cases
such as abrupt short circuit at the load, the output
voltage changes can no longer be under control. In
addition, large load capacitors increase the ramp-up
time and recovery time of the charge pump circuit,
which is not preferred at high speed applications.
In Case (b), output diodes with high reverse voltage are
used to protect the charge pump circuit from the high
voltage spike at the load side. Nevertheless, in the stepup high voltage charge pump circuit, the output voltage
of the charge pump is the highest voltage potential in
the circuit, therefore, such protection is not very useful
and introduces about 0.7 V undesired voltage drop. If
the load current decreases, the output voltage of the
charge pump even without those output diodes will
reach a higher voltage level safely, which is similar to
the start-up of the charge pump. If the load current
increases, the output voltage of the charge pump with
such output diodes will reach a lower voltage level after
abrupt high output voltage changes, which could lead to
the breakdown of the low voltage isolated transistors at
the last stage of the charge pump. In general, this
stabilization method can merely protect the charge
pump circuit from possible external high voltage at the
load side, which is however not common at integrated
high voltage step-up charge pump circuits.
In Case (c), ESD diodes such as Zener diodes are
applied to prevent the output voltage of charge pumps
from exceeding the maximum operating voltage of the
high voltage semiconductor technologies. They can be
easily integrated into the circuit and stabilize the output
voltage at the same highest voltage level, if the charge
pump circuit is designed properly to generate output
voltage much higher than the maximum operating
voltage of the high voltage semiconductor technologies.
However, in such cases, currents through these ESD
diodes should be under the current limitation of these
diodes, and they are in principle wasted. Thus, this
stabilization method is normally only for protection of
the charge pump circuit against voltages exceeding the
technology limit.
In this section, five stabilization methods for the voltage
performance or robustness of fully integrated high voltage
charge pumps are introduced and analyzed. Most of them will
be verified by measurements based on the 2nd Chip Balios
discussed in this paper.
IV.

to realize the function blocks shown in Fig. 4 and 5: voltage

controlled oscillator: 74HC4046; low voltage boost buck
charge pump: MCP1253-ADJ; voltage reference: REF92GPZ;
error amplifier: AD823ANZ. To investigate the thermal
behavior of the test circuits, conditioning cabinet HC4005 was
applied to vary the operating temperature of the two test
circuits between 20 C and 100 C.
In Fig. 7, the measurement results of the feedback
regulation method by adjusting the clock frequency at the room
temperature are displayed. The effective feedback regulation of
the charge pump circuit by adjusting the clock frequency
operates properly, so that the output voltage remains at the
previously selected value 110 V. In Table I, the measurement
results prove the stability of this clock frequency feedback
regulation against the environmental temperature. The increase
of the clock frequency at higher temperature can be explained
by the non-linearity of the discrete components and ICs, while
the output voltage of the charge pump is still stabilized.

Fig. 7. Measurement results of feedback regulation by adjusting clock

frequency
TABLE I.

MEASUREMENT RESULTS OF FEEDBACK REGULATION BY

ADJUSTING CLOCK FREQUENCY AT DIFFERENT TEMPERATURES

Rload (k)

DC power supply: Vdd = 3.686 V

Temp (C)

Vout
(V)

f
(MHz)

Cload
(pF)

833

20

110.11

15.249

106

833

60

110.47

15.586

106

833

100

111.05

18.64

106

In Fig. 8, the measurement results of the feedback

regulation method by adjusting the DC power supply of the
charge pump at the room temperature are also displayed. By
regulating the DC supply voltage for the charge pump through
the feedback circuits, the output voltage of the charge pump is
stabilized at the previously selected value 110 V at various
load resistors. In Table II, good stability of the voltage
performance against the environmental temperature is
demonstrated.

EXPERIMENTAL RESULTS

Two test circuits based on the 2nd chip Balios were built
to verify the output voltage stabilization methods for integrated
high voltage charge pumps by adjusting DC power supply and
clock frequency, respectively. The following ICs were adopted

Fig. 8. Measurement results of feedback regulation by adjusting DC power

supply

TABLE II.

MEASUREMENT RESULTS OF FEEDBACK REGULATION BY

ADJUSTING DC POWER SUPPY AT DIFFERENT TEMPERATURES

Rload (k)

Clock frequency: f = 20 MHz; 3.7 V Battery

Temp (C)

Vout
(V)

Vin
(V)

Cload
(pF)

833

20

110.1

3.598

106

833

60

110.1

3.602

106

833

100

110.2

3.626

106

TABLE III.

MEASUREMENT RESULTS OF STABILIZATION METHOD FOR

THE ROBUSTNESS OF THE CHARGE PUMP CIRCUIT
f = 20 MHz; Vdd = 3.7 V, Temp = 20 C
Cload

Vout
(V)

Vout in
the 1st 100
us
(V)

Recovery
time

910 476

6 pF

114 100

14

50 s

910 476

16 pF

114 100

14

100 s

910 476

100 pF

114 100

12

150 s

910 476

1 nF

114 100

12

500 s

Rload (k)

910 476

10 nF

114 100

2 ms

910 476

100 nF

114 100

<< 1

20 ms

The stabilization method using load capacitors for the

robustness of the circuit is investigated experimentally. Table
III shows the measurement results for different load capacitors,
when the charge pump circuit without any feedback regulation
and the load resistor changes from 910 k to 476 k abruptly.
The value of the load capacitor doesnt affect the stable value
of the output voltage Vout, it does influence the instant output
voltage drop and the recovery time for the charge pump to
reach the new stable state. Larger load capacitor reduces the
short-time output voltage drop, increases the robustness of the
circuit, but causes also very long recovery time. The abrupt
increase of the load resistors brings similar results and it will
mostly not damage charge pump circuits, when the output
voltage of charge pumps is limited by Zener diodes.
V.

DISCUSSION

Both feedback regulation methods to stabilize the output

voltage of the high voltage charge pump against changes of
operating conditions such as load and temperature variations
are proven to be effective. All the ICs adopted in the test
circuits are low voltage, whose functions can be easily realized
on-chip and further optimized. The voltage reference is very
important in both feedback regulation. Thus, an external stable
voltage reference is preferred.

The feedback regulation by adjusting the DC power supply

shows better stabilization performance compared with that by
adjusting clock frequency, mainly due to the instability of the
clock frequency generated by the voltage controlled oscillator.
However, the low voltage charge pump consumes alone
significant power and occupies large layout area for the on-chip
integration, while the voltage controlled oscillator is usually
small in the chip layout and has very low power consumption.
Tradeoffs between output voltage performance and power
consumption (or chip size) should be made, when feedback
regulation methods are introduced.
Large output capacitors can considerably smooth the output
voltage waveform of the high voltage charge pump. However,
the recovery time of the circuit will be longer, which could be
not desired in high speed applications. Furthermore, capacitors
of high capacitance are extremely large in the chip layout,
which are usually supposed to be off-chip. The diodes can
provide protection for the charge pump circuits from too high
voltage at the load, however, they are usually parasitic diodes
in integrated circuits and play a secondary role in integrated
high voltage charge pump applications.
VI.

CONCLUSION

Several beneficial stabilization methods to improve voltage

performance and robustness of integrated high voltage charge
pumps are analyzed and investigated theoretically and
experimentally. All the solutions are able to be fully integrated
into the whole circuit system.
ACKNOWLEDGMENT
The authors thank the LOEWE research initiative of the
state of Hesse/Germany for supporting this research and
development within the LOEWE Priority Program Cocoon.
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