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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 5.4-mW 180-cm Transmission Distance 2.5-Mb/s

Advanced Techniques-Based Novel Intrabody
Communication Receiver Analog Front End
Hao Wang, Student Member, IEEE, Xian Tang, Member, IEEE, Chiu Sing Choy,
Ka Nang Leung, Senior Member, IEEE, and Kong Pang Pun, Senior Member, IEEE

Abstract This paper presents a low power, long-transmission

distance, high data rate intrabody communication (IBC) analog
receiver front end (RFE). First, to optimize the transmission
performance, conventional transmission line analysis scheme is
creatively adopted to the IBC design to characterize the body
channel. Second, switched-capacitor filters based on sampling
rate boosting technique are adopted for higher accuracy and
lower power consumption. Third, a novel RFE topology is
proposed to further enhance the IBC performance. The new RFE
is designed and fabricated in a standard 180-nm CMOS process.
Measurement results show that the RFE can successfully transmit
data spanning the whole human body, around 180 cm, which
is one of the longest transmission distances reported in related
literatures. Furthermore, it reaches a maximum data rate of
2.5 Mb/s with a bit error rate less than 1e-7 and consumes 5.4 mW
from a 1.8 V supply. The proposed RFE compares favorably to
similar reported works.
Index Terms Bit error rate (BER), intrabody communication (IBC), matching network, receiver front end (RFE),
sampling rate boosting, switched-capacitor (SC) filter,
transmission distance, transmission line (TL).

I. I NTRODUCTION

OWADAYS, with the invention and proliferation of

smart wearable electronic devices like cell phones,
smart watches and glasses, bio-medical sensors, and so on,
off-air communication techniques, such as capacitive coupling
used in these devices, have gained a lot of attention in the
research community. As a major branch of body area network,
intrabody communication (IBC) uses the human body as
a communication medium to implement data transmission
between various wearable devices, as shown in Fig. 1.
Comparing with other conventional wireless techniques,
IBC offers the advantages of low radiation, low power

Manuscript received August 7, 2014; revised October 31, 2014; accepted

November 23, 2014.
H. Wang, C. S. Choy, K. N. Leung, and K. P. Pun are with the
Department of Electronic Engineering, the Chinese University of Hong Kong,
Hong Kong (e-mail: wanghao@ee.cuhk.edu.hk; cschoy@ee.cuhk.edu.hk;
knleung@ee.cuhk.edu.hk; kppun@ee.cuhk.edu.hk).
X. Tang was with the Department of Electronic Engineering, the Chinese
University of Hong Kong. He is now with the Graduate School
at Shenzhen, Tsinghua University, Shenzhen 518055, China (e-mail:
tang.xian@sz.tsinghua.edu.cn).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2014.2379443

Fig. 1.

Devices communication network based on IBC.

consumption, high data rate, widebandwidth, small area,

and privacy. Anticipating the significant role that IBC will play
in the near future, researchers have spent much effort on the
modeling of human body channel [1], [2]. However, existing
models are largely based on electromagnetic field theory and
are not readily applicable to IBC physical layer design. This
has a serious impact on realizing IBC to its full commercial
potential. Furthermore, achieving high-transmission speed
(>1 Mb/s) across body tissues acting as parasitic capacitors
and resistors is very difficult. Ensuring good transmission
performance at high data rate and over long distance is a
big challenge. Moreover, in conventional IBC RFE design,
RC filter and hysteretic comparator are often used in signal
recovery and signal level threshold decision. They suffer
from large device mismatches and high power consumption,
further limiting the progress of IBC development.
To tackle the above problems, the following techniques
based on electric-field IBC theory [2] and wideband signaling
IBC scheme [3], are proposed in this paper: first, matching
network is explored to optimize the body communication
channel parameters. An IBC transmission channel is formed
by coupling electric field between electrodes and body. With
increasing signal frequency, the body communication channel
can be modeled as a transmission line (TL). As a result,
impedance matching network, from the transmitter (TX)

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2

Fig. 2.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 3.

Lumped RC electrical model and transmission scheme.

Fig. 4.

Body channel equivalent circuit and its transmission line model.

Architecture of IBC transceiver.

electrode, through the body channel, to the receiver (RX)

electrode, can be used to positively improve on the
S21 parameter (transmission attenuation). This kind of
channel optimization is considered a novelty in the context
of IBC receiver front end (RFE) design. Second, switchedcapacitor (SC) filters take the place of RC filters to minimize
mismatch and power consumption. Normally, conventional
SC filters are not suitable for high data rate systems. Therefore,
a novel sampling rate boosting SC filter is proposed. Third,
a new RFE topology combining all the previously suggested
techniques is developed. For comparison, a conventional
threshold decision (CTD)-based RFE is also implemented.
Our RFE shows superior performance over the conventional
design.
The rest of this paper is organized as follows. Section II
discusses the body channel communication matching network.
Section III introduces the oversampling boosting technique
and presents detailed analysis under nonideal operating conditions. The circuit implementation is presented in Section IV.
Section V offers measurement results from test chips and
Section VI concludes the findings.
II. M ATCHING N ETWORK D ESIGN
A. Conventional RFE Architecture
Fig. 2 shows a block diagram of the architecture of an
IBC transceiver, which is derived from [3]. At the TX end,
after a series of processing like coding, modulation, buffering,
and band-limiting filtering, binary carrier signal is coupled
to the human body channel through electrode attached to
the body. At the RX end, the signal is first recovered by
an RFE, and is then sent to the following digital circuits or
measurement equipment. Generally speaking, the RFE is the
most critical component in such body communication channel
and determines the transmission performance. In this paper,
we will focus on the RFE module and its matching network.
B. Body Channel Modeling Scheme
In the literature, various body channel models have been
proposed exploring different theories, such as finite element
method [4], finite difference time domain [5], statistical [6],
and electric field from infinitesimal dipole calculation [7].
All of these models characterize signal propagation through

human body based on electromagnetic field mechanism. Body

channel characteristics derived from these models are too
complex for the transceiver circuit design, especially for long
distance (over one persons height) transmission with high
data rate (>1 Mb/s). For the transceiver physical layer design,
body channel is always modeled as a lumped RC electrical
model [2], [8], as shown in Fig. 3. Based on electric-field
IBC theory, signal path is constrained within human body
channel with signal return path formed by parasitic
capacitor, C p , between the transceiver and the external
environment. CTX and CRX are the capacitors modeling the
interface between hands and electrodes. However, there are too
many parameters still unknown and their values change with
different transmission distances and data rates. To determine
these complicated values one by one under various conditions
is not practical.
In this paper, we model a body communication channel
using TL. Relevant S parameters can be measured using a
vector network analyzer (VNA). The equivalent circuit for the
body channel and the related TL model are shown in Fig. 4.
Considering the signal path (body channel) and the capacitive
return path, the TX and RX can be treated as two-port
terminals. Based on TL theory, it is necessary to find an

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WANG et al.: 5.4-mW 180-cm TRANSMISSION DISTANCE 2.5-Mb/s ADVANCED TECHNIQUES-BASED NOVEL IBC RECEIVER ANALOG FRONT END

Fig. 6.

Fig. 5.

Measurement setup of IBC with different instruments.

impedance matching network between these two terminals

to maximize signal power delivery and to eliminate signal
reflection. As shown in Fig. 4, ST 1 and S R1 are the incident
signals to succeeding stages, and ST 2 and S R2 are the reflected
signals to preceding stages. An ideal, lossless transmission
can be achieved if S11 and S22 are 0 and S21 is 1. The most
straightforward and effective method to optimize the S21 parameter is to employ impedance matching at the TX terminal,
through the body channel impedance Z body, to the receiver
RX terminal. More details will be given after introducing the
measurement setup in the following section.

Body channel attenuation with hand-to-hand transmission distance.

signal propagation through different body tissues. A parametric model was reported describing the variation of dielectric
properties of body tissues at different frequencies [11]. In this
paper, signal is transmitted through the body by electric field
coupling. Signal propagation is mainly constrained on the
surface of the body [12], or in skin tissue layer. Therefore, the
effectiveness of such body channel accordingly depends on
transmission distance and transmission frequency. In practice,
distance is more of an issue because of the desire to span
the whole body length with wearable devices. We adopt the
distance between fingers on opposite hands (around 180 cm)
as our critical design goal. As found in [9], the characteristics
of a particular body channel deviate only by 2 dB between
different days. The relative stability of body channel characteristics gives credibility to our methodology.
According to the measurement setup shown in the bottom
of Fig. 5, the S21 parameter at different frequencies is measured with VNA and is plotted in Fig. 6. It is noted that signal
attenuation through human body is extremely large and the
frequency response varies widely. As a result, abnormalities
like intersymbol interference (ISI), harmonic introduction and
nonlinear distortion will seriously affect digital transmission.
To improve the S21 parameter characteristic, a matching
network at both terminals of TX and RX can be designed
using tools like advanced design system (ADS).

C. Measurement Setup
Fig. 5 shows the measurement setup for IBC. The digital
data to be transmitted is generated in the TX initially with an
AD9854 signal generation chip. The binary carrier is directly
coupled to the body channel through contacting the copper
electrode. At the receiver end, signal received is monitored
in real time. An oscilloscope is used to show the transient
response and eye diagram. A spectrum analyzer is utilized
for spectral analysis. A logic analyzer is used to sample
the received data and to calculate the bit error rate (BER).
According to [9] and [10], S parameters can be determined by
the setup shown in the bottom of Fig. 5, where two baluns are
adopted to isolate the grounds of TX and RX for authenticity
and accuracy. The measured S parameters denote information of attenuation (S21 ), TX terminal reflection (S11 ), and
RX terminal reflection (S22 ), which characterize the human
body channel. This kind of information helps to determine
design parameters of the transceiver as well.
Rather than considering each person individually, general
body channel characteristics can be derived from studying

D. Matching Network Design Using S Parameters

The main target of matching network at TX/RX terminal
is trying to deliver maximum power to the followed stage
under specific distance and center frequency. Fig. 7 shows
its topology using passive components. CTM and L TM are
the components for TX terminal matching, CRM and L RM
are the ones for RX terminal matching. In this paper, the
transmission distance is fixed to be 180 cm (finger-to-finger
on opposite hands), and the matching characteristic impedance
Z 0 is 500  (finger impedance) [13]. Accordingly, and as a
compromise between speed, power, and chip size, 2.5 MHz
is chosen to be the carrier center frequency which is high
enough for video graphics array (VGA), audio applications or
biomedical signals.
Based on TL theory, the relationship between input
impedance at TX terminal and S11 parameter before matching
is as follows:
1 + S11 (0 )
(1)
Z in (0 ) Z 0
1 S11 (0 )

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Fig. 7.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Impedance matching network with LC components.

TABLE I
B ODY C HANNEL M ATCHING N ETWORK PARAMETERS

where 0 is the center angular frequency at 2.5 MHz, Z 0 is

the finger impedance, whose value is 500 , and Z in is the
body channel input impedance before matching. To implement
the matching network, the following have to be satisfied:

Z in
(0 ) = Z in (0 )//Z LTM (0 ) + Z CTM (0 ) Z 0
Z (0 ) Z 0

S11
(0 ) = in
( ) + Z 0
Z in
0
0

(2)
(3)

where Z LTM and Z CTM are the impedances of inductor and

is the impedance after
capacitor at TX terminal and Z in
matching. The values of Z LTM and Z CTM shown in Fig. 7
after
should be elaborately designed so that the impedance Z in

matching could be 500  at 0 . Then S11 parameter after

matching will approach to zero, which means the reflection
power is depressed. Z LRM and Z CRM at RX terminal are
designed in the same way, but S22 is adopted instead. In this
paper, the values of four LC components shown in Fig. 7 are
calculated by ADS smith chart tool. Related design parameters
are summarized in Table I.
The transmission curves before and after matching are
shown in Fig. 8(a) and (b). It indicates that the S21 parameter
is 11.06 dB compensated at its center frequency and
reveals greatly improved channel attenuation characteristics.
Meanwhile, the signal response is smoother and flatter in
high-frequency band compared with the original one. A flatter
response helps to minimize the ISI problem [14] in digital
communication. The S11 (S22 ) parameters before and after
the matching are shown in Fig. 8(c). The amplitude of the
reflected signal drops sharply at center frequency in the
after-matching cases. Furthermore, the transient waveforms

Fig. 8.
(a) Body channel S21 attenuation after matching. (b) Body
channel S21 attenuation after matching (scaling). (c) Body channel S11 and
S22 parameters.

at center frequency without and with matching are shown

in Fig. 9. Before matching, there are many reflected signal
components mixed into the transmitted signal introducing
serious interference. After matching, the S21 parameter is optimized and reflected components are eliminated. As a result,
a purer signal is transmitted and obtained at the RX front
end. The RFE performance with/without matching network
will be discussed in Section V. Although the proposed
matching network is specific only a particular application
condition, the concept and design methodology are applicable
to any kind of IBC applications.
III. S AMPLING R ATE B OOSTING T ECHNIQUE
IN SC I NTEGRATOR
A. Sampling Rate Boost Technique
In IBC receivers, continuous time filters are conventionally
used [3], [8]. However, they have large variation in frequency
response due to device variations. Frequency tuning or
component trimming techniques can help but may lead to

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WANG et al.: 5.4-mW 180-cm TRANSMISSION DISTANCE 2.5-Mb/s ADVANCED TECHNIQUES-BASED NOVEL IBC RECEIVER ANALOG FRONT END

Fig. 9.

Received signal without and with matching network.

larger chip size, worse nonlinearity, and higher cost. To address

this issue, a SC filter is used in our IBC receiver for better
device matching, higher accuracy, and lower power consumption, benefiting long-distance IBC applications suffering from
large signal attenuation and noise power.
Using SC integrator, nonoverlapped clocks are normally
employed to define two circuit states: sample and hold. The
operational amplifier (OP-amp) involved is thus idle in half of
the clock cycle resulting in power inefficiency. Our solution
is based on the double sampling technique in [15] to improve
the power efficiency and obviously the sampling rate as well.
However, double sampling is still constrained by the system
clock at high data rate. We further advocate the use of
multiinterleaved clocks (four for example) with the same
frequency but active at different phases so that the sampling
rate is boosted by a factor equal to the number of interleaved
clocks. Intuitively, the concept can be expanded to arbitrary
sampling rate boosting if more interleaved system clocks are
adopted. Therefore, the proposed technique is not a mere
extension of double sampling. An analysis with four-time
sampling rate boosting is given to elaborate the technique.
This technique is first proposed and applied to the RFE
in [16]. However, the absence of analysis considering nonideal
conditions such as OP-amp finite gain, capacitors mismatch,
and noise means its usefulness is doubtful. To make matter
worse, an incomplete receiver structure is given in [16] (only
biquad filter is utilized) offering unattractive performance and
therefore inappropriate for high-performance IBC applications.
These problems will be addressed in this paper one by one
leading to a novel and robust receiver front end structure
proposed in Section IV.
Fig. 10 shows a SC integrator implemented with the
four-time sampling rate boosting technique. Whenever the controlling clocks Ph1, Ph2, Ph3, and Ph4 go high, the switches
are closed. The capacitors in all four branches should have
the same value (mismatch will be discussed later). Its timing
setup is also shown in Fig. 10, where Ph1Ph4 are controlling
signals of the same frequency but have different phases.
Applying the principle of charge conservation, we can derive a
transfer function H (z) for the SC integrator. Take the delayed
noninverting SC integrator shown in Fig. 11 as an example;
at time [n 2/4], branch 3 has already transferred the
sampled charge. Thus, considering branch 4 alone, we can

Fig. 10.

Proposed four-time sampling rate boost integrator.

Fig. 11.

Behavior analysis at time [n 2/4].

write



C1 Vin n 34
CF





3
2
+ Vout n
= Vout n
4
4

(4)

and after z-transform, it becomes

z 4
C1 1
1
C1

=
z 4
2
1
C F z 4 z 34
CF
1 z 4
3

H (z) =

(5)

and let z (1/4) exp[(1/4)sT ] 1 (1/4)sT to give



1
C1 1
C1
1

, sT  1. (6)
H (s) =
1 sT 1
1
CF
4
C
sT
F 4 sT
4
Similarly, the transfer function of a nondelayed inverting type
integrator can also be derived. In this case, only branch 2
needs to be considered at time [n 2/4]
C1
z 4
C1
1
H (z) =

2
C F z 4 z 34
C F 1 z 14
2

(7)

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Fig. 12.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Nonideal case with finite OP-amp gain A.

Fig. 13.

and let z 1/4 exp[(1/4)sT ] 1 (1/4)sT

H (s) =

C1
C1
1
1
=

C F 1 1 + 14 sT
C F 14 sT

(8)

so the conclusion in (8) shows that the phase is 180 shifted

without delaying and the sampling rate is also boosted by
four times.
B. Nonidealities Analysis
1) OP-Amp Nonidealities: The performance of a SC integrator is affected by a variety of nonideal conditions, such as
OP-amp finite gain, device mismatch, and noise. The effect
of finite OP-amp gain is considered first. Since the analysis
of the two SC integrator types is almost the same, only the
delayed noninverting type is discussed and shown in Fig. 12.
The reference time point is still [n 2/4]. In this case, the
virtual short property is not exact; therefore, the voltage at
the OP-amp negative input is V = Vout /A. Based on the
principle of charge conservation




2
3
Vout n
Vout n
4
4





2
3
= V n
V n
4
4
 



C1
3
2
+
Vin n
+ V n
.
(9)
C2
4
4
Then the final transfer function is derived as
H (z) =


1 + A1 1 +

C 1 14
CF z
C1
CF


1+

1
A

where = 1/( UGF), = C F /(C F + C1 ), then

10
1.6
UGF >
=
.
2Tclk
Tclk

(12)

Equation (12) has to be satisfied in conventional SC integrator design. However, in the proposed technique, although
the sampling frequency is increased by four times, there is no
need to enhance the UGF of OP-amp with four folds. First,
the OP-amp in conventional SC is only active in half of the
clock cycle, so it has to settle within Tclk /2. The OP-amp in
the proposed circuit is always active in the whole clock cycle.
That means, the settling time is only halved. Second, if the
value of C1 /C F is supposedly equal to 1/4, it is obvious that the
feedback factor is only increased by a little, from 0.5 to 0.67.
That means, the UGF is slightly lower than the expected value.
All in all, the UGF of the proposed circuit UGF P is
UGF p > 1.5UGF.

(13)

According to (13), to increase the sampling rate by four

times with the proposed technique, the UGF is only required
to be increased by 1.5 times.
2) Capacitor Mismatch: It is here assumed that there are
differences in mismatches against C0 among the capacitors in
the four branches, C1 , C2 , C3 and C4 , as shown in Fig. 13.
As a result, we need to calculate the four branches transformation one by one. For C1 branch






C1 Vin n 24
5
1
= Vout n
.
(14)
+ Vout n
CF
4
4
Therefore, the transfer function for branch C1 is

z 4

(10)

(11)

C1
z 4
C0 + 1
z 4

. (15)
C F z 14 z 54
CF
1 z 1
2

H (z)C1 =

where A denotes the finite gain of the OP-amp. It clearly

shows that the finite amplifier gain shifts the integrators poles.
However, as C1 is always 1/4 of the conventionally used value,
we can conclude that the shifting in the proposed technique is
smaller than that in the normal case.
Unity gain frequency (UGF) is another important parameter.
In the conventional case, the OP-amp has to be settled within
half of the sampling clock Tclk . If the OP-amp has 75 phase
margin and the settling error is 0.1%, it has to ensure
Tclk
> 0.7 ln()
2

Nonideal case with capacitors mismatch at [n 2/4].

As the other three branches have a mutual delay of z1/4 ,

we can write down the final transfer function as
C0 + 1 z 4
(C0 + 2 ) z 4
H (z) =
+
C F 1 z1
CF
1 z1
1

(C0 + 3 ) z 4
(C0 + 4 ) z1
+
+
CF
1 z1
CF
1 z1
3

C0 z 4
1 z 4 + 2 z 4 + 3 z 4 + 4 z1
.
+
1
C F 1 z 4
C F (1 z1 )
(16)

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WANG et al.: 5.4-mW 180-cm TRANSMISSION DISTANCE 2.5-Mb/s ADVANCED TECHNIQUES-BASED NOVEL IBC RECEIVER ANALOG FRONT END

Fig. 14.

Nonideal case with output referred noise at [n 2/4].

Considering the s domain

Fig. 15.

Topology of conventional threshold comparison-based RFE.

H (s)
will be




1
C0 1 4 sT
C1 2 kT
2
=
V
=
(20)
1
switch
CF
sT
CF
C1

4 1 



1 1 4 sT +2 1 24 sT + 3 1 34 st +4 (1sT )
2
+
. where Vswitch is the output referred switch noise. OP-amp
C F sT
contributes the second part of the output referred noise
(17)

2
C F + 24 C1
2
VOP =
Va2 .
(21)
If the oversampling rate is very large, it gives
CF


Then the total output referred noise in both phases of one

C0 1 + 14 (1 + 2 + 3 + 4 )
H (s)
.
(18) branch is derived as
1
CF
4 sT


2

C F + 42 C1
C1 2 kT
2
2
Equation (18) shows an interesting result that the mismatch
Vo =
Va + 2
.
(22)
CF
CF
C1
introduced by the four capacitors is not accumulated, but
averaged by the value of the boosting rate instead. If the Given the sampling rate is boosted by n times, the output
sampling rate is boosted by n times, its general expression referred noise in n branches will be




becomes
C F + n2 C1 2 2
C1 2 kT


2
Vo = n
Va +2n
.
(23)
n
CF
CF
C1
i
1 + n1 i=1
C0
H (s)
.
(19) Based on (23), the contribution of OP-amp referring to output
1
CF
noise is little enlarged. However, the noise contributed by all
n sT
In conclusion, if there is no mismatch, the transmission switches of branches is the same as conventional one, because
function is the same as (6). As the mismatch is due to the C1 is n times smaller. Furthermore, small C1 and large C F
discrepancy in the relative sizes of the capacitors, its effect are beneficial to reduce the output noise.
on the circuit is negligible compared with the absolute value
mismatch in the RC integrator. Furthermore, increasing the
value of C F can also minimize the mismatch effectively.
3) Noise Analysis: Noise is another important parameter to
consider for this proposed technique. Noise of SC integrators
is attributable to three means: 1) sampling phase kT /C noise
of switches; 2) amplifying phase kT /C noise of switches; and
3) OP-amp noise. We also take [n 2/4] time point as
an example and the equivalent circuit is shown in Fig. 14,
where branch 4 is in amplifying phase (branch 3 has finished
amplifying and settled). Rs denotes the resistance of switches.
Vns4 denotes the noise source introduced by switch resistors
in branch 4. Va denotes the noise caused by OP-amp. Over
the sampling phase, the switch noise is kT /Ci , where Ci is
the sampling capacitor in the i th branch. In the amplifying
phase, switches noise referring to the output of the integrator

IV. RFE C IRCUIT I MPLEMENTATION

As mentioned earlier, CTD-based RFE processes raw
signal in continuous time domain using a RC filter
and a hysteretic comparator. Large power consumption
(both static and dynamic) in hysteretic comparator, devices
mismatches, and absolute value variations together mean
that this method is not suitable for high-performance
IBC applications.
However, our proposed RFE uses a sampling rate boost
SC biquad filter instead of the conventional RC filter.
In addition, a matching integrator [17] is used rather than a
comparator, followed by weak signal integration and further
noise filtering. Both the SC filter and the integrator consume
little power and achieve reasonably high device matching.
A comparison between these two designs demonstrates the

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Fig. 16.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Proposed IBC receiver front end based on SC biquad filter with novel technique.

feasibility of the proposed structure and its superiority in IBC

receiver design. Specifically, this paper adopts the following
specifications and parameters: binary signaling with 0.5 quality
bandpass filter for ISI suppression, ONOFF keying modulation
with 2.5-MHz carrier at different data rates, 180-cm transmission distance (spanning the whole human body), and sampling
frequency for the proposed SC filter at 50 MHz with four times
sampling boost. The technology used is UMC 180 nm with
1.8 V supply.

The filter transfer function is given in [18, eq. (24)]

As/R3 C3
vo
= 2
vi
s + s(1/R5 C2 + 1/R5 C3 ) + (1/R3 +1/R2 )/R5 C2 C3
(24)
where A is the voltage gain. All the parameters based on the
quality factor Q and the center frequency f o can be calculated
as follows: first choose a value of C2 , and define k = 2 f 0 C3 ,
let C2 = C3 , R3 = 1/Ak, R4 = 1/k(2QA), R5 = 2Q/k. In this
design, f0 and Q are, respectively, 2.5 MHz and 0.5.

A. Conventional IBC Receiver Front End

The architecture of a conventional IBC RFE is shown
in Fig. 15. The bandpass filter in the preamplifier module has
three functions: 1) filtering the out-band noise introduced by
the human body; 2) filtering the unknown dc offset arisen
by the different reference voltages between TX, body and
receiver; and 3) reducing the ISI problem. A bandpass filter
followed by a closed loop amplifier is used to decrease
the sensitivity requirement of the comparator. A hysteretic
comparator is employed to recover the signal back to its binary
values.

B. Proposed Four-Time Boost SC Filter RFE

The architecture of proposed IBC RFE is shown in Fig. 16.
In this paper, the novel IBC RFE has three main modules:
the off-chip impedance matching network (P1 module),
the on-chip sampling rate boost technique based SC
biquad filter (P2 module) and the matched SC integrator
(P3 module). In P2, the signal is injected into port Vin , and
Vout denotes the output port of this stage. The ports with
the same names in P2 are connected together. First, using
the novel sampling rate boost technique makes it possible

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WANG et al.: 5.4-mW 180-cm TRANSMISSION DISTANCE 2.5-Mb/s ADVANCED TECHNIQUES-BASED NOVEL IBC RECEIVER ANALOG FRONT END

for the SC circuit to work at high frequency ensured by the

oversampling ratio. Second, the SC biquad filter replaces
the conventional RC bandpass filter effectively increasing
matching quality and minimizing ISI. Third, the weak
received signal after the SC biquad filter will be amplified to
supply rail level and will then be recovered to binary values
by a matched integrator based on the proposed sampling boost
technique along with greatly decreased power consumption
compared with the hysteretic comparator. The behavior and
hence the feasibility of each module (P1 P4) are proved
by transient simulation. For realistic simulation, the input raw
signal is obtained directly from in situ measurements.
A conventional biquad SC filter was discussed in [19].
Its transmission function can be expressed as
H (s) =

(K 2 s 2 + K 1 s + K 0 )
Vout (s)
=
Vin (s)
s 2 + Q0 s + 02

Fig. 17.

Rail-to-rail input, class AB output, constant gm OP-amp.

TABLE II
OP-A MP PARAMETERS

(25)

where 0 denotes the center angular frequency,

K 0 , K 1 , and K 2 decide the location of zeros and gain,
and Q is the quality factor. Then combining this structure
with the proposed oversampling technique, a novel four-time
sampling biquad filter is shown in Fig. 16.
In Fig. 16, based on (5) and (7), the expressions at nodes
V1 and Vout are as follows:
V1 =

C1
C F a1

1 z 4
1

Vout = a3 Vin

Vin

C1
C F a2

1 z 4
1

Vout

(26)

a5 CCF2 z 4 V1
1

C2
C F a4

1 z 4
1

Vin +

1 z 4
1

C2
C F a6 Vout

1 z 4
(27)
1

and then
H (s) =

Vout
Vin

4 C 2 a4
F
T

4a1 a5 C 1
F
T

 C2
C
4 C a6
4a2 a5 C 1
F
F
s2 +

T
T

s2a


C C
16a1 a5 C 1 C 2
F F
s+
2
T

C C
16a2 a5 C 1 C 2
F F
s+
2
T

C2
CF

C2
CF

(28)
where T is the sampling frequency and the values of a1 , a2 ,
a3 , a4 , a5 , and a6 can be calculated based on the equations
in Fig. 16.
The four-phase nonoverlap clocks are generated with
LeCroy arbitrary signal generator in this paper. The in-phase
and the 90 out-of-phase 50-MHz clocks are buffered with
tapered inverter chains on chip to generate the nonoverlap
gaps, as shown in Fig. 16. For higher than four times sampling
rate boost cases, the interleaved clocks can be easily realized
with a cascaded ring oscillator [20]. The details will not be
discussed in this paper.
For wearable and wireless sensor networks, energy harvesting could be used for obvious benefits and for bringing IBC
into more practical applications. Suitable energy harvesters are
discussed in [21] and [22]. In this paper, our aim is to prove the
feasibility of the proposed SC technique based on impedance

Fig. 18.

AC response for two bandpass filters.

matching network. The problem of the power source is not an

issue here.
C. Postlayout Simulation Results
As most wearable devices are powered with battery, a high
efficiency high SNR amplifier with rail-to-rail input and
class AB output is adopted [23]. Its structure is shown in
Fig. 17. The postlayout simulation results for the amplifier are
shown in Table II. To make a fair comparison, the OP-amps
used in these two RFEs are exactly the same.
A postlayout ac signal response simulation of the proposed
SC filter in comparison with that of the conventional RC filter
is shown in Fig. 18. It can be observed that the accuracy is
increased by 8.8% with the proposed filter technique.
The matched integrator module, which has been discussed
in Fig. 10, is utilized to amplify the weak received signal to
the supply rail level. To further illustrate the superiority of the

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10

Fig. 19.

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

DC transient with proposed and conventional SC integrator.

Fig. 22.

Measurement setup with hand-to-hand touching.

Fig. 23.

Transient waveform of proposed IBC RFE.

Fig. 20. Microphotograph of proposed (left) and conventional (right) RFEs.

TABLE III
R ECEIVER F RONT E ND M EASUREMENT

Fig. 21.

Measurement test boards of TX and RX.

proposed sampling boost technique, a postlayout simulation

with 20-mV dc input for this integrator is shown in Fig. 19.
By the use of the proposed technique, the integration is
more accurate and closer to its ideal integration result. Even
though both of these two designs in Fig. 19 employ the same
OP-amp, the proposed technique has been less affected by the
nonidealities of the amplifier.
V. IBC C HIP M EASUREMENT
The two RFEs were fabricated in a 0.18-m CMOS process
and the chip microphotographs are shown in Fig. 20. The core
area of the proposed RFE is 0.706 mm2 , and the conventional
RFE is 0.464 mm2 . The measurement test board is shown
in Fig. 21. The TX on the left hand side is a battery powered
AD9854. It generates signals with different amplitudes and
frequencies. On the right-hand side is the testing PCB board
of the IBC RFE chip with off-chip matching network and
regulators.

A subject with two-hand span of approximately 180 cm

was holding the electrodes (TX end and RX end), as shown
in Fig. 22. During transmission, an oscilloscope and a logic
analyzer were used to detect and measure the transmission
performance. The transient waveform is shown in Fig. 23. The
transmitted signal is 2.5 Mb/s with 2.5-MHz carrier, 1.2 V
amplitude. Before recovery, the raw signal is weak with a
range of 40 mV and very noisy, and after processing by the
proposed IBC RFE, the signal is recovered fully and noise
free.
BER is an important specification to quantify the reliability
of a communication system. Curves of BER versus different data rates with 180-cm transmission distance are shown

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11

TABLE IV
PARAMETERS C OMPARISON

DFOM can identify a better all-round design considering

BER, power, transmission distance, and data rate together,
the parameters that play significant roles in IBC design.
It indicates how much energy per meter and per bit is used in
units of fJ/(m bit) along with the achieved BER.
Using the DFOM as a figure for comparison, the proposed
SCF RFE outperforms all other referred designs with only
0.12 fJ/(m bit), validating the feasibility and the promising
role the new proposed technique can take in future IBC development.
Fig. 24.

Fig. 25.

BER comparison versus different data rates without matching.

BER comparison versus different data rates with matching.

in Figs. 24 and 25. The measurement results prove that by

introducing the matching network, the minimum BER can
be enhanced by nearly one order of magnitude, and the new
RFE can reach 1e-7 at 2.5 Mb/s, which is much less than
that found in the conventional RFE with 3e-7. A functional
summary of the proposed RFE is shown in Table III and a
comparison with other similar designs is shown in Table IV.
To make a reasonable comparison and stress the importance of
the transmission distance, a distance-figure-of-merit (DFOM)
is defined, which is calculated as
DFOM =

BER Power
.
Distance Data Rate

(29)

VI. C ONCLUSION
This paper has proposed a new approach to deal with
body communication channel modeling based on TL theory.
A matching network was designed to optimize the transmission S21 parameter, which plays a significant role in IBC
receiver design. Furthermore, a new sampling rate boosting
technique has been proposed and applied to a SC filter to
increase its operation frequency and accuracy. An IBC RFE
based on the proposed techniques, together with one based
on the conventional threshold comparison method, has been
implemented in a 0.18-m process. Postlayout simulation
results and chip measurement results are given, which show a
superior performance with the proposed RFE over other similar designs. Finally, these results also suggest that the proposed
arbitrary sampling rate boosting technique is beneficial not
only in IBC design but also in other related SC circuits designs
demanding high speed or high accuracy, such as deltasigma
modulators and biomedical sensors.
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Hao Wang (S13) was born in Jilin, China.

He received the bachelors degree from the
Department of Information Science and Electronic
Engineering, Zhejiang University, Hangzhou, China,
in 2010. He is currently pursuing the Ph.D. degree in
electronic engineering from the Chinese University
of Hong Kong (CUHK), Hong Kong.
He is currently with the ASIC Laboratory,
Department of Electronic Engineering, CUHK. He is
also with the Mixed-Signal Biomedical Integrated
Circuit Group. His current research interests include
mixed-signal biomedical integrated circuits design, field-programmable gate
array, and digital communication system design.

Xian Tang (S08M14) received the bachelors

degree in electronic science and technology from
the Huazhong University of Science and Technology,
Wuhan, China, in 2007, and the Ph.D. degree in
electronic engineering from the Chinese University
of Hong Kong, Hong Kong, in 2013.
She was an International Visiting Student with
the University of Toronto, Toronto, ON, Canada, in
2011. She is currently an Assistant Professor with
the Division of Information Science and Technology,
Graduate School at Shenzhen, Tsinghua University,
Shenzhen, China. Her current research interests include CMOS analog/mixedsignal integrated circuits design, in particular, pipelined analog-to-digital
converters, temperature sensors, and power management integrated circuits.
Dr. Tang was a recipient of the Global Scholarship Program for Research
Excellence-CNOOC Grants 20102011 from the Chinese University of
Hong Kong in 2010, and the Student Travel Grant Award from the IEEE SolidState Society and the International Solid-State Circuits Conference in 2012.

Chiu Sing Choy received the B.Sc., M.Sc., and

Ph.D. degrees in electrical and electronics engineering from the University of Manchester, Manchester,
U.K., in 1983, 1984, and 1987, respectively.
He spent a year with Ferranti Microelectronics, Oldham, U.K., where he participated in
application-specified integrated circuit technology
(ASIC) research. In 1986, he joined the Department
of Electronic Engineering, Chinese University of
Hong Kong, Hong Kong, where he is currently
a Professor. His current research interests include
network-on-chip, body area network, structured ASIC, OFDM-UWB digital
transceiver, real-time object detection, high-performance arithmetic units with
reduced precision, and IEEG signal processing and deep learning designs.
Prof. Choy is a fellow of The Hong Kong Institution of Engineers (HKIE).
He was the Chairperson of the Electronics Division in 2006 and 2007 and a
Council Member of HKIE.

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WANG et al.: 5.4-mW 180-cm TRANSMISSION DISTANCE 2.5-Mb/s ADVANCED TECHNIQUES-BASED NOVEL IBC RECEIVER ANALOG FRONT END

Ka Nang Leung (S02M03SM08) received

the B.Eng., M.Phil., and Ph.D. degrees from the
Department of Electronic and Computer Engineering, Hong Kong University of Science and Technology (HKUST), Hong Kong, all in electrical and
electronic engineering.
He was with HKUST in 2002, where he became
a Visiting Assistant Professor. After three years of
service with HKUST, he joined the Department
of Electronic Engineering, Chinese University of
Hong Kong, Hong Kong, in 2005, where he is
currently an Associate Professor. His current research interests include
power-management integrated circuits and low-voltage low-power analogue
integrated circuits.
Prof. Leung was the Chairman of the IEEE (Hong Kong) Electron
Device/Solid-State Circuit Joint Chapter in 2012. He serves on the Editorial
Board of Active and Passive Electronic Components, Hindawi Publishing
Corporation, Cairo, Egypt, and also serves as a paper reviewer in numerous
IEEE and the Institution of Engineering and Technology journals and international conferences. He is actively involved in the organization of several
IEEE international conferences.

13

Kong Pang Pun (S97M01SM09) received

the B.Eng. and M.Phil. degrees in electronics
engineering from the Chinese University of
Hong Kong (CUHK), Hong Kong, in 1995 and 1997,
respectively, and the Ph.D. degree in electrical and
computer engineering from the Instituto Superior
Tcnico, Technical University of Lisbon, Lisbon,
Portugal, in 2001.
He is currently an Associate Professor with the
Department of Electronic Engineering, CUHK.
His current research interests include CMOS
analog/mixed-signal integrated circuits design, in particular, high-energyefficiency analog-to-digital converters, ultralow voltage circuits, sensor
interface circuits, and complex signal processing circuits.
Dr. Pun received the Exemplary Teaching Awards from the Faculty of
Engineering, CUHK, in 2005, 2010, and 2013. He served as the Chairman
of the IEEE Hong Kong Joint-Chapter of Electron Devices and Solid-State
Circuits in 2008 and 2009. He was the General Co-Chair of the IEEE
International Conference on Electron Devices and Solid-State Circuits in
2008, and a member of the International Technical Committee of the IEEE
International Solid State Circuits Conference from 2008 to 2012. He will be
a Co-Guest Editor of the IEEE J OURNAL ON E MERGING AND S ELECTED
T OPICS IN C IRCUITS AND S YSTEMS 2015 Special Issue on Next-Generation
Delta-Sigma Converters.