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Objective:
To verify the AND gate embedded into an IC chip by using Digital Logic
Training System
Apparatus:
1 Digital Logic Training System (including bread board)
2 Connecting wires
3 7408 IC chip
Procedure:
Insert the given IC chip in bread board such that the legs on one side of IC
are inserted in row of one block of bread board, and the legs on other side
are inserted in row of adjacent block of the bread board. Read the number of
given IC before inserting it into the bread board. The number tells you that
which type of gate is embedded in the corresponding IC. After inserting the
bread board, connect the 7th terminal of IC by using a connecting wire with
the ground port of digital logic training system apparatus. Connect the 14th
terminal of IC with 5V power supply. Input voltage at 1st and 2nd terminal of IC
chip. Take output by connecting the 3rd terminal with output slot of
apparatus. If you are verifying NOT gate then only one input is needed at 1 st
terminal and output is taken from 2nd terminal of IC. ON/OF the switch to
verify the gate embedded into the given IC chip. Light on means that output
is 1 and light of means that output is 0. Repeat this procedure for AND,
NOT and OR gate.
Input 2
0
1
0
1
output
0
0
0
1
Conclusion:
After verifying the above truth table we conclude that the 7408 IC is
embedded with AND gate.
Experiment # 02
Objective:
To verify the OR gate embedded into an IC chip by using Digital Logic
Training System
Apparatus:
1 Digital Logic Training System (including bread board)
2 Connecting wires
3 7432 IC chip
What is an OR gate?
Procedure:
Insert the given IC chip in bread board such that the legs on one side of IC
are inserted in row of one block of bread board, and the legs on other side
are inserted in row of adjacent block of the bread board. Read the number of
given IC before inserting it into the bread board. The number tells you that
which type of gate is embedded in the corresponding IC. After inserting the
bread board, connect the 7th terminal of IC by using a connecting wire with
the ground port of digital logic training system apparatus. Connect the 14th
terminal of IC with 5V power supply. Input voltage at 1st and 2nd terminal of IC
chip. Take output by connecting the 3rd terminal with output slot of
apparatus. If you are verifying NOT gate then only one input is needed at 1 st
terminal and output is taken from 2nd terminal of IC. ON/OF the switch to
verify the gate embedded into the given IC chip. Light on means that output
is 1 and light of means that output is 0. Repeat this procedure for AND,
NOT and OR gate.
Input 2
0
1
0
1
output
0
1
1
1
Conclusion:
After verifying the above truth table we conclude that the 7432 IC is
embedded with OR gate.
Experiment # 03
Objective:
To verify the NOT gate embedded into an IC chip by using Digital Logic
Training System
Apparatus:
1 Digital Logic Training System (including bread board)
2 Connecting wires
3 7404 IC chip
Procedure:
Insert the given IC chip in bread board such that the legs on one side of IC
are inserted in row of one block of bread board, and the legs on other side
are inserted in row of adjacent block of the bread board. Read the number of
given IC before inserting it into the bread board. The number tells you that
which type of gate is embedded in the corresponding IC. After inserting the
bread board, connect the 7th terminal of IC by using a connecting wire with
the ground port of digital logic training system apparatus. Connect the 14th
terminal of IC with 5V power supply. Input voltage at 1st and 2nd terminal of IC
chip. Take output by connecting the 3rd terminal with output slot of
apparatus. If you are verifying NOT gate then only one input is needed at 1 st
terminal and output is taken from 2nd terminal of IC. ON/OF the switch to
verify the gate embedded into the given IC chip. Light on means that output
is 1 and light of means that output is 0. Repeat this procedure for AND,
NOT and OR gate.
output
1
0
Conclusion:
After verifying the above truth table we conclude that the 7432 IC is
embedded with OR gate.
Experiment # 04
Objective:
To verify the Exclusive-OR gate using NAND gates
Apparatus:
1 Digital Logic Training System (including bread board)
2 Connecting wires
3 IC chips embedded with NAND gates
particular logic. Binary coding is very useful to deal with gates. Here 1
represents the presence of a signal and 0 represents the absence of a
signal. Exclusive OR gate work on the following principle:
Output is 1 if and only if inputs are different from each other, otherwise
output is 0.
Procedure:
Arrange the given ICs, embedded with NAND gates, onto the bread board according
to arrangement as shown in the figure below.
Apply input at 1st and 2nd pin of gate # 03. Connect the 1st pin of gate # 01 with
input terminal A and 2nd pin of gate # 01 with output of gate # 03. Connect the 1 st
pin of gate # 02 with output of gate # 03 and 2 nd pin of gate # 02 with input
terminal B. Connect the 1st and 2nd pin of gate # 04 with output of gate # 01 and
gate # 02 respectively. Take the output from gate # 04. Apply different input
combinations from digital logic training system to verify the Exclusive OR gate.
Conclusion:
INPUT 2
1
0
1
0
OUTPUT
0
1
1
0
Experiment # 05
Objective:
To verify the logic of half adder using Exclusive-OR and AND gate
Apparatus:
1 Digital Logic Training System (including bread board)
2 Connecting wires
3 IC chips embedded with Exclusive-OR and AND gates
Half Adder is a combinational circuit, which takes 2 numbers (one bit binary)
from the user and then it add up these numbers using binary addition and
results in two outputs, one is for sum and other is for carry.
Procedure:
Arrange the given ICs, embedded with Exclusive-OR and AND gate, onto the
bread board according to arrangement as shown in the figure below.
Apply input at 1st and 2nd pin of both ICs. Ground the 7th pin of both ICs. Supply
voltage at 14th pin of both ICs. Apply different input combinations to verify the half
adder circuit.
Conclusion:
INPUT 2
1
0
1
0
Sum
0
1
1
0
Carry
1
0
0
0
Experiment # 06
Objective:
To verify the logic of full adder using 2 half adders and an OR gate
Apparatus:
1- Digital Logic Training System (including bread board)
2- Connecting wires
3- IC chips embedded with Exclusive-OR and AND and OR gates
Full Adder is a combinational circuit, which takes 3 numbers (one bit binary)
from the user and then it add up these numbers using binary addition and
results in two outputs, one is for sum and other is for carry.
Procedure:
Arrange the given ICs, embedded with Exclusive-OR and AND and OR gates,
onto the bread board according to arrangement as shown in the figure below.
Apply input1 and input2 on the 1 st and 2nd terminal of both Exclusive-OR and
AND gate. Apply the output of 1st Exclusive-OR gate at 1st terminal of 2nd
Exclusive-OR gate. Apply input3 at 2nd terminal of 2nd Exclusive-OR gate. Also
apply these inputs to 2nd AND gate. Apply the outputs of both AND gates to OR
gate. The output of 2nd Exclusive-OR gate is sum and output of OR gate is carry.
INPUT 2
0
0
1
1
0
0
1
1
INPUT 3
0
1
0
1
0
1
0
1
Carry
0
0
0
1
0
1
1
1
Sum
0
1
1
0
1
0
0
1
Conclusion:
After applying different combinations of inputs we conclude that the
arrangement of Exclusive-OR and AND and OR gates is corresponds to
full adder circuit.
Objective:
To verify the logic of full adder using 2 half adders and an OR gate
Apparatus:
1- Digital Logic Training System (including bread board)
2- Connecting wires
3- IC chips embedded with Exclusive-OR and AND and OR gates
Procedure:
Arrange the given ICs, embedded with Exclusive-OR and AND and OR gates,
onto the bread board according to arrangement as shown in the figure below.
Apply input1 and input2 on the 1 st and 2nd terminal of both Exclusive-OR and
AND gate. Apply the output of 1st Exclusive-OR gate at 1st terminal of 2nd
Exclusive-OR gate. Apply input3 at 2nd terminal of 2nd Exclusive-OR gate. Also
apply these inputs to 2nd AND gate. Apply the outputs of both AND gates to OR
gate. The output of 2nd Exclusive-OR gate is sum and output of OR gate is carry.
INPUT 2
INPUT 3
Carry
Sum
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
1
1
0
1
0
0
1
Conclusion:
After applying different combinations of inputs we conclude that the
arrangement of Exclusive-OR and AND and OR gates is corresponds to
full adder circuit.