Escolar Documentos
Profissional Documentos
Cultura Documentos
AND IC PACKAGES
PRESENTED AT:
FEBRUARY 11, 2003
SCV EMC SOCIETY MEETING
SANTA CLARA, CALIFORNIA
PRESENTER LEE RITCHEY
COPYRIGHT, FEBRUARY 2003 SPEEDING EDGE
SLIDE # 1
SLIDE # 2
SLIDE # 3
SLIDE # 4
SLIDE # 5
SLIDE # 6
VCC
VCC
PACKAGE
INDUCTANCE
PACKAGE
INDUCTANCE
VOLTAGE SPIKE
POWER SYSTEM
CAPACITANCE
PACKAGE
INDUCTANCE
LOAD
CAPACITANCE
CURRENT FLOW
LOAD
CAPACITANCE
POWER SYSTEM
CAPACITANCE
PACKAGE
INDUCTANCE
CURRENT FLOW
Voltage spikes are developed across the package inductances and are seen as Vcc and Ground bounce. Quiet outputs will move with the same
waveform as the Vcc or Ground bounce. Note that both power terminals of the semiconductor die move in either case.
SLIDE # 7
SLIDE # 8
Passive
Receiver
Equivalent circuit at To
Zout = 25 ohms
Vout = 5V
Rs = 25 ohms
VBENCH = V x Zout/(Zout+Z0)
Equivalent circuit at
To plus 4 nSEC
Comment: Simple Series Terminated Transmission Line
8.000 volts
Z0
Transmission Line
Input
Zst
Zout
Transmission Line
Output
Zout
1 V/div
0.0 volts
-1.000 volts
0.000ns
2 nsec/div
20.000ns
SLIDE # 9
VBENCH
Z0
Spectrum Analyzer
Zout = 25 ohms
Vout = 5V
Passive
Receiver
Rs = 25 ohms
OSCILLOSCOPE
Design file: TF15TL2.TLN
Des igner: Lee Ritchey
B oardS im /LineS im , HyperLynx
Com m ent: 50 OHM S E RIE S TE RM INA TE D TRA NS M IS S ION LINE 12" LONG
0mA
7.000
7mA
0 ns
uV/m
Probe 1:RS(A0).2
Probe 5:RP(B0).1
Probe 6:RP(B0).1
6.000
100 ns
5.000
4.000
Volta ge -V-
uV/m
3.000
2.000
1.000
0.000
-1.000
-2.000
-3.000
0.000
uV/m
0
500.000 MHz
1.000 GHz
10.000
20.000
30.000
Tim e (ns )
40.000
50.000
SLIDE # 10
FREQUENCY COMPONENTS IN
SWITCHING WAVEFORM
The highest frequency in the waveform is
determined by the rise time of the switching
edge.
The lowest frequency in the waveform is
determined by the length of the transmission
line being driven.
The clock rate is not reflected in the spectrum
of the current drawn from Vcc or Vdd.
It is these frequencies that make up most EMI
spectra.
Speeding Edge, Spring 2003 Copyright February 2003 by Speeding Edge
SLIDE # 11
SLIDE # 12
Spectrum Analyzer
100 ns
+30dBuV/m
+10dBuV/m
0
500.000 MHz
1.000 GHz
SLIDE # 13
SLIDE # 14
6 LAYER PCMCIA PCB SHOWING SIGNAL LAYERS FILLED WITH POWER PLANES
Power plane capacitance without fill, 500 pF. with fill 4100 pF.
SLIDE # 15
40
35
CISPRB LIMIT
EMISSIONS (dbuV/M)
30
25
20
15
10
FREQUENCY (Mhz)
SLIDE # 16
1000
900
800
700
600
550
500
450
425
400
375
350
325
300
275
250
225
200
180
160
150
140
130
120
110
80.2
80
60
50
40
30
SLIDE # 17
4.6 m V
3.9m V
E3
17.7 m V
8.7 m V
J2
11.0 m V
12.1 m V
P2
17.3 m V
15.4 m V
B6
3.6 m V
5.2 m V
G6
9.2 m V
10.7 m V
L 10
13.1 m V
14.7 m V
P2
17.3 m V
15.4 m V
C 12
2.2 m V
6.0 m V
H 12
10.2 m V
11.9 m V
L 20
13.1 m V
14.7 m V
P 10
14.3 m V
15.5 m V
G N D R E F , P IN 95
V cc R E F , P IN 100
Ig nd = 25 A
Icc = 25 A
D E V IC E
+ 5V
C 17
4.0 m V
6.4 m V
G 17
9.8 m V
11.6 m V
K EY
GROUND
B 21
5.6 m V
5.4 m V
F 21
9.3 m V
10.7 m V
L 20
13.1 m V
14.7 m V
P 20
14.1 m V
15.7 m V
A24
6.2 m V
4.4 m V
E 24
8.8 m V
8.6 m V
J24
12.9 m V
13.2 m V
P 24
13.8 m V
15.6 m V
IR D R O P P R O F IL E F O R 6 L AY E R T T L P C B .
15"
AL L L AY E R S , 1 O Z . C O P P E R .
approxim ately 15 m V /12.5A = 1.2 m illiohm s!
THE CONDUCTIVITY OF 1 OUNCE COPPER PLANES IS SO LOW THAT IT CAN BE IGNORED FOR ALL BUT
THE HIGHEST CURRENT PCBs. 2 OUNCE COPPER PLANES ARE NOT NECESSARY IN ANY, BUT THE
VERY HIGHEST POWER APPLICATIONS.
SLIDE # 18
SLIDE # 19
SLIDE # 20
VCC
VCC
PACKAGE
INDUCTANCE
PACKAGE
INDUCTANCE
VOLTAGE SPIKE
POWER SYSTEM
CAPACITANCE
PACKAGE
INDUCTANCE
LOAD
CAPACITANCE
CURRENT FLOW
LOAD
CAPACITANCE
POWER SYSTEM
CAPACITANCE
PACKAGE
INDUCTANCE
CURRENT FLOW
Voltage spikes are developed across the package inductances and are seen as Vcc and Ground bounce. Quiet outputs will move with the same
waveform as the Vcc or Ground bounce. Note that both power terminals of the semiconductor die move in either case.
SLIDE # 21
di
VL = L
dt
As edge rate increases (rise or fall time decreases), delta t
decreases and VL goes up. With die shrinks, delta t goes
down at the same time that delta i goes up, causing very
large voltage transients in power supply leads.
Speeding Edge, Spring 2003 Copyright February 2003 by Speeding Edge
SLIDE # 22
SLIDE # 23
3.2 - 10.2 nH
3.4 - 13.7 nH
4.4 - 21.7 nH
14 pin SOIC
20 pin SOIC
2.6 - 3.6 nH
4.9 - 8.5 nH
40 pin TAB
44 pin QFP
1.2 - 2.5 nH
6.07 - 7.06 nH
20 pin PLCC
28 pin PLCC
44 pin PLCC
68 pin PLCC
3.5 - 6.3 nH
3.7 - 7.8 nH
4.3 - 6.1 nH
5.3 - 8.9 nH
.15 - 5.7 nH
.13 - 5.1 nH
.5 - 4.75 nH
.2 - 5.8 nH
Lamson, Michael, Packaging Takes Center Stage in IC Design Process Electronic Design, June 8, 1998.
Shear, David Ground Bounce Tests Revisited EDN, April 1993.
SLIDE # 24
Vcc/Vdd
NOTE: IC MUST BE
MOUNTED ON A TEST
PCB WITH PROPERLY
DESIGNED POWER
SUPPLY BYPASSING
Vcc
PACKAGE
INDUCTANCE
INTEGRATED
CIRCUIT
PACKAGE
DATA PATTERN
GENERATOR SET TO
DRIVE BUS FROM ALL
ZERO TO ALL ONE
AND BACK
WIDEST
OUTPUT BUS
INTEGRATED
CIRCUIT DIE
GND
PACKAGE
INDUCTANCE
50 OHM TRANSMISSION
LINES
SLIDE # 25
SLIDE # 26
SLIDE # 27
CONCLUSIONS
Vcc and Ground bounce are caused by switching
transients.
They appear due to high package lead inductances or
inadequate power system decoupling or both.
Worst case Vcc and Ground bounce occurs when all
members of the largest bus switch from one logic state
to the other simultaneously.
Little of the bounce is developed in power planes.
The methods for managing these transient problems
are straight forward and well documented.
SLIDE # 28
WAYS TO CONTACT ME
Lee Ritchey- 707-568-3983
FAX- 707-568-3504
E-mail- leeritchey@earthlink.net
www.speedingedge.com
Most effective method is to send me an E-mail with
your question.
Second most effective is a FAX.
SLIDE # 29
SLIDE # 30
52.
SLIDE # 31