TRANSLATING VCD/EVCD

VECTOR DATA TO ATE

WITH VTRAN

Source III, Inc.

www.sourceiii.com

Background:
During the creation, debug and validation of
large IC designs, it is common to produce large
quantities of simulation data files these are often
referred to as functional vectors. They supplement the
ATPG vectors which provide coverage.
The Problem:
One of the challenging tasks in the Design-toTest flow is translating simulation vector files, typically
in VCD or EVCD format to test programs ready to run
on ATE.

VCD File

EVCD File

$timescale
1ps
$end
$scope module test_fed $end
$var wire
$var wire
$var wire
$var wire
$var wire
$var wire
.......
$upscope $end

1
1
1
4
1
1

!
"
#
$
%
&

$enddefinitions $end
#0
$dumpvars
0&
x%
bxxxx $
x#
x"
0!
........
$end
#4879
0"
#5000
1"
#5606
1#
b0011 $
#7060
1A
#10000
0+
0/
1*
........

p_mrdy_ $end
p_mintr_ $end
p_tclk $end
p_rxd [3:0] $end
p_rclk $end
p_crs $end

$timescale
1 ns
$end
$scope module
$var port
$var port
$var port
$var port
$var port
$var port
$var port
$var port
. . . . . .
$upscope $end

top $end
1 !
clki $end
1 "
clk2x $end
1 #
vcxo_ctrl $end
1 $
bclko $end
1 %
test $end
1 &
bopt $end
[3:0] A
devid $end
1 (
dsp_only $end

$enddefinitions $end
#0
$dumpports
pa 6 6 !
pX 6 6 "
pX 6 6 #
pX 6 6 $
pa 6 6 %
pb 6 6 &
pXXXX 6666 6666 A
pa 6 6 (
$end
#1
pT 0 0 "
pD 6 0 )
#5
pD 6 0 %
pU 0 6 &
pDDDD 5555 0000 A
pD 6 0 (
pH 0 0 0
pD 6 0 4
........

Flow 1: event-based (VCD/EVCD) data to ATE

Simulator

VCD
EVCD

Translator

ATE
Test Program

Event-based vector characteristics

Event entry when any signal transitions
No signal direction information for VCD
Timing is embedded in event data

Translation requirements:
Cyclizing Required (convert event-based to cycle-based)
State character translations
Identify/Specify Timing
Determine Signal Direction
Bidirectional Signal I/O data separation
Significant User input required
4

VCD/EVCD-to-ATE VTRAN FLOW

(errors)

VTRAN

Simulation

VCD/
EVCD

Cyclize vectors
State Trans
Define Timing
Signal Direction
Masking
other processing

Virtual
Test Program
Verification

VTRAN
ReadBack
ATE-to-Testbench

ATE Test
Program &
Timing

Verilog
Verification
Testbench

OK ?

ATE

Verification
Simulation

1. Simulation of final design generates VCD/EVCD file.

2. VTRAN performs cyclization, state mapping, makskng and other optional processing to generate ATE test program
3. In Virtual Test Program Verification, VTRAN ReadBack translates ATE test program to verification testbench.
4. Verification Simulation verifies test program can be run with varying parameter corners.
5. If OK, then ATE test program is ready for tester.
6. If errors, then correlate to design or adjust VTRAN parameters.

VTRAN Translating vcd/evcd to ATE

Information Required:
The names of all signals to be translated and their direction (Input, Output, Bidirect).
Be sure spelling exactly matches vcd/evcd spelling. Used in VTRAN command file,
for example, with:
Inputs clk, signalA, signalB, . . . . ;
Bidirects bidiA, bidiB, . . . . ;
Outputs po1. po2, po3, . . . .;
....
If multiple signals have the same node name, must use hierarchical name. For
example:

Inputs top.module1.clk, top.module1.signalA, . . . . ;

Cycle time and sample points in each cycle for each signal where state data should
be extracted for the cycle. Used in VTRAN command file, for example, with:
ALIGN_TO_CYCLE 200 all_inputs @ 10, all_outputs @ 195, clk @ 100;

ALIGN_TO_SIGNAL ref_clk 0->1 SAMPLE=all_inputs @ 10,

SAMPLE= all_outputs @ 95 ;

VTRAN Translating vcd/evcd to ATE:

Information Required (continued):
Method to determine direction of vector data in each cycle for bidirectional signals
(not necessary for evcd files since they have data direction information). This is used
in the VTRAN command file, for example, with:
BIDIRECT_CONTROL bidiA = input when ctl = 0;
BIDIRECT_CONTROL bibiB = output when ctl = 0 ;

Desired cycle time, signal timing and waveforms for output (ATE) file. This is used
in the VTRAN command file, for example, as:
CYCLE 200 ;
PINTYPE NRZ * @ 0 ;
PINTYPE RZ clk @ 20, 240 ;
PINTYPE STB * @ 195 ;
NOTE that if there is more than one set of CYCLE time and signal timing in the file,
you will need the timing information for each timeset in the file.

VTRAN cyclizing event vector data (vcd/evcd):

For single timeset data use ALIGN_TO_CYCLE / ALIGN_TO_STEP
- User specifies cycle time
- User specifies signal sample points
- User specifies timing for output file
- VTRAN translates event- to cycle-based
For single timeset data with irregular clock use ALIGN_TO_SIGNAL
- User specifies signal sample points
- User specifies timing for output file
- VTRAN translates event- to cycle-based
For multiple timeset data use TEMPLATE_CYCLIZATION
- User specifies cycle time, sample points, and
timing for each timeset
- User specifies matching criteria for each timeset
- VTRAN matches timeset criteria to event data
to select the appropriate timesets and performs
event- to cycle-based translation
For Multiple Time Domain data use multiple passes of VTRAN
- One pass per time domain
- Each pass only translates signals included in that domain
- Results in multiple output files for parallel loading on ATE (e.g. multi-port)
8

VTRAN Vector Processing

template_cyclization example:
TEMPLATE_CYCLIZATION
CYCLIZATION_SKEW = "0.5" ,
TERMINATE_ON_DEFAULTS = "20",
MATCH_REPORT = "designfile.rpt",
MATCH_TRACE_START = 1,
MATCH_TRACE_STOP = 8,
VIEW_OUTPUT = "designfile.view" ;
TIMESET SCAN_SHIFT
CYCLE 3.2;
PINTYPE NRZ * @ 0.5, 0.1;
PINTYPE -PRIMARY RZ cpref_clk @ 1.0, 2.0;
PINTYPE STB * @ 3.0, 3.1;
IDENTIFIER (scan_load=1)&(scan_enb=1) ;
ENDTIMESET;
TIMESET CAPTURE
CYCLE 6.4;
PINTYPE NRZ * @ .8, .1;
PINTYPE -PRIMARY RZ cpref_clk @ 2.0, 4.5;
PINTYPE -PRIMARY -ACTIVE_ONLY RO ubf_clk @ 1.5, 4.8;
PINTYPE STB * @ 6.1, 6.2;
IDENTIFIER (scan_load=0)&(scan_enb=1) ;
ENDTIMESET;
TIMESET RUN
CYCLE 4.0;
WEIGHT 1 ;
SAMPLE_POINT all_inputs @ 2.5;
PINTYPE NRZ * @ .4, .1;
PINTYPE -PRIMARY RZ cpref_clk @ 2.0, 3.0;
PINTYPE -PRIMARY RO ubf_clk @ 1.0, 3.2;
PINTYPE STB * @ 3.5, 3.6;
IDENTIFIER scan_enb = 0 ;
ENDTIMESET;

Multiple Time Domain Translations

DEVICE SIMULATION VECTORS

CK
Domain A

CK
Domain B

CK
Domain C

cmdA.vtran

cmdB.vtran

cmdC.vtran

A.avc
A.dvc

B.avc
B.dvc

C.avc
C.dvc

3 VTRAN command
files.
Each contain signals
and timing for specific
domain.

Resulting 3 test
programs converted
to binary and loaded
with multi-port
feature.

Final Advantest 93000

test program.

10

Example VTRAN command script

OVF_BLOCK
BEGIN
{ Specify how to read input file }
orig_file = "sbc2.vcd";
SCRIPT_FORMAT verilog_vcd;
BIDIRECTS PAD_ICE_DATA[7:0];
INPUTS PAD_ICE_ADDR[15:0];
INPUTS PAD_ICE_EN_B;
BIDIRECTS PAD_PORTA;
BIDIRECTS PAD_PORTB[4:0];
OUTPUTS PAD_ICE_RST_O;
OUTPUTS PAD_ICE_IRQ_O;
INPUTS PAD_ICE_DATA[7:0];
INPUTS PAD_PORTB_ctl[4:0];
. . . .
PROC_BLOCK
BEGIN
{ Processing to be done on vectors }
cycle 100;
{10 MHz cycle}
BIDIRECT_CONTROL PAD_PORTA=input WHEN PAD_PORTA_ctl=1;
BIDIRECT_CONTROL PAD_ICE_DATA=input WHEN PAD_ICE_DATA_ctl=1;
BIDIRECT_CONTROL PAD_PORTB[4]=input WHEN PAD_PORTB_ctl[4]=1;
BIDIRECT_CONTROL PAD_PORTB[3]=input WHEN PAD_PORTB_ctl[3]=1;
. . . .

TVF_BLOCK
BEGIN
{ specify output file format }
tester_format HP93000 ,
-auto_group,
-DVC_OUTPUTS_FNZ,
XMODE = "ts1 3",
XMODE_MAP = "sbc2.map",
PIN_CONFIG_FILE = "sbc2.pin",
PINSCALE = "128",
TIME_STAMPS = "ON",
DVC_FILE = "sbc2.dvc"
REPEAT_THRESHOLD = "4"
;
TARGET_FILE = "sbc2.avc"; {output file }
END;
END;

ALIGN_TO_CYCLE 100, ALL_INPUTS @ 10, ALL_OUTPUTS @ 95 ,

PAD_XIN @ 40, PAD_XCIN @ 30;
PINTYPE
PINTYPE
PINTYPE
PINTYPE

NRZ * @ 10 ;
STB * @ 95 ;
RO PAD_XIN @ 30, 50;
SBC PAD_XCIN @ 20, 40;

STATE_TRANS outputs '0'->'L', '1'->'H', '-'->'X',

'x'->'X', 'z'->'X' 'Z'->'X';
STATE_TRANS pure_inputs 'X'->'0', 'x'->'0', 'z'->'Z';
STATE_TRANS bidir_inputs 'X'->'0', 'x'->'0', 'z'->'Z';
END;

11

Example VTRAN command script (auto_align option)

OVF_BLOCK
BEGIN
{ Specify how to read input file }
orig_file = "sbc2.vcd";
SCRIPT_FORMAT verilog_vcd;
BIDIRECTS PAD_ICE_DATA[7:0];
INPUTS PAD_ICE_ADDR[15:0];
INPUTS PAD_ICE_EN_B;
BIDIRECTS PAD_PORTA;
BIDIRECTS PAD_PORTB[4:0];
OUTPUTS PAD_ICE_RST_O;
OUTPUTS PAD_ICE_IRQ_O;
INPUTS PAD_ICE_DATA[7:0];
INPUTS PAD_PORTB_ctl[4:0];
. . . .
PROC_BLOCK
BEGIN
{ Processing to be done on vectors }
cycle 100;
{10 MHz cycle}
BIDIRECT_CONTROL PAD_PORTA=input WHEN PAD_PORTA_ctl=1;
BIDIRECT_CONTROL PAD_ICE_DATA=input WHEN PAD_ICE_DATA_ctl=1;
BIDIRECT_CONTROL PAD_PORTB[4]=input WHEN PAD_PORTB_ctl[4]=1;
BIDIRECT_CONTROL PAD_PORTB[3]=input WHEN PAD_PORTB_ctl[3]=1;
. . . .
PINTYPE
PINTYPE
PINTYPE
PINTYPE

TVF_BLOCK
BEGIN
{ specify output file format }
tester_format HP93000 ,
-auto_group,
-DVC_OUTPUTS_FNZ,
XMODE = "ts1 3",
XMODE_MAP = "sbc2.map",
PIN_CONFIG_FILE = "sbc2.pin",
PINSCALE = "128",
TIME_STAMPS = "ON",
DVC_FILE = "sbc2.dvc"
REPEAT_THRESHOLD = "4"
;
TARGET_FILE = "sbc2.avc"; {output file }
END;
END;

NRZ * @ 10 ;
STB * @ 95 ;
RO PAD_XIN @ 30, 50;
SBC PAD_XCIN @ 20, 40;

AUTO_ALIGN warnings 100 ;

STATE_TRANS outputs '0'->'L', '1'->'H', '-'->'X',
'x'->'X', 'z'->'X' 'Z'->'X';
STATE_TRANS pure_inputs 'X'->'0', 'x'->'0', 'z'->'Z';
STATE_TRANS bidir_inputs 'X'->'0', 'x'->'0', 'z'->'Z';
END;

12

VCAP Analysis Features:

Handles wide variety of event-based vector formats

VCD, EVCD
Nanosim, SpringSoft FSDB, Mentor Log files, tabular,
Checks for Max Delays
Analyses signal timing & behavior for single timeset
Checks for signal glitches
Illegal state checking
Checks for simultaneous transitions
Checks for output signal stability

Generate timing file for direct import into VTRAN

13