4 .

11 BLOQUES ARITMTICOS
Elena Valderrama
Universidad Autnoma de Barcelona

4 .1
Losbloquesaritmticosconstituyenunaparteimportanteencasocualquiercircuito
digital.
Estudiaremoscircuitoscapacesdeimplementarlas4operacionesbsicas:
1.SUMA
2 RESTA
2.RESTA
3.MULTIPLICACIN
4.DIVISIN

4 .1
1.Sumabinaria
Sumadorparalelo:Verlecciones2.2y2.3delasemana2.
xi

yi

n
n

acarreo0

Sumadorn+1
n bits

Sumador
1bit

acarreoOUT

acarreoIN
Full_Adder (FA)

zi
xn-1

acarreoOUT

yn-1

Sumador
1bit

zn-1

xn-2

Sumador
1bit

zn-2

x1

yn-2

y1

Sumador
1bit

z1

x0

y0

Sumador
1bit

acarreoIN

z0
3

4 .1
2.Restabinaria
Unrestadorbinariorealizaelclculo:
n
n

donde:

acarreo0:1bit
(habitualmente igual a 0)
(habitualmenteiguala0)

acarreo0

n+1
Restador
Restador
n bits

Cmorepresentamosunnmeronegativo?
, serepresentaporunnmeroden+1
p
p
SiD<0,D
bitsllamadoelcomplementoa2deD:

4 .1
2.Restabinaria
Algoritmomanual:

1 1 0 0

1 0 0 1

1 0 0 1

1 1 0 0

n pasos,encadapasocalculamos:
Elbitresta:
Elacarreohacialaetapa
siguiente:
g

4 .1
2.Restabinaria
Algoritmo1delaresta
acarreo(0)<=acarreo_inicial; (habitualmente 0)
for i in0ton1loop
in 0 to n 1 loop
d(i)<=(x(i)+y(i)+acarreo(i))mod2;
acarreo(i+1)<=sign(x(i) y(i) acarreo(i));
p;
end loop;
s(n)<=acarreo(n);

Algoritmo2delaresta
acarreo(0)<=acarreo_inical;; (habitualmente 0)
fori in0ton1loop
d(i)<=x(i)xor y(i)xor acarreo(i);
acarreo(i+1)<=
(not(x(i)) and y(i)) or (not(x(i)) and acarreo(i))
(not(x(i))andy(i))or(not(x(i))andacarreo(i))
or (y(i)and acarreo(i));
endloop;
s(n)<=acarreo(n);

4 .1
2.Restabinaria

Restador n+1
n bits

xi

acarreoOUT

yi

acarreo0

Restador
1bit

acarreoIN

Full_Substractor
((FS))
di
xn-1

dn=acarreoOUT

yn-1

xn-2

FS

FS

dn-1

dn-2

d(i)<=x(i)xor y(i)xor acarreo(i);

acarreo(i+1)<=
(not(x(i))andy(i))or(not(x(i))andacarreo(i))
or (y(i) and acarreo(i))
or(y(i)andacarreo(i))

x1

yn-2

y1

x0

y0

FS

FS

d1

d0

acarreoIN

4 .1
(Ejercicio)
ConstruiruncircuitoquecalculeD =x y (x,y den bits)ydevuelvaelvalordeD enla
representacin clsica de signo
representacinclsicade
signoymagnitud
y magnitud,,esdecir,comoD
es decir, como D =((1)
1)sign|D
|D|
Sugerencia:Calculaenparalelox y andy x yseleccionael|D|dependiendodelsignodex y.

4 .1
(Solucin del ejercicio)
(Solucindelejercicio)
ConstruiruncircuitoquecalculeD =x y (x,y den bits)ydevuelvaelvalordeD enla
p
g y
g
,
,
=(1)
( )sign|D|
| |
representacinclsicadesignoymagnitud,esdecir,comoD
Sugerencia:CalculaenparaleloX Y andY X yseleccionael|D|dependiendodelsignodeX Y.
x

subtract.
Restador

subtract.
Restador

d
d

d
d
0

sign

d
9

4 .1
3.Multiplicadorbinario
Unmultiplicadorrealizaelclculo:

donde:
Algoritmo1:

MayorvalordeP:

p0 =Xy
X 0;
p1 =Xy12;
p2 =Xy222;

pm1 =Xym12m1;
P =p0 +p1 +p2 ++pm1 .

P esunnmeroden+m bits
10

3.Multiplicadorbinario

4 .1

Algoritmo1:
p0 =Xy0;
p1 =Xy12;
p2 =Xy222;

pm1 =Xym12m11;
P =p0 +p1 +p2 ++pm1 .

Ej
Ejemplo:
l
101101
x1011

101101 p0
101101 p1
000000
000000
p2
101101 p3

111101111 P
11

3.Multiplicadorbinario

4 .1

p0 =Xy0;
p1 =Xy12;
p2 =Xy222;

pm1 =Xym12m1;
P =p0 +p1 +p2 ++pm1 .
Algoritmo2:Righttoleft algorithm
acc <=0;
fori in0tom1loop
acc <=acc +X*(2**i)*y(i);
endloop;
P<
P<=acc;
12

4.Divisorbinario

4 .1

DadosdosnmerosX eY naturales(X <Y),

dividirX entreY (X/Y )consisteencalcular
Q yyR talesque:
q
dosnmerosQ

Para calcular X/Y cuando X Y ser necesario

alinear previa y convenientemente los operandos.

13

4 .1

4.Divisorbinario
Algoritmodedivisinbinaria
r(0)<=x;
for i in1toploop
in 1 to p loop
d<=2*r(i1) y;
ifd<0thenq(i)<=0;r(i)<=2*r(i1);
else q(i) <=1;r(i)<
elseq(i)<
1; r(i) <=d;
d;
end if;
end loop;
Resultado:
Q =(q1 q2 qp1 qp)2p,
R =r
= rp2pp.

Ejemplo:X=21,Y =35,p =6
iteracin
0
1
2
3
4
5
6

r
21
7
14
28
21
7
14

1
0
0
1
1
0

7
21
7
7
21
7
<0

comentarios

D=4235=7
D=1435=21
D=2835=7
D=5635=21
D=4235=7
D=2835< 0

Q =[100110]2.2p =38/64 =[0,100110]2,

R =14/64 =[0,001110]2

14

4.Divisorbinario

4 .1

Algoritmodedivisinbinaria
r(0)<=x;
for i in1toploop
in 1 to p loop
d<=2*r(i1) y;
ifd<0thenq(i)<=0;r(i)<=2*r(i1);
else q(i) <=1;r(i)<
elseq(i)<
1; r(i) <=d;
d;
end if;
end loop;

15

4 .1
RESUMEN

Hemosvistounconjuntodecircuitoscapacesdeejecutarlasoperacionesaritmticas
bsicasdesuma,resta,multiplicacinydivisin.

Hemosintroducido,aunquemuybrevemente,larepresentacindenmerosnegativos
medianteelcomplementoa2.

16

4 .22 Short introduction to VHDL

Llus Ters
Instituto de Microelectrnica de Barcelona, IMB-CNM (CSIC)
Universitat Autnoma de Barcelona (UAB)

CONTENTS
1.
1
2.
3.
4
4.
5.
6.
7
7.

4 .2

Maingoals&Expectedlearning
M
i
l &E
t dl
i
BasicsonVHDLlexical&syntax
VHDLDesignUnits
VHDL Sequential Sentences (selection)
VHDLSequentialSentences(selection)
VHDLConcurrentSentences(selection)
VHDLusageformodelling,simulationandsynthesis
Summary

18

Main goals & Expected learning

4 .2

M i
Maingoals
l

VHDLsyntax,mainunitsandstructure
Fundamentalsonsequentialandconcurrentstatements
Processes
Componentinstances
Signalassignments
VHDLusage:modelling,simulationandsynthesis

Expectedlearning
BasicknowledgeaboutVHDLlanguageanditsusage(basedonexamplesalreadyseeninthiscourse)
BeabletoreadandunderstandsimpleVHDLcode
BeabletowritespecificportionsofVHDLcode
Understandtheroleofhardwarelanguagesindigitalsystemsdesign
19

4 .2

Basics on VHDL lexical & syntax

Lexicalelements:ReservedWords,Identifiers,Symbols,Literals
,
, y
,
Language Reserved Words
abs
array
bus
exit
if
new
open

access
assert
case
file
in
next
or

after
attribute
component
for
inout
nor
others

alias
begin
else
function
is
not
out

all
block
elsif
generate
label
null
process

and
body
end
generic
library
of
procedure

architecture
buffer
entity
guarded
nand
on
...

Identifiers to provide specific names to VHDL elements and objects

- Based on character set {az, AZ, 09, _}
- First character shall be alphabetical and _ at the end or two __ are forbidden
- Upper/lower-case are indifferent and reserved words are forbidden
Examples: COUNT, aBc, X, f123, VHDL, VH_DL, ABC, q1, Q0

Symbols

Literales

- 1 or 2 characters
Base
- operators, punctuation, comments, part of sent. 2#110_1010#
16#CA#
+ - * / ( ) . , : & < >
= 16#f.ff#e+2
| # ; -- => ** := /= >= <= <> Decimal
12 0 1E6

Character
a A @
String
Tiempo
110101

Physical
10 ns
2.2 V
50 pF
Bit String
XF0f B111_100

4 .2

Basics on VHDL lexical & syntax

VHDLObjects
j

constant
constant
constant
constant
t t

VHDLobjectisanylanguageelementabletocontainavalue
TypesofVHDLobjects:
Constant
Variable
Object definition:
<Object type> <identifier> : <data
Signal
File
PI : real := 3.1415927;
WordBits : natural := 8;
NumWords : natural := 1024;
T tBit : natural
TotBits
t
l := WordBits
W dBit * NumWords;
N W d

signal Clk : bit := 0;

...
Clk <=
< 1
1;

Signal declaration
& initialization

type> [:= Initial value];

variable Counter : integer :=0;

variable Increment : integer;

Variables
declaration

Increment
I
t := 2;
2
Counter := Counter + Increment;

Variables
V
i bl
assignment

Si
Signal
l assignment
i
t
file Estimuli : FileTypeName1 open read_mode is data.in;
file Dataout : FileTypeName2 open write_mode is data.out; 21

Basics on VHDL lexical & syntax

4 .2

VHDLDataTypes
TheVHDLisastronglytypedlanguage
Adatatypedefinesasetoffixedandstaticvalues
Anylanguageobjectbelongstoaspecificdatatype
Objectvaluesshallbelongtorelateddatatype
STANDARD package:
is (false, true);
boolean
Newdatatypescouldbeuserdefined
Predefined Types of VHDL

type
type bit is (0, 1);
type severity_level is (note, warning, error, failure);
type character is (NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS,
HT, LF, VT, FF, CR, SO, SI, DEL, DC1, DC2, DC3, DC4, DC5, NAK,
SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, , !, ,
#, $, %, &, , (, ), *, +, ,. -, ., /,
0,
0 , 1,
, 2,
, 3,
3 , 4,
, 5,
5 , 6,
6 , 7,
, 8,
8 , 9,
9 , :,
: , ;,
; , <,
,
=, >, ?, @, A, B, C, D, E, F, G, H, I,
J, K, L, M, N, O, P, Q, R, S, T, U, V,
W, X, Y, Z, [, \, ], ^, _, `, a, b, c,
d, e, f, g, h, i, j, k, l, m, n, o, p,
q, r, s, t, u, v, w, x, y, z, {, ...);
type integer is range -2.147.483.647 to 2.147.483.647;
type real is range -1.0e38 to 1.0e38;
/

22

Basics on VHDL lexical & syntax

4 .2

VHDLDataTypes
yp

TheVHDLisastronglytypedlanguage
Adatatypedefinesasetoffixedandstaticvalues
Any language object belongs to a specific data type
Anylanguageobjectbelongstoaspecificdatatype
Objectvaluesshallbelongtorelateddatatype
Newdatatypescouldbeuserdefined

type time is range 0 to 1e20

units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
h = 60 min;
hr
i
end units time;
23

4 .2

Basics on VHDL lexical & syntax

VHDLOperatorsandexpressions

Operatorsaresymbolsidentifyingspecificoperations
Types:arithmetic,logic,relationalandconcatenation
Operands:
Expressions:
Relational

Logic

Arithmetic

=
/=
<
<=
>
>=

and
or
nand
nor
xor
not

+
*
/
**
mod
rem
abs

Concatenation

&

Arithmetic
(-b + sqrt(b**2 - 4.0*a*c))/(2.0*a)

Relational
delay >= 20 ns
name < Smith

Logic
(a xor b) and not c;

Concatenation
BitSign & VectorValue

Expressionscouldbeassignedto:
p
g
Constants(const := expression;)
Variables(var := expression;) 24
Signals(sig <= expression;)

4 .2

VHDL Design Units

VHDLisorganizedondifferentDesignUnits:

Entity
Architecture
Package(declaration&body)
Configuration

Architecture
1

Architecture
n

Package
Declaration

Package
g
Body
Secund
dary

Architecture
2

Configuration
D l
Declaration
i

Prim
mary

Entity
Declaration

25

4 .2

VHDL Design Units

ENTITY

Likeablackboxjustdescribingexternalinterfaceforamodulewhile
hidingitsinternalarchitecture
Syntax:
Entity name (module name)

entity <id> is
[<generics>];
[<ports>];
p
[<declarations>];
[begin <sentences>];
end [entity] [<id>];

Generic parameters
Input/Output ports (electrical interface)
Global declarations (common to any potential architecture of this entity)
Passive sentences (common to any potential architecture of this entity)

entity MUX21 is
port( A
:
B
:
Ct l :
Ctrl
Z
:
end MUX21;

in
in
i
in
out

bit;
bit;
bit
bit;
bit;

A
B
Ctrl

MUX21

Z
26

4 .2

VHDL Design Units

ENTITY

Likeablackboxjustdescribingexternalinterfaceforamodulewhile
hidingitsinternalbehaviourandarchitecture
Syntax:
Entity name (module name)

entity <id> is
[<generics>];
[<ports>];
p
[<declarations>];
[begin <sentences>];
end [entity] [<id>];

Generic parameters
Input/Output ports (electrical interface)
Global declarations (common to any potential architecture of this entity)
Passive sentences (common to any potential architecture of this entity)

entity MUX21n
generic( n
port( A
B
Ctrl
Z
end MUX21;

is
: integer := 2);
: in bit_vector(n-1 downto 0);
: in bit_vector(n
bit vector(n-1
1 downto 0);
: in bit;
: out bit_vector(n-1 downto 0));

Bus size as generic parameter

A
B
Ctrl

n
n

MUX21

Z
27

4 .2

VHDL Design Units

ARCHITECTURE

DetailswhatisbehindanEntitywhiledescribingitsbehaviouratfunctional,
dataflow,structuralormixedlevels
MultipleArchitecturesfo asingleEntityarepossible
Syntax:
Architecture name
architectura <id> of <id_entity> is
[<declarations>];
begin
<concurrent sentences>;
end [architecture] [<id>];

E tit name
Entity
Signals, variables, components
Concurrent sentences:
Concurrent assignments
Instances to components
Processes
Blocks

28

4 .2

VHDL Design Units: Entity & Architectures

entity MUX21 is
port( A, B, Ctrl : in bit;
Z : out bit);
end MUX21;
architecture Functional of MUX21 is
begin
process(A, B, Ctrl)
begin
beg
if Ctrl = 0 then
Z <= A;
else
Z <= B;
end if;
end process;
end Functional;

A
B
Ctrl

MUX21
Z

entity MUX21n is
generic ( n: natural);
port( A
: in bit_vector(n-1 downto 0);
B
: in bit_vector(n-1 downto 0);
Ctrl : in bit;
Z
: out bit_vector(n-1 downto 0));
end MUX21;
architecture Functional of MUX21n is
begin
process(A, B, Ctrl)
begin
if Ctrl = 0 then
Z <= A;
;
else
Z <= B;
n
end if;
end process; A
n
end
d Functional;
F
ti
l B
MUX21n

Ctrl

29

VHDL Design Units : Entity & Architectures

entity MUX21 is
port( A
:
B
:
Ctrl :
Z
:
end MUX21;
;

in
i
in
in
out

bit;
i
bit;
bit;
bit;

architecture DataFlow of MUX21 is

signal Ctrl_n, N1, N2 : bit;
b i
begin
Ctrl_n <= not Ctrl;
N1
<= Ctrl_n and a;
N2
<= Ctrl and b;
Z
<= (N1 or N2);
end DataFlow;
Concurrent Statements

4 .2
architecture structural of MUX21 is
signal Ctrl_n, N1, N2 : bit;
component INV
port( Y : in bit;
Z : out bit);
end component;
component AND2
port(
p
( X,
, Y : in bit;
;
Z
: out bit);
end component;
component OR2
port( X, Y : in bit;
Z
: out bit);
end component;
begin
U0: INV port map (Ctrl, Ctr_n);
U1: AND2 port map (Ctrl_n, A, N1);
U2: AND2 port map (Ctrl, B, N2);
U3: OR2 port map (N1, N2, Z);
end structural;
30

4 .2

VHDL Design Units

PACKAGE

Usefulforcodereuseasitcouldcontaindefinitionsofdatatypes,functionsand
languageobjects(constants,variables,signalsorfiles)foritsuseondifferentcodes
Twounits:
P k
Package
name
Packagedeclaration package <identifier>
[<declarations>];
end [package] [<identifier>]

Declarations of:
Data types
Constants
Functions & procedures
Package name

Packagebody
g
y

package body <identifier>

[<Assignments and
Detailed definitions>];
end [package body] [<identifier>]

Packageusage
g
g
use <library>.<package name>.[<identifier> | all];

Assignments & definitions of:

Constants
Functions & procedures
Usual packages:
- STANDARD & TEXTIO
- Std_logic_1164
31
- Std_logic_arith

4 .2

VHDL Design Units

PACKAGE

VHDL constant object

package VSuP_Pack is

Constant Id.
Id

Constant
data type

Comment

-- Processor basic dimensions

constant ProcWordBits : integer; -- Processor word lenght (bits)
constant MemAdrBits : integer; -- Memory address lenght (bits)
constant CtrlBusNumBits : integer; -- Number of bits for control bus
constant StatusBusNumBits : integer; -- Number of bits for status and flags bus
constant ALUopNumBits : integer; -- Number of bits to especify the ALU operation code
constant OpCodeNumBits
p
: integer;
g
-- Number of bits to especify
p
y the instruction OpCode
p
constant Bus2zeros : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant string of 0s
constant Bus2ones : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant string of 1s
constant One : std_ulogic_vector (ProcWordBits-1 downto 0); -- constant value 1;
-- Mnemonics for ALU operations
constant NoOp,Add,Sub,IncL,IncR,DecL,DecR,AndL,
OrL,NotL,LSh,RRot,GoL,GoR,Out0,Out1 : std_ulogic_vector (ALUopNumBits-1 downto 0);
-- Processor instruction set OpCodes
constant
t t LDA, S
STA,MOV,SAV,CLR,SET,LAND,LNOT,LOR,SHIL,ROTR,
O S
C
S
O
O S
O
ADD,SUB,INC,DEC,CMP,BRZ,BRN,JMP,NOP,EOP : std_ulogic_vector (OpCodeNumBits-1 downto 0);
end package VSuP_Pack;

32

VHDL Design Units

Constant values definition.

4 .2

package
body VSuP_Pack is
PACKAGE
-- Processor basic dimensions
constant ProcWordBits : integer := 16; -- Processor word lenght (bits)
constant MemAdrBits : integer := 16; -- Memory address lenght (bits)
constant CtrlBusNumBits : integer := 25; -- Number of bits for control bus
constant StatusBusNumBits : integer := 5; -- Number of bits for status and flags bus
constant ALUopNumBits : integer := 4; -- Number of bits to especify the ALU operation code
constant OpCodeNumBits : integer := 5; -- Number of bits to especify the instruction OpCode
constant Bus2zeros : std_ulogic_vector (ProcWordBits-1 downto 0):= (others =>0);
constant Bus2ones : std_ulogic_vector (ProcWordBits-1 downto 0):= (others =>1);
g _vector (
(ProcWordBits-1 downto 0)
) := conv_std_logic
g _vector (
(1,
,
constant One : std_ulogic
ProcWordBits);
-- Mnemonics for ALU operations
-- No operation cycle
constant NoOp : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0000";
-- Addition: Out <- A + B;[C
B;[C,N,Z]
N Z]
constant Add : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0001";
-- Subtraction: Out <- A - B;[C,N,Z]
constant Sub : std_ulogic_vector (ALUopNumBits-1 downto 0) := "0010";
/
-- Put all
ll output bi
bits at '1':
1
Out <- "1...1";[N]
1
1 [ ]
constant Out1 : std_ulogic_vector (ALUopNumBits-1 downto 0) := "1111";
end package body VSuP_Pack;

33

VHDL Summary (part-I)

4 .2

Sessionsummary

BasicsonVHDLlexicalandsyntax
Languagelexicalelements
Objects(constant,variable,signalandfiles)
Objects (constant variable signal and files)
Datatypes,Operatorsandexpressions

VHDLdesignunits
EntityandArchitecture
Configuration
Package(declaration&body)
Package (declaration & body)

SimplifiedformalVHDLdesignunitsdescriptionsbutexamplebasedlearning

34

4 .33 Short introduction to VHDL

Llus Ters
Instituto de Microelectrnica de Barcelona, IMB-CNM (CSIC)
Universitat Autnoma de Barcelona (UAB)

(cont.)

VHDL Sentences (selected subset)

4 .3

Sequentialvs.ConcurrentSentences

Sequential
AlgorithmicsentenceslikeforSWlanguages(if, case, loop, exit, return, )
Interpretedsequentially Orderofsentencesisimportantfortheresults
Onlyusedinfunctions,proceduresandProcesses

Concurrent
Devotedtoexpresshardwarestructure(Hw componentsandblocksaredoingconcurrently)
andprocessesworkingsimultaneously
d
ki
i l
l
Somesequentialsentenceshaveitsequivalentconcurrentones
Selectedsentences:Process,Signalassignments,Componentsinstantiation
MainlyusedinArchitectures
Mainly used in Architectures

ConcurrenttoSequentialforsimulation
EachconcurrentstatementcouldbetranslatedtoitsequivalentProcess basedonsequential
statements.
Forsimulationpurposesalltheconcurrentstatementsaretranslatedtorelatedprocesses.
VHDLeventdrivensimulationwillmanagejustalotofprocesses.

36

VHDL Sentences (small selection)

4 .3

SequentialSentences

Wherearepossible?
process
begin
-- sequential
-- sentences
end process;

procedure P() is
begin
-- sequential
-- sentences
end P;

function F() return

begin
-- sequential
-- sentences
end F;

Whicharetheselectedsentences?

Variable&Signalassignments
Wait
Ifthenelseendif
Case
Loop,ExitandNext
Functions & Procedures
Functions&Procedures
Assertreportseverity
37

VHDL Sentences (small selection)

4 .3

SequentialSentences:VariableAssignment

Immediate replacementofvariablevalue.
Syntax:
[label:] <variable name> := <expression>;

Examples:
Var := 0;
Vector := 00011100;
string := Message is: ;
A := B;
B := my_function(3,databus)
C := my_function(4,adrbus)
my function(4 adrbus) + A;

38

4 .3

VHDL Sentences (small selection)

SequentialSentences:SignalAssignment

Projectsanewevent(value,time)onthesignaldriver.
Syntax:

t0

t1

ti

v0

v1

vi

[label:] <signal_name> <= [delay_type] <expression> {after <delay>};

Nextsentencesequenceswillexchangethevalues
betweensignalAandB:
Delaytypes:inertialortransport
Examples:
p

A <= B;
B <= A;

B <= A;
A <= B;

B1
B2
B3

B1 <= transport A after 10 ns;

B2 <= A after 10 ns;
B3 <= reject 5 ns A after 10 ns;

A
0

10

20

30

40

A <= 0, 1 after 10 ns, 0 after 15 ns, 1 after 20 ns, A

0 after 28 ns, 1 after 40 ns, 0 after 50 ns;
driver

50

60

70

((ns))

10

15

20

28

40

50

VHDL Sentences (small selection)

SequentialSentences:Wait

4 .3

Indicatesthepointwhereaprocessexecutionshallbesuspended,aswellasthe
Indicates
the point where a process execution shall be suspended as well as the
conditionsforitsreactivation.Morethanonewaitsentenceperprocessispossible.
Syntax:
[label:] wait [on <signal> {, ...}]
[until <boolean_expresion>]
[for <time_expresion>];

B i
Basicexamples:
l
process
begin
<sequential sentences>
wait;
end process;

Withoutreactivationcondition

process
begin
c <= a and b;
wait on a, b;
end process;

Sensibletoeventsonsignalsab

process
begin
Clock <= not Clock;
wait for 10 ns;
end process;

Suspends and fixes a time for reactivation 10ns

Suspendsandfixesatimeforreactivation10ns
process
begin
q <= d;
wait until Clock = 1;
end process;
40

Sensibletoeventsonsignals&condition=True

4 .3

VHDL Sentences (small selection)

SequentialSentences:Ifthenelseendif;

SelectsthegroupofsentencestoexecutedependingonaBooleancondition.
Syntax:
[label:] if <condicion> then
<sentencias secuenciales>
{elsif <condicion> then
<sentencias secuenciales}
[else
<sentencias secuenciales>]
end if [
[label];
]

Examples:
Latch: process begin
if load =1 then
Q <= D;
end if;
wait on load, D;
end process;

Latch

Process (A,
(A B
B, Ctrl)
Begin
if Ctrl = 0 then
Q <= A;
else
Q <= B;
end if;
end process;

Mux

Buffer Triestate
process
begin
if Enable =1 then
S lid <= Entrada;
Salida
d
else
Salida <= Z;
end if;
wait on Enable, Entrada;
end process;
41

VHDL Sentences (small selection)

4 .3

SequentialSentences:Case

Selectsthegroupofsentencestoexecute
dependingonaexpressionvalue.
Syntax:
Orofvalues:when00|01
Valuesrange:when5to12(integers)
Lastoption:whenothers

[label:] case <condition> is

{when <value> =>
<sequential sentences>;}
[when others =>
<sequential sentences>;]
end case [label];

type weekdays
t
kd
: (Monday,
(M d
T
Tuesday,
d
W d
Wednesday,
d
Th
Thursday,
d
F id
Friday,
S t d
Saturday,
S d )
Sunday);
type typeofday : (Workingday, Holiday);
Signal Day : Weekdays;
process
process
Signal Daytype : typeofday;
begin
begin
case ValEnt
V lE t is
i
case Day
D
i
is
when 0
=> Res := 5;
when Monday to Friday =>
when 1 | 2 | 8 => Res := ValEnt;
Daytype <= Workingday;
when 3 to 7
=> Res := ValEnt + 5;
when Saturday | Saunday =>
when others
=> Res := 0;
Daytype <= Holiday;
end case;
end case;
wait on ValEnt;
wait on Day;
end process;
end process;
42

Examples:

VHDL Sentences (small selection)

SequentialSentences:If&Case

PreviousexamplewithtwoProcess:
Mux
Latch

LatMux
A
B

C
D

4 .3

entity LatMux is
port(
Load
: in bit;
A B
A,
B, C
C, D : in bit;
Ctrl
: in bit_vector(0 to 1);
Y
: out bit);
end LatMux;
architecture TwoProc of LatMux is
Signal X : bit;
Concurrent Statements
begin
Mux: process (Ctrl, A, B, C, D);
begin
case Ctrl is
when 00 => X <= A;
when 01 => X <= B;
when 10 => X <= C;
when 11 => X <= D;
end case;
;
end process;

Sequential Statements

Ctrl
Load

Latch: process (Load, X);

begin
if Load=0 then
Y <= X;
end if;
end process;
end TwoProc;

43

VHDL Sentences (small selection)

4 .3

SequentialSentences:Loop

Sequentialsentencesintheloopregionarerepeatedforanumberoftimes.
Typesofloops:while,forandwithoutiterationscontrol(infiniteloop).
Syntax: [[label:]
abe :] [
[while
e <boolean
boo ea _co
condition>
d t o
| for
o <repetition
epet t o _co
control>]
t o ]

loop
<sequential sentences>}
end loop [label];
achitecture Functional of ParallelAdder is
begin
process (X, Y, Cin);
Examples:Fulladder
variable C : std_logic_vector(n downto 0);
variable tmp : std_logic;
variable I : integer;
entity ParallelAdder is
begin
g
generic (n : natural :=4 );
C(0) := Cin;
port ( X, Y : in
for I in 0 to n-1 loop
std_logic_vector(n-1 downto 0);
tmp
:= X(I) xor Y(I);
Cin : in std_logic;
Z(I)
<= tmp xor C(I);
Z : out std_logic_vector(n-1 downto 0);
C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
Cout : out std_logic);
end loop;
End ParallelAdder ;
Cout <= C(n);
end process;
44
end Functional;

VHDL Sentences (small selection)

4 .3

SequentialSentences:Exit(insidealoop)

Endstheloopexecutionwhenboolean_conditionistrueandgoestonextsentence
aftertheloop.
Syntax: [label:] exit [loop_label] [when <boolean_condition>];

Needed
N
d d for
f neested
t d loops
l
t id tif which
toidentify
hi h is
i the
th
loop tobeexitedor nexted

SequentialSentences:Next(insidealoop)

Stopscurrentloopiterationwhenboolean_conditionistrueandgoesforthenextiteration
St
tl
it ti
h b l
diti i t d
f th
t it ti
(skipscurrentiterationafterthissentence).
Syntax: [label:] next [loop_label] [when <boolean_condition>];

45

VHDL Sentences (small selection)

4 .3

SequentialSentences:Functions(sameassoftwarelanguages)

Apieceofcodedevotedtospecificcomputationofinputparameterstoreturnavalue.
Syntaxforfunctiondeclaration: function <name> [(<parameters list>)] return <data_type>;

Syntaxforfunctiondefinition:
function <name> [(<parameters list>)] return <data_type> is
{<declarative part>}
begin
{<sequential sentences>}
[label:] return [expresion];
end [function] [<name>];

Example:
p
function bv2int (bs: bit_vector(7 downto 0)) return integer;

Var :
:= base + bv2int(adrBus(15 downto 8));

Functionusage
Sig <= base + bv2int(adrBus(7 downto 0));
orreference

46

VHDL Sentences (small selection)

4 .3

SequentialSentences:Procedures(sameassoftwarelanguages)

Apieceofcodedevotedtospecificcomputationofinputparameterstoreturnavalue.
Syntaxforproceduredeclaration: procedure <name> [(<parameters list>)];

Syntaxforproceduredefinition:
procedure <name> [(<parameters list>)] is
{<declarative part>}
begin
{<sequential sentences>}
end [function] [<name>];

Example:
p
procedure bv2int (bs: bit_vector(7 downto 0); x: out integer );

Procedureusage
orreference

bv2int(adrBus(15 downto 8); Var);

Var := base + Var;
47

4 .3

VHDL Sentences (small selection)

SequentialSentences:Assert

Akindofvalidationsentence:when<boolean expression>isFALSEthe<stringofcharacters>
isprintedoutandactionsrelatedtospecifiedseveritylevelaredone.
[label:] assert <boolean expression>
p
Syntax:
y
[report <string of characters>]
[severity (note | warning | error |failure);

Examples:
p
assert not(addr < X"00001000" or addr > X"0000FFFF)
report Address in range" severity note;
assert (J /= C) report "J = C" severity note;

SequentialSentences:Report

Syntax:

Example:

[label:] [report < string of characters >]

[severity (note | warning | error |failure);

report Check point 13;

assert FALSE Check point 13 severity note;

4 .3

VHDL Summary (part-II)

Sessionsummary

Sequentialvs.ConcurrentworldsinVHDL

VHDLsequentialsentences(insideaprocess,functionorprocedure)
Selectedsentences:
Selected sentences:

Variable&signalassignments
Wait

Ifthenelseendif
Case

Loop,ExitandNext
Assert,Functions&Procedures

ExamplesbasedVHDLlearning

49

50

4 .44 Short introduction to VHDL

Llus Ters
Instituto de Microelectrnica de Barcelona, IMB-CNM (CSIC)
Universitat Autnoma de Barcelona (UAB)

(cont.)

4 .4

Previous comment
GeneralstructureofaVHDLmodel
entity X is
begin

end X;

architecture Y of X is

begin

onlyconcurrentsentences

S<=A when Sel=0 else B;

Clock <= not clock after 20 ns;

P1: process (clock, S);

begin

onlysequentialsentences
end process;

end Y;

P2: p
process

52

CONTENTS
1.
1
2.
3.
4
4.
5.
6.
7
7.

4 .4

Maingoals&Expectedlearning
M
i
l &E
t dl
i
BasicsonVHDLlexical&syntax
VHDLDesignUnits
VHDL Sequential Sentences (selection)
VHDLSequentialSentences(selection)
VHDLConcurrentSentences(selection)
VHDLusageformodelling,simulationandsynthesis
Summary

53

4 .4

VHDL Sentences (small selection)

ConcurrentSentences

Alltheconcurrentsentencesarebeingevaluatedsimultaneously

Wherearepossible?

Entity(passivesentences)
Block(collectsconcurrentsentences)
Architecture

Whicharetheselectedsentences?

Process
Signal assignments
Signalassignments

DirectAssignment
ConditionalAssignment
SelectedAssignment

entity X is
begin

Concurrent sentences

end X;

architecture Y of X is
begin

B : block
begin

end block;
end Y;

Components
Generate

Eachconcurrentsentencewillbetranslatedtoitsequivalentprocessbeforeitssimulation

54

4 .4

VHDL Sentences (small selection)

ConcurrentSentences:Process

Containssequentialsentencestodefineitsownbehaviour
Communicateswithotherprocessesandconcurrentsentencesbymeansofsignals
Theprocessisaninfiniteexecutionloopabletocontainstop/waitconditions(atleastONE!!)
Eachprocessissensibletoeventsonspecificsignalsorconditionstolaunchagainitsexecution
Syntax:
[<label>:] process [(<signal> ,{<signal>,
{<signal> ...})]
})] [is]
<local declarations>
begin
<sequential sentences>
end process [<label>];

process (<sensitivity signals list>)

begin
g
<sequential sentences>
end process;

process
begin
<sequential
i l sentences>
wait on <sensitivity signals list>;
end process;

55

4 .4

VHDL Sentences (small selection)

ConcurrentSentences:SignalAssignment

Syntax:
[label:] <signal> <= [delay_type] <expresion | waveform> {after <delay_time>};

Examples:
Tmp <= A xor B after 10 ns;
Z
<= Tmp xor Cin after 10 ns;
Cout <= (A and B) or (Tmp and Cin) after 15 ns;

Fullll
F
Adder

Cout

Waveform
W

W <= 0, 1 after 10 ns, 0 after 15 ns, 1 after 20 ns,

0 after 28 ns, 1
1 after 40 ns, 0
0 after 50 ns;
0

W
driver

Cin

10

15

20

28

40

50

(ns)
0

10

20

30

40

50

60

70

56

4 .4

VHDL Sentences (small selection)

ConcurrentSentences:ConditionalSignalAssignment
g
g

Syntax:
[<label>:] <signal> <= [delay_type]
{<expression|waveform> when <boolean expression> else}
< expression|waveform> [when <boolean expression>];

Example
S <= A when Sel = 0 else B;

process (Sel, A, B)
begin
if Sel = 0 then
S <= A;
else
S <= B;
end
d if;
if
end process;

process (Sel2, E1, E2)

begin
if Sel2 = 00 then
Equivalent
S <= E1;
Process
elsif Sel2 = 11 then
S <= E2;
else
null;
S <= E1 when Sel2 = 00 else
end if;
E2 when Sel2 = 11 else
end process;
unnafected when others;
Equivalent
57
Process

4 .4

VHDL Sentences (small selection)

ConcurrentSentences:SelectedSignalAssignment

Syntax:
[<label>] with <expression> select
<signal> <= [delay_type]
{<expression|waveform> when <value>,}
<
<expression|waveform>
i |
f
> when
h
< l >
<value>;

Example
with Operation select
Result <= Op1 + Op2
Op1 - Op2
O 1 and
Op1
d Op2
O 2
Op1 or Or2

when
when
when
h
when

add,
subs,
andL,
d
orL;

Equivalent
Process
Type opcode is (add, subs, andL, orL);
Signal operation : opcode;

process (Op1, Op2, Operation)

begin
case Operation is
when add => Result <= Op1 + Op2;
when subs => Result <= Op1 - Op2;
when andL => Result <= Op1 and Op2;
when orL => Result <= Op1 or Op2;
end case;
end process;

58

VHDL Sentences (small selection)

4 .4

ConcurrentSentences:Components

Structuralandhierarchicaldescriptionsbyusingcomponentsdefinedsomewhereelse.
Syntaxforcomponentdeclaration: component <idname> [is]
[generic (<generic parameters list>);]
[port (<ports list>);]
end [component] [<idname>];

Syntaxforcomponentreferenceorinstantiation:
<label>: <idname>
[generic map (<parameters association list>);]
[port map (<ports association list>);]

Examples:
component example is
port(a,
t(
b c : in
b,
i bit;
bit
d : out bit);
end component example;

Association lists by:

position
name

U2 : example port map (X, Y, W, Z)

U4 : example port map
(d=>Z, a=>X, b=>Y, c=>W);
59

4 .4

VHDL Sentences (small selection)

ConcurrentSentences:Components
entity FullAdder is
begin
port(X, Y, CIn
: in bit;
Cout, Su
Sum : out b
bit);
t);
end FullAdder;

U1
X
Y

architecture structural of FullAdder is

component HalfAdder
CIn
port(I1,
t(I1 I2
: in
i std_logic;
td l i
COut, Sum : out std_logic);
end component;
component OrG
port(I1, I2 : in std_logic;
O
: out std_logic);
end component;
Positionalassociationlist
signal A, B, C : std_logic;
begin
U1: HalfAdder port map (X, Y, A, B);
U2: HalfAdder port map (B, CIn, C, Sum);
U3: OrG port map (O => COut, I1 => A, I2 => C);
end structural;

Half
Adder

U3

A
B

Half
Adder

OrG

COut
Sum

U2
I1
0
0
1
1

I2
0
1
0
1

Sum Cout
0
0
1
0
1
0
0
1

Sum<=I1xor I2;Cout <=I1andI2;

Nominalassociationlist

60

VHDL Sentences (small selection)

4 .4

ConcurrentSentences:Generate

Generallyusedtocreatearraysofcomponentinstances,butitcouldincludeanyother
concurrentsentence. <label>: {[for <range specification> | if <condition> ]}
generate
Syntax:
{<concurrent sentences>}
end generate;

Example:
E(N-1)

E(N-2)

DFF

DFF

Clk

S(N-1)

E(0)

DFF

S(N-2)

S(0)

entity Register is
Parallelin/out
generic (N: positive);
NbitsRegister
port( Clk : in std_logic;
E
: in std_logic_vector(N-1 downto 0);
S
out std_logic_vector(N
std logic vector(N-1
1 downto 0));
end Register;
architecture structural of Register is
component DFF
port (Clk : in std_logic;
E
: in
i std_logic;
td l i
S
: out std_logic);
end component;
variable I : integer;
begin
GenReg: for I in N-1 downto 0 generate
Reg: DFF port map(Clk, E(I), S(I));
end generate;
61
end structural;

VHDL Sentences (small selection)

4 .4

ConcurrentSentences:Assert,Procedurecalland Functioncall

Sameusageandbehaviourastheequivalentsequentialones,butintheconcurrentworld.
[label:] assert <boolean expression>
[report <string of characters>]
[severity (note | warning | error |failure);

ConcurrentProcedurecallisjustlikeaprocesswithprocedureparametersinthesensitivity
list
list.
[label:] <Procedure name> [(<parameters>)];
Check_Timing(min_time, max_time, clk, sig_to_test, testOK);

F ti
Functioncallcouldbeembeddedinanyexpressioninsideaconcurrentstatement.
ll
ld b
b dd d i
i i id
t t t
t
function Check_Timing(min_time, max_time, clk, sig_to_test) returns boolean;

assert Check_Timing(min_time, max_time, clk, sig_to_test)

report Timing error
severity (warning);

62

VHDL Modelling, Simulation & Synthesis

4 .4

entity Exercise is end;

architecture Code of Exercise is
signal a,
a b : std_logic_vector(3
std logic vector(3 downto 0);
signal opcode : (add, sub);
signal z : std_logic_vector(3 downto 0);
Begin
Function under test
FuT: process (a, b, opcode);
variable x, y : std_logic_vector(3 downto 0);
variable s : std_logic; signal sign : std_logic;
begin
if a >= b then x := a; y := b; s := 0;
else x := b;
; y := a;
; s := 1;
;
case opcode is
when add then z <= x + y; sign <= 0;
when sub then z <= x y; sign <= s;
end case
end process FuT;
TV: process;
Test vectors wavefroms
begin
a <= 0110; b <= 0011; opcode <= add;
wait for 100 ns;
opcode <= sub; wait for 100 ns;
b <= 1001; wait for 100 ns;
opcode <= add; wait;
63
end process VdT;
end Functional;

VHDL Modelling, Simulation & Synthesis

4 .4

entity Exercise is end;

architecture Code of Exercise is
signal a,
a b : std_logic_vector(3
std logic vector(3 downto 0);
signal opcode : (add, sub);
signal z : std_logic_vector(3 downto 0);
Begin
Function under test
FuT: process (a, b, opcode);
variable x, y : std_logic_vector(3 downto 0);
variable s : std_logic; signal sign : std_logic;
begin
if a >= b then x := a; y := b; s := 0;
else x := b;
; y := a;
; s := 1;
;
case opcode is
when add then z <= x + y; sign <= 0;
when sub then z <= x y; sign <= s;
end case
end process FuT;
TV: process;
Test vectors wavefroms
begin
a <= 0110; b <= 0101; opcode <= add;
wait for 100 ns;
opcode <= sub; wait for 100 ns;
b <= 1001; wait for 100 ns;
opcode <= add; wait;
64
end process VdT;
end Functional;

VHDL Modelling, Simulation & Synthesis

4 .4

entity ParallelAdder is
generic (n : natural := 4);
g
port ( X, Y : in std_logic_vector(n-1 downto 0);
Cin : in std_logic;
Z : out std_logic_vector(n-1 downto 0);
Cout : out std_logic);
End ParallelAdder ;
achitecture Functional of ParallelAdder is
Begin
process (X, Y, Cin);
variable
i bl C : std_logic_vector(n
d l i
( downto
d
t 0);
0)
variable tmp : std_logic;
variable I : integer;
begin
C(0) := Cin;
for I in 0 to n-1 loop
tmp
:= X(I) xor Y(I);
Z(I)
<= tmp xor C(I);
C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
end loop;
Cout <= C(n);
end process;
end Functional;
65

VHDL Modelling, Simulation & Synthesis

4 .4

entity ParallelAdder is
generic (n : natural := 4);
g
port ( X, Y : in std_logic_vector(n-1 downto 0);
Cin : in std_logic;
Z : out std_logic_vector(n-1 downto 0);
Cout : out std_logic);
End ParallelAdder ;
Logic Simulation

achitecture Functional of ParallelAdder is

Begin
process (X, Y, Cin);
variable
i bl C : std_logic_vector(n
d l i
( downto
d
t 0);
0)
variable tmp : std_logic;
variable I : integer;
begin
Cout
C(0) := Cin;
for I in 0 to n-1 loop
tmp
:= X(I) xor Y(I);
X
Z(I)
<= tmp xor C(I);
C(I+1) := (tmp and C(I)) or (X(I) and Y(I));
end loop;
Z
Y
Cout <= C(n);
end process;
end
Logic Synthesis
Cin Functional;

4 .4

VHDL Summary (part-III)

Sessionsummary

VHDLconcurrentsentences(insideanarchitecture,blockorentity)
Selectedsentences:

Process
signalassignments(uncond &cond.)

Components
Generate

Assert
Functions&Procedures

VHDLmodelling,simulation&synthesis:basicconceptsandflows

VHDL E
VHDLExamplesbasedlearning
l b dl
i

ThisendsourshortintroductiontoVHDLlanguageforitsusageinthecurrent
g g
g
DigitalSystemsCourse

67

68

Basics on VHDL lexical & syntax

4 .2

VHDLDataTypes
TheVHDLisastronglytypedlanguage
Adatatypedefinesasetoffixedandstaticvalues
Anylanguageobjectbelongstoaspecificdatatype
Objectvaluesshallbelongtorelateddatatype
Newdatatypescouldbeuserdefined
Result
is real;

type
type mark is range 10.0 downto 0.0;
...
type Price is integer;
type Month is range 1 to 12;
...
type Cardinal is (North, South, East, West);
t
type
C dK
CardKeys
i (N,
is
(N S,
S E,
E W)
W);
type Mixed is (N, South, East, W);
...
variable Direction : Cardinal := West;
variable Var : Mixed;
Signal Key : CardKeys := N;
...
Var := N; -- Var & Key cannot be assigned to each other as
Key <= E; -- they doesnt belongs to the same data type

69

4 .2

VHDL Design Units

CONFIGURATION

Foreachcomponentinaspecificarchitectureselectsthemodule(entity+
architecturetobemappedonit
Example:

architecture structural of MUX21 is

signal Ctrl_n, N1, N2 : bit;
component INV
port( Y : in bit;
Z : out bit);
end component;
component AND2
port( X, Y : in bit;
Z
: out bit);
end component;
component OR2
port( X, Y : in bit;
Z
: out bit);
end component;
begin
U0: INV p
port map
p (
(Ctrl,
, Ctr_n);
);
U1: AND2 port map (Ctrl_n, A, N1);
U2: AND2 port map (Ctrl, B, N2);
U3: OR2 port map (N1, N2, Z);
end structural;

TTL

CMOS

configuration mux21_cfg of MUX21 is

for structural
for U0 : INV
use entity CMOS.INV(Funct);
for all : AND2
use entity TTL.AND2(Funct);
for U3 : OR2
use entity
i
CMOS.OR2(Funct);
2
end for;
end mux21_cfg;
70

4 .3

VHDL Sentences (small selection)

SequentialSentences:VariableAssignment

Immediate replacementofvariablevalue.
Syntax:
[label:] <variable name> := <expression>;

Nonequivalentsequences:

Examples:

A := B;
B := A;

B := A;
A := B;

Var := 0;
V t
Vector
:= 00011100
00011100;
string := Message is: ;
A := B;
B := my_function(3,databus)
C := my_function(4,adrbus) + A;

71

4 .3

VHDL Sentences (small selection)

SequentialSentences:Wait

Indicatesthepointwhereaprocessexecutionshallbesuspended,aswellasthe
Indicates
the point where a process execution shall be suspended as well as the
conditionsforitsreactivation.Morethanonewaitsentenceperprocessispossible.
Syntax:

Basicexamples:

[label:] wait [on <signal> {, ...}]

[until <boolean_expresion>]
[for <time_expresion>];

process
begin
<sequential sentences>
wait;
end process;

Withoutreactivationcondition

process
begin
c <= a and b;
wait on a, b;
end process;

Sensibletoeventsonsignalsab

process
b i
begin
Clock <= not Clock;
wait for 10 ns;
end process;

Suspendsandfixesatimeforreactivation10ns
process
begin
q <= d;
wait until Clock = 1;
end process;

Sensibletoeventsonsignals&condition=True

Otherpossibilities
wait on a,b until c=1;

wait until a=1 for 1 ns;

wait on a, b for 10 ns;

wait on a, b until c=1 for 10 ns;

72

4 .3

VHDL Sentences (small selection)

SequentialSentences:Ifthenelseendif;

SelectsthegroupofsentencestoexecutedependingonaBooleancondition.
Syntax:
[label:] if <condicion> then
<sentencias secuenciales>
{elsif <condicion> then
<sentencias secuenciales}
[else
<sentencias secuenciales>]
end if [
[label];
]

Examples:
Latch: process begin
if load =1 then
Q <= D;
end if;
wait on load, D;
end process;

Latch

Buffer Triestate
process
begin
if Enable =1 then
Salida <= Entrada;
else
Salida <= Z;
end if;
wait on Enable, Entrada;
end process;

Process (rst, clk)

FF with reset
begin
if rst =0 then
Q <= 0;
elsif clk
clkevent
event and clk=
clk=1
1 then
Q <= D;
end if;
end process;

if Ctrl = 0 then
Q <= A;
else
e
se
Q <= B;
end if;

Mux
73

4 .3

VHDL Sentences (small selection)

SequentialSentences:If&Case

AnotherexampletocombineIf&Case
sentencesinasingleProcess.
LatMux
A
B

C
D
Ctrl
Load

entity LatMux is
port(
Load
: in
A, B, C, D : in
Ctrl
: in
Y
end LatMux;

bit;
bit;
bit_vector(0 to 1);
: out bit);

architecture OneProc of LatMux is

begin
g
process (Load, Ctrl, A, B, C, D);
begin
if Load=0 then
case Ctrl is
when 00
00 =>
> Y <=
< A;
when 01 => Y <= B;
when 10 => Y <= C;
when 11 => Y <= D;
end case;
end
d if;
if
end process;
end OneProc;

74

4 .3

VHDL Sentences (small selection)

SequentialSentences:Loop

Sequentialsentencesintheloopregionarerepeatedforanumberoftimes.
Typesofloops:while,forandwithoutiterationscontrol(infiniteloop).
Syntax: [[label:]
abe :] [
[while
e <boolean
boo ea _co
condition>
d t o
| for
o <repetition
epet t o _co
control>]
t o ]
loop
<sequential sentences>}
end loop [label];

Examples:countermod16
process
begin
Cont <= 0;
loop
wait until Clock=1;
Cont <= (Cont + 1) mod 16;
end loop;
end process;

Withoutiterationscontrol(infiniteloop)

Process
var I : integer;
begin
Cont <= 0;
for I in 0 to 15 loop
wait until Clock=1;
Cont <= Cont + 1;
end loop;
wait until Clock=1;
end process;

Forcontrolledloop

process
begin
Cont <= 0;
wait until Clock=1;
while Cont < 15 loop
Cont <= Cont + 1;
wait until Clock=1
end loop;
end process;

Whilecontrolledloop

75

4 .3

VHDL Sentences (small selection)

SequentialSentences:Loop,Exit&Nextexample(countermodule16)
entity Counter16 is
port(
Clock, Rst : in bit;
Count : out natural);
end Counter16;

Countermodule16with
asynchronousreset

architecture functional of Counter16 is

variable C : natural;
begin
process
begin
C := 0;
loop
wait
it until
til ((Clockevent
((Cl k
t and
d Clock
Cl k = 1)
or Rst = 1);
exit when Rst = 1;
C := (C + 1) mod 16;
end loop;
end process;
Count <= C;
end functional;

Countermodule16
entity Counter16 is
whichavoidsvalue8
port(
Clock, Rst : in bit;
Count
Cou
t : out natural);
atu a );
end Counter16;
architecture functional of Counter16 is
variable C : natural;
variable I : integer;
begin
process
begin
C := 0;
for I in 0 to 15 loop
next when I=8;
C := I;
wait until Clock=1;
end loop;
p;
end process;
Count <= C;
end functional;
76

VHDL Sentences (small selection)

4 .4

ConcurrentSentences:Generate

Example:

entity ShiftReg is
NbitsShift register
generic (N: positive);
port( Clk, SIn : in bit ;
SOut
: out bit);
end ShiftReg;
X(0)
X(N 2)
X(N-2)
SIn
SOut
architecture structural of ShiftReg is
component DFF
DFF
DFF
DFF
port (Clk, E : in bit;
S
: out bit);
end component;
Clk
signal X : bit_vector(0 to N-2);
variable I : integer;
begin
GenShReg:
g for I in 0 to N-1 g
generate
G1 : if (I=0) generate
CIzq: DFF port map(Clk, SIn, X(I)); end generate;
G2 : if (I>0) and (I<N-1) generate
CCen: DFF port map(Clk, X(I-1), X(I)); end generate;
G3 : if (I=N-1)
(I=N 1) generate
CDer: DFF port map(Clk, X(I-1), SOut); end generate;
end generate;
77
end structural;

VHDL Sentences (small selection)

ConcurrentSentences:Generate

Example:

4 .4

entity
y ParallelAdder is
N bits Parallel Adder
NbitsParallelAdder
generic (n : natural),
port ( X, Y : in bit_vector(n-1 downto 0);
Cin : in bit;
Z
: out bit_vector(n-1 downto 0);
Cout : out bit);
End ParallelAdder;
architecture structural of parallelAdder is
component FA
Xn-1 Yn-1
Xn-2 Yn-2
X0 Y0
port ( A, B, Ci : in bit;
Cout=Cn
C0=Ci
Ci
Cn-1
C1
S C
S,
Co
: out
t bit);
bit)
n
end component;
FA
FA
FA
signal C : bit_vector(n downto 0);
variable I : integer;
begin
Zn-1
Zn-2
Z0
GenShReg: for I in 0 to N-1 generate
G1 : if (I=0) generate
LSB: FA port map(X(I), Y(I), Cin, Z(I), C(I+1)); end generate;
G2 : if (I>0) and (I<N-1) generate
OtherB: FA port map(X(I), Y(I), C(I), Z(I), C(I+1)); end generate;
G3 : if (I=N-1) generate
MSB: FA port map(X(I), Y(I), C(I), Z(I), Cout); end generate;
end generate;
78
end structural;

VHDL Sentences (small selection)

ConcurrentSentences:Generate

Example:

entity ParallelAdder is
generic (n : natural),
port ( X, Y : in bit_vector(n-1 downto 0);
Cin : in bit;
Z
: out bit_vector(n
bit vector(n-1
1 downto 0);
Cout : out bit);
End ParallelAdder;

4 .4
NbitsParallelAdder

architecture structural of ParallelAdder is

component FA
Xn-1 Yn-1
Xn-2 Yn-2
port ( A, B, Ci : in bit;
Cout=Cn
Cn-1
S, Co
: out bit);
end component;
FA
FA
signal C : bit_vector(n downto 0);
variable I : integer;
Begin
Zn-1
Zn-2
C(0) <= Cin;
GenParAdder: for I in 0 to N-1 generate
FAstage:
g
FA p
port map(X(I),
p( ( ), Y(I),
( ), C(I),
( ), Z(I),
( ), C(I+1));
(
));
end generate;
Cout <= C(n);
end structural;

X0 Y0
C0=Cin

C1

FA

Z0

79

4 .4

VHDL Modelling, Simulation & Synthesis

VHDL
Source code

VHDL Analyser

Libraries VHDL Elaboration

Sea of processes

VHDL
Simulator

4 .4

VHDL Simulation
VHDLEventDrivenSimulationCycle
y
Updating
Signals & Time

Processes
Execution

Which processes
shall be resumed?

?
y/n

Wait till all resumed

processes are stopped

...

Initialize
Signals
Drivers

Signals
Initialization

d
delay

STOP

y/n

Process-n

Process-1

y/n
Process-2

y/n

Update signals
drivers

5 Time

81

4 .4

VHDL Summary (part-III)

Sessionsummary

VHDLconcurrentsentences(insideanarchitecture,blockorentity)
Selectedsentences:

signalassignments
Conditionedsignalassignments

Process
Components

Generate
Assert,Functions&Procedures

VHDLmodelling,simulation&synthesis:basicconceptsandflows

VHDL
VHDLeventdrivensimulationofprocessesoceans
td i
i l ti
f
Simulationcycle
delayversussimulationtime

VHDLExamplesbasedlearning

ThisendsourshortintroductiontoVHDLlanguageforitsusageinthecurrent
DigitalSystemsCourse

82