Prototype of An Underground Multi-Storied

S.
NO
CONTENTS
1.
ABSTRACT
2.
INTRODUCTION
3.
4.
5.
6.
2.1
EMBEDDED SYSTEMS
2.2
SCOPE OF EMBEDDED SYSTEM
INTRODUCTION OF AMR7 LPC2148

3.1
BLOCK DIAGRAM DESCRIPTION
3.2
PIN DESCRIPTION OF LPC2148
3.3
EMBEDDED C
RF MODULE
4.1
HISTORY
4.2
ARCHITECHTURE
HARDWARE REQUIREMENT
5.1
BLOCK DIAGRAM
5.2
L.C.D.
5.3
IR SENSOR
SOFTWARE REQUIREMENT
6.1
SIMULATION/DEBUGGER
6.2
KEIL SOFTWARE
7.
APPLICATIONS
8.
CONCLUSION
9.
BIBLIOGRAPHY
PG.NO
CHAPTER-1
Abstract:
Prototype of an Underground Multi-Storied

Automated Car Parking System
Introduction
Parking of cars in a parking area is becoming a difficult task as the number of cars
increases when the parking space is limited. Hence, a person have to spend a certain amount of
time looking for parking space and thus cause a situation where the traffic would be slowed
down and results to congestion. Moreover, the information of available parking spaces is not
readily available to the people looking for space to parking. The situation for finding the parking
space and traffic congestion in parking areas are frequent. Different approaches have been used
to develop a car park management system such as wireless sensor network system, a vision based
system and the multi-storied parking system.
Existing System:
Recent increase in the growth of automotive industry coupled with the perpetual demand
of commuters urged the need for better and smarter parking mechanisms. Most of the existing
parking management systems rarely address the issues of parking space management, vehicle
guidance, parking lot reservation etc.
Proposed System:
In the proposed system we have three sections in which two sections are floor sections
and the third section is Gate section. The two floor sections are interfaced with the IR sensors to
detect vehicles. And the information is transmitted to the Gate section. If a car enters into the
Parking building the driver has to press a button in the keypad. At that time it will show the
vacant IR slots available for parking. So the driver can park the car in that particular slot without
wasting the time.
Block Diagram:
Floor1 Section:
Power
Power
Supply
Supply
LCD
LCD
RF
RF
ARM7
ARM7
LPC2148
LPC2148
IRIR
Receiver
Receiver
IRIR
Transceiver
Transceiver
IRIR
Receiver
Receiver
IRIR
Transceiver
Transceiver
Floor2 Section:
Power
Power
Supply
Supply
LCD
LCD
RF
RF
8051
8051
Micro
Micro
Controller
Controller
IRIR
Receiver
Receiver
IRIR
Transmitter
Transmitter
IRIR
Receiver
Receiver
IRIR
Transmitter
Transmitter
Gate Section:
Power
Power
Supply
Supply
LCD
LCD
RF
RF
8051
8051
Micro
Micro
Controller
Controller
Hardware used:
8051 Microcontroller.
Zigbee Transceiver.
RFID reader and Tag
MAX232
LCD.
Software used:
KEIL Complier.
Embedded C.
.Net
CHAPTER-2
Keypad
Keypad
INTRODUCTION
2.1 Embedded Systems:
An embedded system is a combination of software and hardware to perform a dedicated
task. Some of the main devices used in embedded products are Microprocessors and
Microcontrollers. Microprocessors are commonly referred to as general purpose processors as
they simply accept the inputs, process it and give the output. In contrast, a microcontroller not
only accepts the data as inputs but also manipulates it, interfaces the data with various devices,
controls the data and thus finally gives the result.
An embedded system can be defined as a computing device that does a specific focused
job. Appliances such as the air-conditioner, VCD player, DVD player, printer, fax machine,
mobile phone etc. are examples of embedded systems. Each of these appliances will have a
processor and special hardware to meet the specific requirement of the application along with the
embedded software that is executed by the processor for meeting that specific requirement. The
embedded software is also called firm ware. The desktop/laptop computer is a general purpose
computer. You can use it for a variety of applications such as playing games, word processing,
accounting, software development and so on. In contrast, the software in the embedded systems
is always fixed listed below:
Embedded systems do a very specific task they cannot be programmed to do different
things. Embedded systems have very limited resources, particularly the memory. Generally, they
do not have secondary storage devices such as the CDROM or the floppy disk. Embedded
systems have to work against some deadlines. A specific job has to be completed within a
specific time. In some embedded systems, called real-time systems, the deadlines are stringent.
Missing a deadline may cause a catastrophe-loss of life or damage to property. Embedded
systems are constrained for power. As many embedded systems operate through a battery, the
power consumption has to be very low. Some embedded systems have to operate in extreme
environmental conditions such as very high temperatures and humidity.
2.1.1 Categories of Embedded System.
2.1.1.1 Application specific systems.

Embedded systems are not general-purpose computers. Embedded system designs are
Optimized for a specific application. Many of the job characteristics are known before the
hardware is designed. This allows the designer to focus on the specific design constraints of a
well defined application. As such, there is limited user reprogram ability. Some embedded
systems, however, require the flexibility of reprogrammability. Programmable DSPs are common
for such applications.
2.1.1.2 Distributed Systems
A common characteristic of an embedded system is one that consists of communicating
processes executing on several CPUs or ASICs which are connected by communication links.
The reason for this is economy. Economical 4 8-bit microcontrollers may be cheaper than a 32bit processors. Even after adding the cost of the communication links, this approach may be
preferable. In this approach, multiple processors are usually required to handle multiple timecritical tasks. Devices under control of embedded systems may also be physically distributed.
2.1.1.3. Reactive Embedded systems.
A typical embedded systems model responds to the environment via Sensors and control
the environment using actuators. This requires embedded systems to run at the speed of the
environment. This characteristic of embedded system is called reactive. Reactive computation
means that the system (primarily the software component) executes in response to external
events.
External events can be either periodic or aperiodic. Periodic events make it easier to
schedule processing to guarantee performance. Aperiodic events are harder to schedule. The
maximum event arrival rate must be estimated in order to accommodate worst case situations.
Most embedded systems have a significant reactive component.
2.1.1.4. Heterogeneous
Embedded systems often are composed of heterogeneous architectures (Figure 4). They
may contain different processors in the same system solution. They may also be mixed signal
systems. The combination of I/O interfaces, local and remote memories, and sensors and
actuators makes embedded system design truly unique. Embedded systems also have tight design
constraints, and heterogeneity provides better design flexibility.
2.1.2. Requirements
Embedded systems are unique in several ways, as described above. When designing
Embedded systems, there are several categories of requirements that should be Considered:
Functional Requirements
Temporal Requirements (Timeliness)
Dependability Requirements.
Functional Requirements
Functional requirements describe the type of processing the system will perform. This
Processing varies, based on the application. Functional requirements include the Following;
Data Collection requirements
Sensor requirements
Signal conditioning requirements
Alarm monitoring requirements
Direct Digital Control requirements
Actuator control requirements
Man-Machine Interaction requirements
(Informing the operator of the current state of a controlled object for example. These interfaces
can be as simple as a flashing LED or a very complex GUI-based system. They include the ways
that embedded systems assist the operator in controlling the object/system.)
2.1.2.2. Temporal Requirement
Embedded systems have many tasks to perform, each having its own deadline.
Temporal requirements define the stringency in which these time-based tasks must complete.
Examples include;
Minimal latency jitter
Minimal Error-detection latency
Temporal requirements can be very tight (for example control-loops) or less stringent
(for example response time in a user interface).
2.1.2.3. Dependability Requirements
Most embedded systems also have a set of dependability requirements. Examples of
dependability requirements include;
Reliability: this is a complex concept that shoulda always be considered at the System rather than
the individual component level. There are three dimensions to Consider when specifying system
reliability;
Hardware reliability: Probability of a hardware component failing
Software reliability: Probability that a software component will produce an Incorrect result
Operator reliability: How likely that the operator of a system will make an Error.
2.1.3.Processor selection.
2.1.3.1. General factors that govern the selection are:
Complexity of overall design
Design reuse.
Performance
Power size
Cost tools.
OS Support and availability.

The design's complexity helps determine the CPU to use. If the design calls for the
deployment of a single state machine with interrupts from a small set of peripherals, then a small
CPU and/or micro controller such as the MCS51 or the Z80 could be the best choice. Many
systems such as industrial timer may fit this category, as the memory footprint is small, the signal
is slow and battery consumption must be extremely low. The application and its interaction will
dictate the design's complexity and may also determine whether it requires a real-time operating
system (RTOS).
Typically, as the application complexity increases, the need for a greater bit-width
processor increases. The selection of the CPU will greatly impact performance of the overall
system. Specifically, features like 8 / 16 / 24 / 32 bit architecture, RISC / CISC / DSP
architecture, cache, MMU, pipelining, branch prediction and super-scalar architecture, all affect
the speed of a system.Depending on system needs, these features may be necessary to achieve
peak performance of the system.
There are various benchmarking threshold data available for various 8/16/32 bit processors
like MIPS (Million Instructions per Second), EEMBC, Dhrystone, MIPS/MHz etc, which can be
taken as reference or comparison base.
CISC Vs RISC.
CISC is an acronym for Complex Instruction Set Computer and are chips that are easy to
program and which make efficient use of memory. Since the earliest machines were programmed
in assembly language and memory was slow and expensive, the CISC philosophy made sense,
and was commonly implemented in such large computers as the PDP-11 and the DECsystem 10
and 20 machines. Most common microprocessor designs such as the Intel 80x86 and Motorola
68K series followed the CISC philosophy. But recent changes in software and hardware
technology have forced a re-examination of CISC and many modern CISC processors are
hybrids, implementing many RISC principles.
The design constraints that led to the development of CISC (small amounts of slow memory
and fact that most early machines were programmed in assembly language) give CISC
instructions sets some common characteristics:
A 2-operand format, where instructions have a source and a destination. Register to
register, register to memory, and memory to register commands. Multiple addressing modes
for memory, including specialized modes for indexing through arrays
Variable length instructions where the length often varies according to the addressing
mode
Instructions which require multiple clock cycles to execute.
Most CISC hardware architectures have several characteristics in common:
Complex instruction-decoding logic, driven by the need for a single instruction to support
multiple addressing modes.
A small number of general purpose registers. This is the direct result of having
instructions which can operate directly on memory and the limited amount of chip space not
dedicated to instruction decoding, execution, and microcode storage.
Several special purpose registers. Many CTSC designs set aside special registers for the
stack pointer, interrupt handling, and so on. This can simplify the hardware design somewhat,
at the expense of making the instruction set more complex.
A 'Condition code" register which is set as a side-effect of most instructions. This register
reflects whether the result of the last operation is less than, equal to, or greater than zero and
records if certain error conditions occur.
At the time of their initial development, CISC machines used available technologies to
optimize computer performance.
Microprogramming is as easy as assembly language to implement, and much less
expensive than hardwiring a control unit.
The ease of microcoding new instructions allowed designers to make CISC machines
upwardly compatible: a new computer could run the same programs as earlier computers
because the new computer would contain a superset of the instructions of the earlier
computers.
As each instruction became more capable, fewer instructions could be used to implement
a given task. This made more efficient use of the relatively slow main memory.
Because microprogram instruction sets can be written to match the constructs of high-
level languages, the compiler does not have to be as complicated.
Designers soon realized that the CISC philosophy had its own problems, including:
Earlier generations of a processor family generally were contained as a subset in every
new version - so instruction set & chip hardware become more complex with each generation
of computers.
So that as many instructions as possible could be stored in memory with the least possible
wasted space, individual instructions could be of almost any length - this means that different
instructions will take different amounts of clock time to execute, slowing down the overall
performance of the machine.
Many specialized instructions aren't used frequently enough to justify their existence
-approximately 20% of the available instructions are used in a typical program.
CISC instructions typically set the condition codes as a side effect of the instruction. Not
only does setting the condition codes take time, but programmers have to remember to
examine the condition code bits before a subsequent instruction changes them.
As memory speed increased, and high-level languages displaced assembly language, the
major reasons for CISC began to disappear, and computer designers began to look at ways
computer performance could be optimized beyond just making faster hardware.
One of their key realizations was that a sequence of simple instructions produces the same results
as a sequence of complex instructions, but can be implemented with a simpler (and faster)
hardware design. (Assuming that memory can keep up.) RISC (Reduced Instruction Set
Computers) processors were the result. CISC and RISC implementations are becoming more and
more alike. Many of todays RISC chips support as many instructions as yesterday's CISC chips.
And today's CISC chips use many techniques formerly associated with RISC chips.
2.2 SCOPE OF EMBEDDED SYSTEMS
Nearly 99 per cent of the processors manufactured end up in embedded systems. The
embedded system market is one of the highest growth areas as these systems are used in very
market segment- consumer electronics, office automation, industrial automation, biomedical
engineering, wireless communication, data communication, telecommunications, transportation,
military and so on.
2.2.1 Consumer appliances:

At home we use a number of embedded systems which include digital camera, digital
diary, DVD player, electronic toys, microwave oven, remote controls for TV and air-conditioner,
VCO player, video game consoles, video recorders etc. Todays high-tech car has about 20
embedded systems for transmission control, engine spark control, air-conditioning, navigation
etc. Even wrist watches are now becoming embedded systems. The palmtops are powerful
embedded systems using which we can carry out many general-purpose tasks such as playing
games and word processing.
2.2.2 Office automation:
The office automation products using embedded systems are copying machine, fax
machine, key telephone, modem, printer, scanner etc.
2.2.3 Industrial automation:
Today a lot of industries use embedded systems for process control. These include
pharmaceutical, cement, sugar, oil exploration, nuclear energy, electricity generation and
transmission. The embedded systems for industrial use are designed to carry out specific tasks
such as monitoring the temperature, pressure, humidity, voltage, current etc., and then take
appropriate action based on the monitored levels to control other devices or to send information
to a centralized monitoring station. In hazardous industrial environment, where human presence
has to be avoided, robots are used, which are programmed to do specific jobs. The robots are
now becoming very powerful and carry out many interesting and complicated tasks such as
hardware assembly.
2.2.4 Medical electronics:
Almost every medical equipment in the hospital is an embedded system. These
equipments include diagnostic aids such as ECG, EEG, blood pressure measuring devices, X-ray
scanners; equipment used in blood analysis, radiation, endoscopy etc. Developments in medical
electronics have paved way for more accurate diagnosis of diseases.
2.2.5 Computer networking:

Computer networking products such as bridges, routers, Integrated Services Digital
Networks (ISDN), Asynchronous Transfer Mode (ATM), X.25 and frame relay switches are
embedded systems which implement the necessary data communication protocols. For example,
a router interconnects two networks. The two networks may be running different protocol stacks.
The routers function is to obtain the data packets from incoming pores, analyze the packets and
send them towards the destination after doing necessary protocol conversion. Most networking
equipments, other than the end systems (desktop computers) we use to access the networks, are
embedded systems.
2.2.6 Telecommunications:
In the field of telecommunications, the embedded systems can be categorized as
subscriber terminals and network equipment. The subscriber terminals such as key telephones,
ISDN phones, terminal adapters, web cameras are embedded systems. The network equipment
includes multiplexers, multiple access systems, Packet Assemblers Dissemblers (PADs),
sate11ite modems etc. IP phone, IP gateway, IP gatekeeper etc. are the latest embedded systems
that provide very low-cost voice communication over the Internet.
2.2.7 Wireless technologies:
Avances in mobile communications are paving way for many interesting applications
using embedded systems. The mobile phone is one of the marvels of the last decade of the 20h
century. It is a very powerful embedded system that provides voice communication while we are
on the move. The Personal Digital Assistants and the palmtops can now be used to access
multimedia services over the Internet. Mobile communication infrastructure such as base station
controllers, mobile switching centers are also powerful embedded systems.
2.2.8 Insemination:
Testing and measurement are the fundamental requirements in all scientific and
engineering activities. The measuring equipment we use in laboratories to measure parameters
such as weight, temperature, pressure, humidity, voltage, current etc. are all embedded systems.
Test equipment such as oscilloscope, spectrum analyzer, logic analyzer, protocol analyzer, radio
communication test set etc. are embedded systems built around powerful processors. Thank to
miniaturization, the test and measuring equipment are now becoming portable facilitating easy
testing and measurement in the field by field-personnel.
2.2.9 Security:
Security of persons and information has always been a major issue. We need to protect
our homes and offices; and also the information we transmit and store. Developing embedded
systems for security applications is one of the most lucrative businesses nowadays. Security
devices at homes, offices, airports etc. for authentication and verification are embedded systems.
Encryption devices are nearly 99 per cent of the processors that are manufactured end up in~
embedded systems.
Embedded Systems find applications in every industrial segment consumer electronics,
transportation, avionics, biomedical engineering, manufacturing, process control and industrial
automation, data communication, telecommunication, defense, security etc used to encrypt the
data/voice being transmitted on communication links such as telephone lines. Biometric systems
using fingerprint and face recognition are now being extensively used for user authentication in
banking applications as well as for access control in high security buildings.
2.2.10 Finance:
Financial dealing through cash and cheques are now slowly paving way for transactions
using smart cards and ATM (Automatic Teller Machine, also expanded as Any Time Money)
machines. Smart card, of the size of a credit card, has a small micro-controller and memory; and
it interacts with the smart card reader! ATM machine and acts as an electronic wallet. Smart card
technology has the capability of ushering in a cashless society. Well, the list goes on. It is no
exaggeration to say that eyes wherever you go, you can see, or at least feel, the work of an
embedded system.
Overview of Embedded System Architecture
Every embedded system consists of custom-built hardware built around a Central

Processing Unit (CPU). This hardware also contains memory chips onto which the software is
loaded. The software residing on the memory chip is also called the firmware.
Fig 2.1 The building blocks diagram

The operating system runs above the hardware, and the application software runs above
the operating system as shown in figure. The same architecture is applicable to any computer
including a desktop computer. However, there are significant differences. It is not compulsory to
have an operating system in every embedded system. For small appliances such as remote
control units, air conditioners, toys etc., there is no need for an operating system and you can
write only the software specific to that application.
For applications involving complex processing, it is advisable to have an operating
system. In such a case, you need to integrate the application software with the operating system
and then transfer the entire software on to the memory chip. Once the software is transferred to
the memory chip, the software will continue to run for a long time you dont need to reload new
software.
Now, let us see the details of the various building blocks of the hardware of an embedded
system.
As shown in Fig. the building blocks are;

Central Processing Unit (CPU)
Memory (Read-only Memory and Random Access Memory)
Input Devices
Output devices
Communication interfaces
.Application-specific circuitry
Fig 2.2 Working of cpu in arm7

Central Processing Unit (CPU):
The Central Processing Unit (processor, in short) can be any of the following:
microcontroller, microprocessor or Digital Signal Processor (DSP). A micro-controller is a lowcost processor. Its main attraction is that on the chip itself, there will be many other components
such as memory, serial communication interface, analog-to digital converter etc. So, for small
applications, a micro-controller is the best choice as the number of external components required
will be very less. On the other hand, microprocessors are more powerful, but you need to use
many external components with them. D5P is used mainly for applications in which signal
processing is involved such as audio and video processing.
Memory:
The memory is categorized as Random Access 11emory (RAM) and Read Only Memory
(ROM). The contents of the RAM will be erased if power is switched off to the chip, whereas
ROM retains the contents even if the power is switched off. So, the firmware is stored in the
ROM. When power is switched on, the processor reads the ROM; the program is program is
executed.
Input devices:
Unlike the desktops, the input devices to an embedded system have very limited
capability. There will be no keyboard or a mouse, and hence interacting with the embedded
system is no easy task. Many embedded systems will have a small keypad-you press one key to
give a specific command. A keypad may be used to input only the digits. Many embedded
systems used in process control do not have any input device for user interaction; they take
inputs from sensors or transducers 1fnd produce electrical signals that are in turn fed to other
systems.
Output devices:
The output devices of the embedded systems also have very limited capability. Some
embedded systems will have a few Light Emitting Diodes (LEDs) to indicate the health status of
the system modules, or for visual indication of alarms. A small Liquid Crystal Display (LCD)
may also be used to display some important parameters.
Interfaces:
The embedded systems may need to, interact with other embedded systems at they may
have to transmit data to a desktop. To facilitate this, the embedded systems are provided with one
or a few communication interfaces such as RS232, RS422, RS485, Universal Serial Bus (USB),
IEEE 1394, Ethernet etc.
Application-specific circuitry:
Sensors, transducers, special processing and control circuitry may be required fat an
embedded system, depending on its application. This circuitry interacts with the processor to
carry out the necessary work. The entire hardware has to be given power supply either through
the 230 volts main supply or through a battery. The hardware has to design in such a way that the
power consumption is minimized.
Wireless Communication:
Wireless communication, as the term implies, allows information to be exchanged
between two devices without the use of wire or cable. A wireless keyboard sends information to
the computer without the use of a keyboard cable; a cellular telephone sends information to
another telephone without the use of a telephone cable. Changing television channels, opening
and closing a garage door, and transferring a file from one computer to another can all be
accomplished using wireless technology. In all such cases, information is being transmitted and
received using electromagnetic energy, also referred to as electromagnetic radiation. One of the
most familiar sources of electromagnetic radiation is the sun; other common sources include TV
and radio signals, light bulbs and microwaves. To provide background information in
understanding wireless technology, the electromagnetic spectrum is first presented and some
basic terminology defined.
CHAPTER - 3
ARM
A complex instruction set computer, commonly known as CISC, is in complete contrast
to the reduced instruction set computer, commonly known as RISC. Both stand for two entirely
different philosophies in modern computer architecture. Some microcontrollers supports the
RISC architecture some microcontrollers supports the CISC architecture.
The example of the RISC architecture is 8085 microcontroller and ARM microcontrollers
supports the RISC architecture.
3.2.1 CISC architecture
In 1964 IBM released the IBM 360 to much acclaim. It is regarded as the first modern
processor system and adopted the concept of micro-coded control. Micro-coded control
accommodated the use of complex instruction sets which is a vital concept within CISC
architecture. A CISC central processing unit recognizes an enormous amount of instructions that
denote highly complex task. The CISC based architecture tends to throw the kitchen sink at the
problem, items that are common to the architecture include:
It allowed for a much less complicated compiler as extremely complex tasks were
implemented in micro-coding
Instruction sets for loops
Instruction sets for procedure calls
Complex addressing modes
Small program sizes, complex routines completed by hardware
Uses of CISC:
Some common CISC based processors included the System/360, VAX, PDP-11,
Motorola 68000 family, and Intel x86 architecture based processors. The CISC based
architecture's crowning glory has to have been the Intel x86 lines in my opinion. The x86
generation defines the first few processor generations which were backward compatible with the
original Intel 8086 and has revolutionized personal computing as we know it. The x86
architecture is now supported by an enormous amount of software and operating platforms such
as the following systems, from MS-DOS, Windows, BSD, Linux, Solaris and recently more
recently Mac OS-X. Through these systems, CISC can be seen throughout all industries from
fashion to finance and from engineering to healthcare.
To further push the CISC architecture, Intel aggressively marketed the Pentium 486
Processors this single act allowed people to have CISC based processors at a fraction of their
development cost and changed the layout of the RISC versus CISC debate.
3.2.2 RISC architecture
A RISC (Reduced Instruction Set Computer) based system contains a much more
minimized instruction set, allowing the programmer to break their application into much smaller
steps, doing less, and simplifying their solutions. It was developed in response to the CISC
approach and maintained that complex addressing took many instruction cycles to perform and
would be much better facilitated by sequences of simpler instructions at a much higher
frequency. RISC emphasized the instructions that were used most often and further optimized
them for the fastest possible execution. RISC architecture would have the following common
characteristics:
Uniform instruction formats
Identical and many more general purpose registers
Extremely simple addressing modes
Very few data types
A reduced instruction set
Simplified architecture
Larger program sizes, complex routines are completed by the compiler
Less costly to design, test, and manufacture
Faster instruction execution
RISC maintains a few, simple pipelined instructions with fixed length and typically 1
instruction/cycle. They support only register-to-register operations and a few simple addressing
modes (usually register addressing).
Uses of RISC:
The RISC based architecture has become more prominent in the computer industry
however it is only in recent times that this has become evident. The RISC chip is faster than its
CISC counterpart as it is designed and built more economically, and predominantly retains those
instructions that can be executed in one machine cycle or less. The RISC chip's influence can be
seen lately within the Apple IPod, its ARM architecture dominates the market for high precision,
lower power, low cost mobile embedded devices and is used in high class gaming consoles such
as the Nintento Wii, Sony Play station 3 and throughout many other consoles such as the XBOX
360 (Controller).
The RISC based architecture has very little impact on the desktop PC market where
Intels x86 architecture remains the dominant processor, however it is making large inroads into
the high-end server market, it should also be noted that in 2008 a RISC based architecture, Power
Architecture-based Cell processors, within the IBM's Roadrunner is the number one recognized
supercomputer in the world. It should still be noted that the vast majority of other
supercomputers are using x86 CISC architecture too.
3.2.3 Features of ARM7TDMI-S:
32/16-bit RISC architecture (ARM v4T)
32-bit ARM instruction set for maximum performance and flexibility
16-bit Thumb instruction set for increased code density
Unified bus interface, 32-bit data bus carries both instructions and data
Three-stage pipeline
32-bit ALU
Very small die size and low power consumption
Fully static operation
Coprocessor interface
Extensive debug facilities:

Embedded ICE-RT real-time debug unit
JTAG interface unit
Interface for direct connection to Embedded Trace Macrocell(ETM)
3.2.4 The ARM7TDMI Core:

The ARM7TDMI core is the industrys most widely used 32-bit embedded RISC
microprocessor. Optimized for cost and power- sensitive applications, the ARM7TDMI solution
provides the low power consumption, small size and high performance needed in portable,
embedded applications. Key features are:
Hard macro cell
Portable down to 65nm
Performance up to 133 MHz
Thumb and ARM instruction sets
Three-stage pipeline
Unified bus architecture
Low power, fully static design
Small die size
Coprocessor interface
Embedded ICE-RT debug logic
Embedded Trace Microcell (ET) interface
3.2.5 The ARM7TDMI-S Core
The ARM7TDMI-S core is the synthesizable version of the ARM7TDMI but with the
improved testability and flexibility that synthesis offers. Scan flip-flops for automatic production
testing and customer-specific boundary scan can easily be added. Optimized for flexibility, the
ARM7TDMI-S core cuts time-to-market by reducing development time while allowing for
increased design flexibility
.
3.2.6 The ARM7EJ-S Core
The ARM7EJ-S core provides all the benefits of the ARM7TDMI core low power
consumption, small size and the Thumb instruction set while also incorporating ARMs Jazelle
DBX technology and DSP extensions, offering up to 133 MHz on a typical 0.13m process.
The DSP instruction extensions allow systems that may conventionally have been designed using
a microcontroller and DSP to be implemented in a single core solution, removing multi-core
complexity.
The Jazelle DBX extensions enable hardware acceleration in the execution of Java
applications while retaining compatibility with existing ARM and Thumb code.
3.2.7 The ARM720T Macrocell
The ARM720T hard Macrocell is a high-performance processor for systems requiring full
virtual memory management and protected execution spaces. It is compatible with leading
operating systems such as Linux, Palm OS, Symbian OS and Windows CE. It combines the
ARM7TDMI core with:
8K unified cache
Memory Management Unit (MMU)
Write buffer
AMBA AHB bus interface
The ARM720T core retains the coprocessor and ETM interfaces for system expansion and realtime debug capabilities
ARM{x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{-S}
Xfamily
Ymemory management/protection unit
Zcache
TThumb 16-bit decoder
DJTAG debug
Mfast multiplier
IInterrupt
Eenhanced instructions (assumes TDMI)
JJazelle
Fvector oating-point unit

Ssynthesizable version
The ARM7TDMI core is a member of the ARM family of general-purpose 32-bit
microprocessors. The ARM family offers high performance for very low power consumption,
and small size. The ARM architecture is based on Reduced Instruction Set Computer (RISC)
principles. The RISC instruction set and related decode mechanism are much simpler than those
of Complex Instruction Set Computer (CISC) designs. This simplicity gives:
a high instruction throughput
an excellent real-time interrupt response
a small, cost-effective, processor macrocell.
The instruction pipeline: The ARM7TDMI core uses a pipeline to increase the speed of the
flow of instructions to the processor. A three-stage pipeline is used, so instructions are executed
in three stages:
Fig 3.1 block diagram of pipeline

Memory access:
The ARM7TDMI core has Von Neumann architecture, with a single 32-bit data bus
carrying both instructions and data. Only load, store, and swap instructions can access data from
memory.
Data can be:
8-bit (bytes)
16-bit (halfwords)
32-bit (words).
Memory interface:
The Embedded ICE-RT logic provides integrated on-chip debug support for the
ARM7TDMI core. The Embedded ICE-RT logic contains a Debug Communications Channel
(DCC), used to pass information between the target and the host debugger. The Embedded ICERT logic is controlled through the Joint Test Action Group (JTAG) test access port.
Architecture
The ARM7TDMI processor has two instruction sets:
the 32-bit ARM instruction set
the 16-bit Thumb instruction set.
Instruction compression
In comparison with 16-bit architectures, 32-bit architectures exhibit higher performance
when manipulating 32-bit data and can address a large address space much more efficiently. 16bit architectures typically have higher code density than 32-bit architectures, but approximately
half the performance.
Thumb implements a 16-bit instruction set on a 32-bit architecture to provide:
higher performance than a 16-bit architecture
higher code density than a 32-bit architecture.
The Thumb instruction set
Thumb instructions are each 16 bits long, and have a corresponding 32-bit ARM
instruction that has the same effect on the processor model. On execution, 16-bit Thumb
instructions are transparently decompressed to full 32-bit ARM instructions in real time, without
performance loss.
Thumb has all the advantages of a 32-bit core:
32-bit address space

32-bit registers
32-bit shifter, and Arithmetic Logic Unit (ALU)
32-bit memory transfer.
Thumb therefore offers Long Branch range, powerful arithmetic operations, and a large address
space.
3.2.7. Differences between processor and micro controller
A microprocessor incorporates the functions of a computer's central processing unit
(CPU) on a single integrated circuit, (IC) or at most a few integrated circuits. It is a
multipurpose, programmable device that accepts digital data as input, processes it according to
instructions stored in its memory, and provides results as output. It is an example of sequential
digital logic.
The advent of low-cost computers on integrated circuits has transformed modern society.
General-purpose microprocessors in personal computers are used for computation, text editing,
multimedia display, and communication over the Internet. Many more microprocessors are part
of embedded systems, providing digital control of a myriad of objects from appliances to
automobiles to cellular phones and industrial process control.
A microprocessor control program can be easily tailored to different needs of a product
line, allowing upgrades in performance with minimal redesign of the product. Different features
can be implemented in different models of a product line at negligible production cost.
Microprocessor control of a system can provide control strategies that would be impractical to
implement using electromechanical controls or purpose-built electronic controls. For example, an
engine control system in an automobile can adjust ignition timing based on engine speed, load on
the engine, ambient temperature, and any observed tendency for knocking - allowing an
automobile to operate on a range of fuel grades.
A microcontroller is a small and low-cost computer built for the purpose of dealing with
specific tasks, such as displaying information in a microwave LED or receiving information from
a televisions remote control. Microcontrollers are mainly used in products that require a degree
of control to be exerted by the user.
Microcontroller v/s microprocessor

Microprocessors are used to execute big and generic applications, while a microcontroller
will only be used to execute a single task within one application. Some of the benefits of
microcontrollers include the following:
Cost advantage:
The biggest advantage of microcontrollers against larger microprocessors is that the
design and hardware costs are much lesser and can be kept to a minimum. A microcontroller is
cheap to replace, while microprocessors are ten times more expensive.
Lesser power usage:
Microcontrollers are generally built using a technology known as Complementary Metal
Oxide Semiconductor (CMOS). This technology is a competent fabrication system that uses less
power and is more immune to power spikes than other techniques.
All-in-one:
A microcontroller usually comprises of a CPU, ROM, RAM and I/O ports, built within it
to execute a single and dedicated task. On the other hand, a microprocessor generally does not
have a RAM, ROM or IO pins and generally uses its pins as a bus to interface to peripherals such
as RAM, ROM, serial ports, digital and analog IO.
3.2.8 LPC2148
The LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI-S

CPU with real-time emulation and embedded trace support, that combines the microcontroller
with embedded high speed flash memory ranging from 32 kB to 512 kB. A 128-bit wide memory
interface and unique accelerator architecture enable 32-bit code execution at the maximum clock
rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more
than 30 % with minimal performance penalty. Due to their tiny size and low power consumption,
LPC2141/2/4/6/8 ideal for applications where miniaturization is a key requirement, such as
access control and point-of-sale. A blend of serial communications interfaces ranging from a
USB 2.0 Full Speed device, multiple UARTs, SPI, SSP to I2Cs, and on-chip SRAM of 8 kB up
to 40 kB, make these devices very well suited for communication gateways and protocol
converters, soft modems, voice recognition and low end imaging, providing both large buffer
size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC,
PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt
pins make these microcontrollers particularly suitable for industrial control and medical systems.
Features:
16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory.
128 bit wide interface/accelerator enables high speed 60 MHz operation.
In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.
Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.
Embedded ICE RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software and high speed tracing of instruction execution.
USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.
In addition, the LPC2146/8 provides 8 kB of on-chip RAM accessible to USB by DMA.
One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14
analog inputs, with conversion times as low as 2.44 s per channel.
Single 10-bit D/A converter provide variable analog output.
Two 32-bit timers/external event counters (with four capture and four compare channels
each), PWM unit (six outputs) and watchdog.
Low power real-time clock with independent power and dedicated 32 kHz clock input.
Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus
(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.
Vectored interrupt controller with configurable priorities and vector addresses.
Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.
Up to nine edge or level sensitive external interrupt pins available.
60 MHz maximum CPU clock available from programmable on-chip PLL with settling
time of 100 s.
On-chip integrated oscillator operates with an external crystal in range from 1 MHz to
30 MHz and with an external oscillator up to 50 MHz.
Power saving modes include Idle and Power-down.
Individual enable/disable of peripheral functions as well as peripheral clock scaling for

additional power optimization.
Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out
Detect (BOD) or Real-Time Clock (RTC).
Single power supply chip with Power-On Reset (POR) and BOD circuits:
CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V tolerant I/O pads.
Applications
Industrial control
Medical systems
Access control
Point-of-sale
Communication gateway
Embedded soft modem
General purpose applications
On-chip flash memory system

The LPC2141/2/4/6/8 incorporates a 32 kB, 64 kB, 128 kB, 256 kB, and 512 kB Flash
memory system, respectively. This memory may be used for both code and data storage.
Programming of the Flash memory may be accomplished in several ways: over the serial built-in
JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application
Programming (IAP) capabilities. The application program, using the IAP functions, may also
erase and/or program the Flash while the application is running, allowing a great degree of
flexibility for data storage field firmware upgrades, etc. When the LPC2141/2/4/6/8 on-chip boot
loader is used, 32 kB, 64 kB, 128 kB, 256 kB, and 500 kB of Flash memory is available for user
code.
The LPC2141/2/4/6/8 Flash memory provides minimum of 100,000 erase/write cycles
and 20 years of data-retention.
On-chip Static RAM (SRAM)
On-chip Static RAM (SRAM) may be used for code and/or data storage. The on-chip
SRAM may be accessed as 8-bits, 16-bits, and 32-bits. The LPC2141/2/4/6/8 provide 8/16/32 kB
of static RAM, respectively. The LPC2141/2/4/6/8 SRAM is designed to be accessed as a byteaddressed memory. Word and halfword accesses to the memory ignore the alignment of the
address and access the naturally-aligned value that is addressed (so a memory access ignores
address bits 0 and 1 for word accesses, and ignores bit 0 for halfword accesses).
Therefore valid reads and writes require data accessed as half words to originate from
addresses with address line 0 being 0 (addresses ending with 0, 2, 4, 6, 8, A, C, and E in
hexadecimal notation) and data accessed as words to originate from addresses with address lines
0 and 1 being 0 (addresses ending with 0, 4, 8, and C in hexadecimal notation). This rule applies
to both off and on-chip memory usage.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls
during back-to-back writes. The write-back buffer always holds the last data sent by software to
the SRAM. This data is only written to the SRAM when another write is requested by software
(the data is only written to the SRAM when software does another write). If a chip reset occurs,
actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip
reset, the SRAM does not reflect the last write operation).
Any software that checks SRAM contents after reset must take this into account. Two
identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a
dummy write operation before entering idle or power-down mode will similarly guarantee that
the last data written will be present in SRAM after a subsequent Reset.
Block Diagram:
Fig 3.2 block digram of arm7

Memory map concepts and operating modes
The basic concept on the LPC2141/2/4/6/8 is that each memory area has a "natural" location in
the memory map. This is the address range for which code residing in that area is written. The
bulk of each memory space remains permanently fixed in the same location, eliminating the need
to have portions of the code designed to run in different address ranges.
Because of the location of the interrupt vectors on the ARM7 processor (at addresses 0x0000
0000 through 0x0000 001C), a small portion of the Boot Block and SRAM spaces need to be remapped in order to allow alternative uses of interrupts in the different operating modes. Remapping of the interrupts is accomplished via the Memory Mapping Control feature.
Table: ARM exception vector locations

LPC2148 System control
The System Control Block includes several system features and control registers for a
number of functions that are not related to specific peripheral devices. These include:
Crystal Oscillator
External Interrupt Inputs
Miscellaneous System Controls and Status
Memory Mapping Control
PLL
Power Control
Reset
APB Divider
Wakeup Timer
Each type of function has its own register(s) if any are required and unneeded bits are
defined as reserved in order to allow future expansion. Unrelated functions never share the same
register addresses.
Pin description
The below table shows the pins that are associated with System Control block functions.
LPC2148 Pin configuration
Fig 3.3 pin description of arm7
LPC2148 Pin connect block
The purpose of the Pin connect block is to configure the microcontroller pins to the
desired functions. The pin connect block allows selected pins of the microcontroller to have more
than one function. Configuration registers control the multiplexers to allow connection between
the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior
to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled
peripheral function that is not mapped to a related pin should be considered undefined.
Selection of a single function on a port pin completely excludes all other functions otherwise
available on the same pin.
The only partial exception from the above rule of exclusion is the case of inputs to the
A/D converter. Regardless of the function that is selected for the port pin that also hosts the A/D
input, this A/D input can be read at any time and variations of the voltage level on this pin will
be reflected in the A/D readings. However, valid analog reading(s) can be obtained if and only if
the function of an analog input is selected. Only in this case proper interface circuit is active in
between the physical pin and the A/D module. In all other cases, a part of digital logic necessary
for the digital function to be performed will be active, and will disrupt proper behavior of the
A/D.
The Pin Control Module contains 2 registers as shown in Table below.
Table: Pin connect block register map
Vectored Interrupt Controller
Features
ARM Prime Cell Vectored Interrupt Controller
32 interrupt request inputs
16 vectored IRQ interrupts
16 priority levels dynamically assigned to interrupt requests
Software interrupts generation
The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and
programmably assigns them into 3 categories, FIQ, vectored IRQ, and non-vectored IRQ.
The programmable assignment scheme means that priorities of interrupt from the various
peripherals can be dynamically assigned and adjusted. Fast Interrupt request (FIQ) requests have
the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to
produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when
only one request is classified as FIQ, because then the FIQ service routine can simply start
dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ
service routine can read a word from the VIC that identifies which FIQ source(s) is (are)
requesting an interrupt.
Vectored IRQs have the middle priority, but only 16 of the 32 requests can be assigned to
this category. Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots, among
which slot 0 has the highest priority and slot 15 has the lowest.
Non-vectored IRQs have the lowest priority.
The VIC ORs the requests from all the vectored and non-vectored IRQs to produce the
IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from
the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the
address of the highest-priority requesting IRQs service routine, otherwise it provides the address
of a default routine that is shared by all the non-vectored IRQs. The default routine can read
another VIC register to see what IRQs are active.
All registers in the VIC are word registers. Byte and half word reads and write are not supported
Pin Description:
Symbol
P0.0/TXD0/PW
M1
P0.1/RXD0/
Pin
19
Type
I/O
21
O
O
I/O
22
I
O
I
I/O
PWM3/EINT0
P0.2/SCL0/
CAP0.0
I/O
I
P0.3/SDA0/
MAT0.0/EINT1
26
I/O
I/O
O
I
P0.4/SCK0/
CAP0.1/AD0.6
27
I/O
I/O
I
I
P0.5/MISO0/
MAT0.1/AD0.7
29
I/O
I/O
O
I
P0.6/MOSI0/
CAP0.2/AD1.0
30
I/O
I/O
I
I
P0.7/SSEL0/
31
I/O
Description
General
purpose
input/output
pin(GPIO).
Transmitter output for UART0.
Pulse Width Modulator output 1.
General
purpose
input/output
digital pin (GPIO).
Receiver input for UART0.

External interrupt 0 input.
General purpose input/output digital pin

(GPIO).
I2C0 Clock input/output. Open-drain
output (for I2C-bus compliance).
Capture input for Timer 0, channel
0.

(GPIO).
II2C0 data input/output. Open-drain
output (for I2C-bus compliance).
Match output for Timer 0, channel 0.
(GPIO).
Serial clock for SPI0. SPI clock output
from master or input to slave.
Capture input for Timer 0, channel 0.
ADC 0, input 6.
(GPIO).
Master In Slave OUT for SPI0. Data input
to SPI master or data output from SPI
slave.
ADC 0, input 7.
(GPIO).
Master Out Slave In for SPI0. Data
output from SPI master or data
input to SPI slave.
ADC
1, input 0. Available
in
LPC2144/46/48 only
PWM2/EINT2
I
O
I
P0.8/TXD1/
PWM4/AD1.1
33
P0.9/RXD1/
PWM6/EINT3
34
P0.10/RTS1/
CAP1.0/AD1.2
35
I/O
O
O
I
I/O
I
O
I
I/O
O
I
I
P0.11/CTS1/
CAP1.1/SCL1
37
I/O
P0.12/DSR1/
MAT1.0/AD1.3
38
I/O
I
O
I
P0.13/DTR1/
MAT1.1/AD1.4
39
I/O
P0.14/DCD1/
EINT1/SDA1
41
I
I
I/O
O
O
I
I/O
(GPIO).
Slave Select for SPI0. Selects the SPI
interface as a slave.
P0.8 General purpose input/output
digital pin (GPIO).
Transmitter output for UART1.
ADC
in
LPC2144/46/48 only
(GPIO).
Receiver input for UART1.
External interrupt 3 input
(GPIO).
Request to Send output for UART1.
LPC2144/46/48 only.
ADC
in
LPC2144/46/48 only.
(GPIO).
Clear to Send input for UART1. Available
in LPC2144/46/48 only.
I2C1 clock input/output. Open-drain
output (for I2C-bus compliance)
(GPIO).
Data Set Ready input for UART1.
Available in LPC2144/46/48 only.
ADC input 3. Available in LPC2144/46/48
only.
(GPIO).
Data Terminal Ready output for UART1.
LPC2144/46/48 only.
ADC input 4. Available in LPC2144/46/48
only.
(GPIO).
I
I
I/O
P0.15/RI1/
EINT2/AD1.5
45
I/O
I
I
I
P0.16/EINT0/
MAT0.2/CAP0.2
46
P0.17/CAP1.2/
SCK1/MAT1.2
47
I/O
I
I/O
O
I/O
I
I/O
O
P0.18/CAP1.3/
MISO1/MAT1.3
53
I/O
I
I/O
O
P0.19/MAT1.2/
MOSI1/CAP1.2
54
I/O
O
I/O
I
P0.20/MAT1.3/
SSEL1/EINT3
55
I/O
O
I
I
Data Carrier Detect input for UART1.

LPC2144/46/48 only.
I2C1 data input/output. Open-drain
output (for I2C-bus compliance)
Note: LOW on this pin while RESET is
LOW forces on-chip boot loader to
take over control of the part after reset
(GPIO).
Ring Indicator input for UART1.
Available in LPC2144/46/48 only.
ADC
in
LPC2144/46/48 only.
(GPIO).
Capture input for Timer 0, channel 2
(GPIO).
Serial Clock for SSP. Clock output from
master or input to slave.
(GPIO).
Master In Slave Out for SSP. Data input
to SPI master or data output from SSP
slave.
(GPIO).
Master Out Slave In for SSP. Data output
from SSP master or data
Input to SSP slave.
(GPIO).
Slave Select for SSP. Selects the SSP
interface as a slave.
External interrupt 3 input
P0.21/PWM5/
AD1.6/CAP1.3
I/O
O
I
I
P0.22/AD1.7/
CAP0.0/MAT0.0
I/O
I
I
O
P0.23/VBUS
58
I/O
I
P0.25/AD0.4/
AOUT
P0.28/AD0.1/
CAP0.2/MAT0.2
13
P0.29/AD0.2/
CAP0.3/MAT0.3
14
P0.30/AD0.3/
EINT3/CAP0.0
15
P0.31/UP_LED/
CONNECT
17
I/O
I
O
I/O
I
I
O
I/O
I
I
O
I/O
I
I
I
O
O

(GPIO).
ADC
in
LPC2144/46/48 only.
(GPIO).
ADC
in
LPC2144/46/48 only.
(GPIO).
Indicates the presence of USB bus power.
Note: This signal must be HIGH for USB
reset to occur.
(GPIO).
ADC 0, input 4.
DAC
output.
Available
in
LPC2142/44/46/48 only
(GPIO).
ADC 0, input 1.
(GPIO).
ADC 0, input 2.
Capture input for Timer 0, Channel 3.
(GPIO).
ADC 0, input 3.
General purpose output only digital pin
(GPO).
USB Good Link LED indicator. It is LOW
when device is configured (non-control
endpoints enabled). It is HIGH when the
device is not configured or during global
suspend.
Signal used to switch an external 1.5 k
resistor under the software control. Used
with the SoftConnect USB feature.

Important: This is an digital output only pin. This pin
MUST NOT be
externally pulled LOW when RESET pin is LOW or the
JTAG port will be
disabled.
P1.16/
TRACEPKT0
16
P1.17/
TRACEPKT1
12
P1.18/
TRACEPKT2
P1.19/
TRACEPKT3
P1.20/
TRACESYNC
48
P1.21/
PIPESTAT0
44
P1.22/
PIPESTAT1
40
P1.23/
PIPESTAT2
36
P1.24/
TRACECLK
32
P1.25/EXTIN0
28
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
O
I/O
I
P1.26/RTCK
24
I/O

(GPIO).
Trace Packet, bit 0. Standard I/O port
with internal pull-up
(GPIO).
with internal pull-up.
(GPIO).
(GPIO).
(GPIO).
Trace Synchronization. Standard I/O port
(GPIO).
Pipeline Status, bit 0. Standard I/O port
(GPIO).
(GPIO).
(GPIO).
Trace Clock. Standard I/O port with
internal pull-up.
(GPIO).
External Trigger Input. Standard I/O with
internal pull-up.
I/O
(GPIO).
Returned Test Clock output. Extra signal
added to the JTAG port.
Assists debugger synchronization when
processor frequency varies.
Bidirectional pin with internal pull-up.
Note: LOW on RTCK while RESET is LOW
enables pins P1.31:26 to operate
as Debug port after reset.
64
I/O
60
O
I/O
56
I
I/O
52
I
I/O
20
I
I/O
D+
DRESET
10
11
57
I
I/O
I/O
I
XTAL1
62
XTAL2
RTXC1
RTXC2
VSS
61
3
5
O
I
O
I
P1.27/TDO
P1.28/TDI
P1.29/TCK
P1.30/TMS
P1.31/TRST
6,
18,
25,
42,

(GPIO).
Test Data out for JTAG interface
(GPIO).
Test Data in for JTAG interface.
(GPIO).
Test Clock for JTAG interface.
(GPIO).
Test Mode Select for JTAG interface.
(GPIO).
Test Reset for JTAG interface
USB bidirectional D+ line
USB bidirectional D- line
A LOW on this pin resets the device,
causing I/O ports and peripherals to take
on their default states, and processor
execution to begin at address 0. TTL with
hysteresis, 5 V tolerant
Input to the oscillator circuit and internal
clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
0 V Reference ground
50
VSSA
59
VDD
23,
Analog ground: 0 V reference. This should

nominally be the same voltage as VSS, but
should be isolated to minimize noise and
error.
3.3 V power supply: This is the power
VDDA
43,
51
7
VREF
63
Vbat
49
supply voltage for the core and I/O

ports.
Analog 3.3 V power supply: This should
be nominally the same voltage as VDD but
error. This voltage is only used to power
the on-chip ADC(s) and DAC.
ADC reference: This should be nominally
less than or equal to the VDD voltage but
error. Level on this pin is used as a
reference for ADC(s) and DAC.
RTC power supply: 3.3 V on this pin
supplies the power to the RTC.
3.3 Embedded C language

Embedded C is a set of language extensions for the C Programming language by the C Standards
committee to address commonality issues that exist between C extensions for different embedded
systems. Historically, embedded C programming requires nonstandard extensions to the C language in
order to support exotic features such as fixed-point arithmetic, multiple distinct memory banks, and basic
I/O operations.
The C programming language is perhaps the most popular programming language for
programming embedded systems. We mentioned other popular programming languages).
Most C programmers are spoiled because they program in environments where not only there is
a standard library implementation, but there are frequently a number of other libraries available
for use. The cold fact is, that in embedded systems, there rarely are many of the libraries that
programmers have grown used to, but occasionally an embedded system might not have a
complete standard library, if there is a standard library at all. Few embedded systems have
capability for dynamic linking, so if standard library functions are to be available at all, they
often need to be directly linked into the executable. Oftentimes, because of space concerns, it is
not possible to link in an entire library file, and programmers are often forced to "brew their
own" standard c library implementations if they want to use them at all. While some libraries are
bulky and not well suited for use on microcontrollers, many development systems still include
the standard libraries which are the most common for C programmers.
C remains a very popular language for micro-controller developers due to the code
efficiency and reduced overhead and development time. C offers low-level control and is
considered more readable than assembly. Many free C compilers are available for a wide variety
of development platforms. The compilers are part of an IDEs with ICD support, breakpoints,
single-stepping and an assembly window. The performance of C compilers has improved
considerably in recent years, and they are claimed to be more or less as good as assembly,
depending on who you ask. Most tools now offer options for customizing the compiler
optimization. Additionally, using C increases portability, since C code can be compiled for
different types of processors.
Figure. 3.4 Embedded System Development Environment
CHAPTER-4
RF Module
RF is a specification for a suite of high level communication protocols using small, low-power
digital radios based on the IEEE 802.15.4-2003 standard for wireless personal area networks
(WPANs), such as wireless headphones connecting with cell phones via short-range radio. The
technology defined by the RF specification is intended to be simpler and less expensive than
other WPANs, such as Bluetooth. RF is targeted at radio-frequency (RF) applications that require
a low data rate, long battery life, and secure networking. The RF Alliance is a group of
companies that maintain and publish the RF standard.
INTRODUCTION
RF is an established set of specifications for wireless personal area networking (WPAN), i.e.
digital radio connections between computers and related devices. WPAN Low Rate or RF
provides specifications for devices that have low data rates, consume very low power and are
thus characterized by long battery life. RF makes possible completely networked homes where
all devices are able to communicate and be controlled by a single unit. The RF Alliance, the
standards body which defines RF, also publishes application profiles that allow multiple OEM
vendors to create interoperable products. The current list of application profiles either published
or in the works are:
Home Automation
RF Smart Energy
Telecommunication Applications
Personal Home
The relationship between IEEE 802.15.4 and RF is similar to that between IEEE 802.11 and the
Wi-Fi Alliance. For non-commercial purposes, the RF specification is available free to the
general public. An entry level membership in the RF Alliance, called Adopter, costs US$ 3500
annually and provides access to the as-yet
unpublished specifications and permission to create products for market using the specifications.
RF is one of the global standards of communication protocol formulated by the relevant task
force under the IEEE 802.15 working group. The fourth in the series, WPAN Low Rate/RF is the
newest and provides specifications for devices that have low data rates, consume very low power
and are thus characterized by long battery life. Other standards like Bluetooth and IrDA address
high data rate applications such as voice, video and LAN communications. RF devices are
actively limited to a through rate of 250Kbps, compared to Bluetooth's much larger pipeline of
1Mbps, operating on the 2.4 GHz ISM band, which is available throughout most of the world.In
the consumer market RF is being explored for everything from linking low-power household
devices such as smoke alarms to a central housing control unit, to centralized light controls.
The specified maximum range of operation for RF devices is 250 feet (76m),
substantially further than that used by Bluetooth capable devices, although security concerns
raised over "sniping" Bluetooth devices remotely, may prove to hold true for RF devices as well.
Due to its low power output, RF devices can sustain themselves on a small battery for many
months, or even years, making them ideal for install-and-forget purposes, such as most small
household systems. Predictions of RF installation for the future, most based on
the explosive use of RF in automated household tasks in China, look to a near future when
upwards of sixty RF devices may be found in an average American home, all communicating
with one another freely and regulating common tasks seamlessly. The RF Alliance has been set
up as an association of companies working together to enable reliable, cost-effective, lowpower, wirelessly networked, monitoring and control products based on an open global
standard. Once a manufacturer enrolls in this Alliance for a fee, he can have access to the
standard and implement it in his products in the form of RF chipsets that would be built into the
end devices. Philips, Motorola, Intel, HP are all members of the Alliance. The goal is to provide
the consumer with ultimate flexibility, mobility, and ease of use by building wireless intelligence
and capabilities into every day devices. RF technology will be embedded in a wide range of
products and applications across consumer, commercial, industrial and government markets
worldwide. For the first time, companies will have a standards based wireless platform optimized
for the unique needs of remote monitoring and control applications, including simplicity,
reliability, lowcost and low-power.The target networks encompass a wide range of devices with
low data rates in the Industrial, Scientific and Medical (ISM) radio bands, with buildingautomation controls like intruder/fire alarms, thermostats and remote (wireless) switches,
video/audio remote controls likely to be the most popular applications. So far sensor and control
devices have been marketed as proprietary items for want of a standard. With acceptance and
implementation of RF, interoperability will be enabled in multi-purpose, self-organizing mesh
networks.
RF CHARACTERISTICS
The focus of network applications under the IEEE 802.15.4 / RF standard include the features of
low power consumption, needed for only two major modes (Tx/Rx or Sleep), high density of
nodes per network, low costs and simple implementation. These features are enabled by the
following characteristics,
2.4GHz and 868/915 MHz dual PHY modes. This represents three license-free bands: 2.42.4835 GHz, 868-870 MHz and 902-928 MHz The number of channels allotted to each
frequency band is fixed at sixteen (numbered 11-26), one (numbered 0) and ten (numbered 1-10)
respectively. The higher frequency band is applicable worldwide, and the lower band in the areas
of North America, Europe, Australia and New Zealand.
Low power consumption, with battery life ranging from months to years. Considering the
number of devices with remotes in use at present, it is easy to see that more numbers of batteries
need to be provisioned every so often, entailing regular (as well as timely), recurring
expenditure. In the RF standard, longer battery life is achievable by either of two means:
continuous network connection and slow but sure battery drain, or intermittent connection and
even slower battery drain.
Maximum data rates allowed for each of these frequency bands are fixed as 250 kbps @2.4
GHz, 40 kbps @ 915 MHz, and 20 kbps @868 MHz
High throughput and low latency for low duty cycle applications (<0.1%)
Channel access using Carrier Sense Multiple Access with Collision Avoidance (CSMA - CA)
Addressing space of up to 64 bit IEEE address devices, 65,535 networks.
ARCHITECTURE:
RF is a home-area network designed specifically to replace the proliferation of individual remote

controls. RF was created to satisfy the market's need for a cost-effective, standards-based
wireless network that supports low data rates, low power consumption, security, and reliability.
It may be helpful to think of IEEE 802.15.4 as the physical radio and RF as the logical network
and application software. Following the standard Open Systems Interconnection (OSI) reference
model, RF's protocol stack is structured in layers. The first two layers, physical (PHY) and media
access (MAC), are defined by the IEEE 802.15.4 standard. The layers above them are defined by
the RF Alliance. The IEEE working group passed the first draft of PHY and MAC in 2003.
RF-compliant products operate in unlicensed bands worldwide, including 2.4GHz
(global), 902 to 928MHz (Americas), and 868MHz (Europe). Raw data throughput rates of
250Kbps can be achieved at 2.4GHz (16 channels), 40Kbps at 915MHz (10 channels), and
20Kbps at 868MHz (1 channel). The transmission distance is expected to range from 10 to 75m,
depending on power output and environmental characteristics. Like Wi-Fi, RF uses directsequence spread spectrum in the 2.4GHz band, with offset-quadrature phase-shift keying
modulation. Channel width is 2MHz with 5MHz channel spacing. The 868 and 900MHz bands
also use direct-sequence spread spectrum but with binary-phase-shift keying modulation.
Protocols
The protocols build on recent algorithmic research (Ad-hoc On-demand Distance Vector,
neuRFon) to automatically construct a low-speed ad-hoc network of nodes. In most large
network instances, the network will be a cluster of clusters. It can also form a mesh or a single
cluster. The current profiles derived from the RF protocols support beacon and non-beacon
enabled networks.
In non-beacon-enabled networks (those whose beacon order is 15), an unslotted CSMA/CA
channel access mechanism is used. In this type of network, RF Routers typically have their
receivers continuously active, requiring a more robust power supply. However, this allows for
heterogeneous networks in which some devices receive continuously, while others only transmit
when an external stimulus is detected. The typical example of a heterogeneous network is a
wireless light switch: The RF node at the lamp may receive constantly, since it is connected to
the mains supply, while a battery-powered light switch would remain asleep until the switch is
thrown. The switch then wakes up, sends a command to the lamp, receives an acknowledgment,
and returns to sleep. In such a network the lamp node will be at least a RF Router, if not the RF
Coordinator; the switch node is typically a RF End Device.
In beacon-enabled networks, the special network nodes called RF Routers transmit periodic
beacons to confirm their presence to other network nodes. Nodes may sleep between beacons,
thus lowering their duty cycle and extending their battery life. Beacon intervals may range from
15.36 milliseconds to 15.36 ms * 2 14 = 251.65824 seconds at 250 Kbit/s, from 24 milliseconds to
24 ms * 214 = 393.216 seconds at 40 kbit/s and from 48 milliseconds to 48 ms * 2 14 = 786.432
seconds at 20 kbit/s. However, low duty cycle operation with long beacon intervals requires
precise timing, which can conflict with the need for low product cost.
In general, the RF protocols minimize the time the radio is on so as to reduce power use. In
beaconing networks, nodes only need to be active while a beacon is being transmitted. In nonbeacon-enabled networks, power consumption is decidedly asymmetrical: some devices are
always active, while others spend most of their time sleeping.
Except for the Smart Energy Profile 2.0, which will be MAC/PHY agnostic, RF devices are
required to conform to the IEEE 802.15.4-2003 Low-Rate Wireless Personal Area Network
(WPAN) standard. The standard specifies the lower protocol layersthe physical layer (PHY),
and the media access control (MAC) portion of the data link layer (DLL). This standard specifies
operation in the unlicensed 2.4 GHz (worldwide), 915 MHz (Americas) and 868 MHz (Europe)
ISM bands. In the 2.4 GHz band there are 16 RF channels, with each channel requiring 5 MHz of
bandwidth. The center frequency for each channel can be calculated as, F C = (2405 + 5 * (ch 11)) MHz, where ch = 11, 12, ..., 26.
The radios use direct-sequence spread spectrum coding, which is managed by the digital stream
into the modulator. BPSK is used in the 868 and 915 MHz bands, and OQPSK that transmits two
bits per symbol is used in the 2.4 GHz band. The raw, over-the-air data rate is 250 kbit/s per
channel in the 2.4 GHz band, 40 kbit/s per channel in the 915 MHz band, and 20 kbit/s in the
868 MHz band. Transmission range is between 10 and 75 meters (33 and 246 feet) and up to
1500 meters for RF pro, although it is heavily dependent on the particular environment. The
maximum output power of the radios is generally 0 dBm (1 mW).
The basic channel access mode is "carrier sense, multiple access/collision avoidance"
(CSMA/CA). That is, the nodes talk in the same way that people converse; they briefly check to
see that no one is talking before they start. There are three notable exceptions to the use of
CSMA. Beacons are sent on a fixed timing schedule, and do not use CSMA. Message
acknowledgments also do not use CSMA. Finally, devices in Beacon Oriented networks that
have low latency real-time requirements may also use Guaranteed Time Slots (GTS), which by
definition do not use CSMA.
RF/IEEE 802.15.4 - General Characteristics:
Dual PHY (2.4GHz and 868/915 MHz)
Data rates of 250 kbps (@2.4 GHz), 40 kbps (@ 915 MHz), and 20 kbps (@868 MHz)
Optimized for low duty-cycle applications (<0.1%)
CSMA-CA channel access Yields high throughput and low latency for low duty cycle
devices like sensors and controls
Low power (battery life multi-month to years)
Multiple topologies: star, peer-to-peer, mesh
Addressing
-
space
18,450,000,000,000,000,000
of
devices
up
(64
bit
IEEE
to:
address)
- 65,535 networks
Optional guaranteed time slot for applications requiring low latency
Fully hand-shaked protocol for transfer reliability
Range: 50m typical (5-500m based on environment)
Uses
RF protocols are intended for use in embedded applications requiring low data rates and low
power consumption. RF's current focus is to define a general-purpose, inexpensive, selforganizing mesh network that can be used for industrial control, embedded sensing, medical data
collection, smoke and intruder warning, building automation, home automation, etc. The
resulting network will use very small amounts of power individual devices must have a
battery life of at least two years to pass RF certification. SERIAL COMMUNICATION
RS-232 Interfaces:
The RS-232 interface is the Electronic Industries Association (EIA) standard for the
interchange of serial binary data between two devices. It was initially developed by the EIA to
standardize the connection of computers with telephone line modems. The standard allows as
many as 20 signals to be defined, but gives complete freedom to the user. Three wires are
sufficient: send data, receive data, and signal ground. The remaining lines can be hardwired on
or off permanently. The signal transmission is bipolar, requiring two voltages, from 5 to 25 volts,
of opposite polarity.
FIG.5.1 DB9 CONNECTOR
Table 5.1: RS-232 DB9 Pins

Pin
description
1
Data carrier detect ( -DCD)
Received data (RXD)
Transmitted data (TXD)
Data Terminal Ready (DTR)
Ground(GND)
Data Set Ready (-DSR)
Table 6.1 (contd): RS-232 DB9 Pins

7
Request To Send (-RTS)
Clear To Send (-CTS)
Ring Indicator (RI)
Communication Standards:
The industry custom is to use an asynchronous word consisting of: a start bit, seven or
eight data bits, an optional parity bit and one or two stop bits. The baud rate at which the word
sent is device-dependent. The baud rate is usually 150 times an integer power of 2, ranging from
0 to 7 (150, 300, 600, and 19,200). Below 150 baud, many system-unique rates are used. The
standard RS-232-C connector has 25 pins, 21 pins which are used in the complete standard.
Many of the modem signals are not needed when a computer terminal is connected directly to a
computer, and Figure 1 illustrates
How some of the "spare" pins should be linked if not needed. Figure1 also illustrates the
pin numbering used in the original DB-25 connector and that now commonly used with a DB-9
connector normally used in modern computers Specifying compliance to RS-232 only
establishes that the signal levels in two devices will be compatible and that if both devices use
the suggested connector, they may be able to be connected. Compliance to RS-232 does not
imply that the devices will be able to communicate or even acknowledge each other's presence.
Fig 5.2 DIRECT-TO-COMPUTER RS-232 INTERFACE

Table 5.2 shows the signal names, and functions of the RS-232 serial port pin out, Table 5.3 shows a
complete pin description.
Table 6.3 RS-232 Interface Signals
Range:
The RS-232-C standard specifies that the maximum length of cable between the
transmitter and receiver should not exceed 100 feet, although in practice many systems are used
in which the distance between transmitter and receiver exceeds this rather low figure. The
limited range of the RS-232C standard is one of its major shortcomings compared with other
standards which offer greater ranges within their specifications. One reason why the range of the
RS-232C standard is limited is the need to charge and discharge the capacitance of the cable
connecting the transmitter and receiver.
Table 6.4 Summary of RS-232
MAX-232:
The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to

supply EIA-232 voltage levels from a single 5-V supply. Each receiver converts EIA-232 inputs
to 5-V TTL/CMOS levels.
Fig 6.3 Schematic diagram of MAX-232
These receivers have a typical threshold of 1.3 V and a typical hysteresis of 0.5 V, and
can accept 30-V inputs. Each driver converts TTL/CMOS input levels into EIA-232 levels. The
driver, receiver, and voltage-generator functions are available as cells in the Texas Instruments
Lin ASIC library.
CHAPTER-5
Hardware Requirements
The following hardware required to develop the project
ARM7 microcontroller
Max232
LCD
8052 microcontroller
5.1. Design
5.1.1 Block Diagram:
Power
Supply
LCD
LPC2148
Microcontro
ller
RF
Sensor Unit
Figure 5.1 block diagram
5.2 LCD
5.2.1 Introduction
A liquid crystal display (LCD) is a thin, flat electronic visual display that uses the light
modulating properties of liquid crystals (LCs). LCs does not emit light directly.
They are used in a wide range of applications including: computer monitors, television,
instrument panels, aircraft cockpit displays, signal, etc. They are common in consumer devices
such as video players, gaming devices, clocks, watches, calculators, and telephones. LCDs have
displaced cathode ray tube (CRT) displays in most applications. They are usually more compact,
lightweight, portable, less expensive, more reliable, and easier on the eyes. They are available in
a wider range of screen sizes than CRT and plasma displays, and since they do not use
phosphors, they cannot suffer image burn-in.
LCDs are more energy efficient and offer safer disposal than CRTs. Its low electrical
power consumption enables it to be used in battery-powered electronic equipment. It is an
electronically-modulated optical device made up of any number of pixels filled with liquid
crystals and arrayed in front of a light source (backlight) or reflector to produce images in color
or monochrome. The earliest discovery leading to the development of LCD technology, the
discovery of liquid crystals, dates from 1888. By 2008, worldwide sales of televisions with LCD
screens had surpassed the sale of CRT units.
Each pixel of an LCD typically consists of a layer of molecules aligned between two
transparent electrodes, and two polarizing filters the axes of transmission of which are (in most
of the cases) perpendicular to each other. With no actual liquid crystal between the polarizing
filters, light passing through the first filter would be blocked by the second (crossed) polarizer. In
most of the cases the liquid crystal has double refraction
5.2.2Passive-matrix and active-matrix addressed LCDs
Figure 5.2 LCD diagram.

LCDs with a small number of segments, such as those used in digital watches and pocket
calculators, have individual electrical contacts for each segment. An external dedicated circuit
supplies an electric charge to control each segment. This display structure is unwieldy for more
than a few display elements.
The most commonly used Character based LCDs are based on Hitachi's HD44780
controller or other which are compatible with HD44580. In this tutorial, we will discuss about
character based LCDs, their interfacing with various microcontrollers, various interfaces (8-bit/4bit), programming, special stuff and tricks you can do with these simple looking LCDs which can
give a new look to your application.
5.2.3Pin Description
The most commonly used LCDs found in the market today are 1 Line, 2 Line or 4 Line
LCDs which have only 1 controller and support at most of 80 characters, whereas LCDs
supporting more than 80 characters make use of 2 HD44780 controllers.
Figure 5.3 pin description of LCD
5.2.4 Pin No. Name Description

Pin no. 1 VSS
Power supply (GND) Pin no. 2 VCC Power supply (+5V) Pin no. 3 VEE
Contrast adjust Pin no. 4 RS
0 = Instruction input
1 = Data input Pin no. 5 R/W
0 = Write to LCD module
1 = Read from LCD module Pin no. 6 EN
Enable signal Pin no. 7 D0 Data bus line 0 (LSB) Pin no. 8 D1 Data bus line 1 Pin no. 9 D2Data
bus line 2
Pin no. 10 D3
Data bus line 3
Pin no. 11 D4
Data bus line 4
Pin no. 12 D5
Data bus line 5
Pin no. 13 D6
Data bus line 6
Pin no. 14 D7
Data bus line 7 (MSB)
5.2.5 Commands and Instruction set
The instruction register (IR) and the data register (DR) of the LCD can be controlled by
the MCU. Before starting the internal operation of the LCD, control information is temporarily
stored into these registers to allow interfacing with various MCUs, which operate at different
speeds, or various peripheral control devices. The internal operation of the LCD is determined by
signals sent from the MCU. These signals, which include register selection signal (RS),
read/write signal (R/W), and the data bus (DB0 to DB7), make up the LCD instructions (Table
3). There are four categories of instructions that:
Designate LCD functions, such as display format, data length, etc.
Set internal RAM addresses
Perform data transfer with internal RAM
Although looking at the table you can make your own commands and test them. Below is a brief
list of useful commands which are used frequently while working on the LCD.
No.
Instruction
Hex
Decimal
1.Function Set: 8-bit, 1 Line, 5x7 Dots
0x3048
2. Function Set: 8-bit, 2 Line, 5x7 Dots
0x3856
3. Function Set: 4-bit, 1 Line, 5x7 Dots
0x2032
4.Function Set: 4-bit, 2 Line, 5x7 Dot
0x2840
5.Entry Mode
0x066
6. Display off Cursor off
(clearing display without clearing DDRAM content)
0x088
7. Display on Cursor on
0x0E14
8 .Display on Cursor off
0x0C12
9. Display on Cursor blinking 0x0F15
10. Shift entire display left
0x1824
12. Shift entire display right
0x1C30
13 .Move cursor left by one character
0x10 16
14. Move cursor right by one character0x1420
15.Clear Display (also clear DDRAM content)0x011

16 .Set DDRAM address or courser position on display 0x80+add*128+add*
17. Set CGRAM address or set pointer to CGRAM location
0x40+add**64+add**
* DDRAM address given in LCD basics section see Figure 2,3,4
** CGRAM address from 0x00 to 0x3F, 0x00 to 0x07 for char1 and so on..
IR SENSOR:
is the same principle in ALL Infra-Red proximity sensors. The basic idea is to send
infra red light through IR-LEDs, which is then reflected by any object in front of the
sensor.
Then all you have to do is to pick-up the reflected IR light. For detecting the
reflected IR light, we are going to use a very original technique: we are
going to use another IR-LED, to detect the IR light that was emitted from
another led of the exact same type. This is an electrical property of Light Emitting
Diodes (LEDs) which is the fact that a led Produce a voltage difference across its
leads when it is subjected to light. As if it was a photo-cell, but with much lower
output current. In other words, the voltage generated by the leds can't be - in any
way - used to generate electrical power from light, It can barely be detected. that's
why as you will notice in the schematic, we are going to use a Op-Amp (operational
Amplifier) to accurately detect very small voltage changes.
The sender is composed of an IR LED (D2) in series with a 470 Ohm resistor,
yielding a forward current of 7.5mA. The receiver part is more complicated, the 2
resistors R5 and R6 form a voltage divider which provides 2.5V at the anode of the
IR LED (here, this led will be used as a sensor). When IR light falls on the LED (D1),
the voltage drop increases, the cathode's voltage of D1 may go as low as 1.4V or
more, depending on the light intensity. This voltage drop can be detected using an
Op-Amp (operational Amplifier LM358).
You will have to adjust the variable resistor (POT.) R8 so the the voltage at the
positive input of the Op-Amp (pin No. 5) would be somewhere near 1.6 Volt. if you
understand the functioning of Op-Amps, you will notice that the output will go High
when the volt at the cathode of D1 drops under 1.6. So the output will be High when
IR light is detected, which is the purpose of the receiver.
If the +ve input's voltage is higher than the -ve input's voltage, the
output goes High (5v, given the supply voltage in the schematic),
otherwise, if the +ve input's voltage is lower than the -ve input's voltage,
then the output of the Op-Amp goes to Low (0V). It doesn't matter how big is
the difference between the +ve and -ve inputs, even a 0.0001 volts difference will
be detected, and the the output will swing to 0v or 5v according to which input has
a higher voltage.
MICROCONTROLLERS:
Microprocessors and microcontrollers are widely used in embedded systems
products. Microcontroller is a programmable device. A microcontroller has a CPU in addition to
a fixed amount of RAM, ROM, I/O ports and a timer embedded all on a single chip. The fixed
amount of on-chip ROM, RAM and number of I/O ports in microcontrollers makes them ideal
for many applications in which cost and space are critical.
The Intel 8052 is Harvard architecture, single chip microcontroller (C) which was
developed by Intel in 1980 for use in embedded systems. It was popular in the 1980s and early
1990s, but today it has largely been superseded by a vast range of enhanced devices with 8052compatible processor cores that are manufactured by more than 20 independent manufacturers
including Atmel, Infineon Technologies and Maxim Integrated Products.
8052 is an 8-bit processor, meaning that the CPU can work on only 8 bits of data at a
time. Data larger than 8 bits has to be broken into 8-bit pieces to be processed by the CPU. 8052
is available in different memory types such as UV-EPROM, Flash and NV-RAM.
The present project is implemented on Keil uVision. In order to program the device,
proload tool has been used to burn the program onto the microcontroller.
The features, pin description of the microcontroller and the software tools used are
discussed in the following sections.
FEATURES
Compatible with MCS-51 Products
8K Bytes of In-System Programmable (ISP) Flash Memory
Endurance: 1000 Write/Erase Cycles
4.0V to 5.5V Operating Range
Fully Static Operation: 0 Hz to 33 MHz
Three-level Program Memory Lock
256 x 8-bit Internal RAM
32 Programmable I/O Lines
Three 16-bit Timer/Counters
Eight Interrupt Sources
Full Duplex UART Serial Channel

Low-power Idle and Power-down Modes
Interrupt Recovery from Power-down Mode
Watchdog Timer
Dual Data Pointer
Power-off Flag
DESCRIPTION
The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K

bytes of in-system programmable Flash memory. The device is manufactured using Atmels
high-density nonvolatile memory technology and is compatible with the industry- standard
80C51 instruction set and pinout. The on-chip Flash allows the program memory to be
reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a
versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel
AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective
solution to many embedded control applications.
The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of
RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector
two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry.
In addition, the AT89S52 is designed with static logic for operation down to zero frequency and
supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
PIN CONFIGURATIONS
PIN DESCRIPTION
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight
TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.
Port 0 can also be configured to be the multiplexed low order address/data bus during accesses to
external program and data memory. In this mode, P0 has internal pullups. Port 0 also receives the
code bytes during Flash programming and outputs the code bytes during program verification.
External pullups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the
internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled
low will source current (IIL) because of the internal pullups. In addition, P1.0 and P1.1 can be
configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2
trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the
low-order address bytes during Flash programming and verification.
Port 2
low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX
@ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the
high-order address bits and some control signals during Flash programming and verification.
Port 3
low will source current (IIL) because of the pullups. Port 3 also serves the functions of various
special features of the AT89S52, as shown in the following table. Port 3 also receives some
control signals for Flash programming and verification.
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 96 oscillator periods after the Watchdog times out. The DISRTO
bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit
DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG) during Flash
programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator
frequency and may be used for external timing or clocking purposes. Note, however, that one
ALE pulse is skipped during each access to external data memory. If desired, ALE operation can
be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a
MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable
bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory. When the
AT89S52 is executing code from external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to external data
memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code
from external program memory locations starting at 0000H up to FFFFH. Note, however, that if
lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage (VPP) during Flash programming.
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be
configured for use as an on-chip oscillator, as shown in Figure. Either a quartz crystal or ceramic
resonator may be used. To drive the device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven, as shown in the below figure. There are no requirements on
the duty cycle of the external clock signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and maximum voltage high and low time
specifications must be observed.
Fig: Oscillator Connections
C1, C2 = 30 pF 10 pF for Crystals

= 40 pF 10 pF for Ceramic Resonators
Fig: External Clock Drive Configuration
8052 MICROCONTROLLER MEMORY ORGANIZATION

The microcontroller memory is divided into Program Memory and Data Memory. Program
Memory (ROM) is used for permanent saving program being executed, while Data Memory
(RAM) is used for temporarily storing and keeping intermediate results and variables. Depending
on the model in use (still referring to the whole 8052 microcontroller family) at most a few Kb of
ROM and 128 or 256 bytes of RAM can be used. However
All 8052 microcontrollers have 16-bit addressing bus and can address 64 kb memory. It is neither
a mistake nor a big ambition of engineers who were working on basic core development. It is a
matter of very clever memory organization which makes these controllers a real programmers
tidbit.
Program Memory
The oldest models of the 8052 microcontroller family did not have any internal program
memory. It was added from outside as a separate chip. These models are recognizable by their
label beginning with 803 (for ex. 8031 or 8032). All later models have a few Kbytes ROM
embedded, Even though it is enough for writing most of the programs, there are situations when
additional memory is necessary. A typical example of it is the use of so called lookup tables.
They are used in cases when something is too complicated or when there is no time for solving
equations describing some process. The example of it can be totally exotic (an estimate of selfguided rockets meeting point) or totally common (measuring of temperature using non-linear
thermo element or asynchronous motor speed control). In those cases all needed estimates and
approximates are executed in advance and the final results are put in the tables (similar to
logarithmic tables).
How does the microcontroller handle external memory depend on the pin EA logic state?
EA=0 In this case, internal program memory is completely ignored, only a program stored in
external memory is to be executed.
EA=1 In this case, a program from built-in ROM is to be executed first (to the last location).
Afterwards, the execution is continued by reading additional memory.
in both cases, P0 and P2 are not available to the user because they are used for data and address
transmission. Besides, the pins ALE and PSEN are used too.
SWITCHES AND PUSHBUTTONS
There is nothing simpler than this! This is the simplest way of controlling appearance of some
voltage on microcontrollers input pin. There is also no need for additional explanation of how
these components operate.
Nevertheless, it is not so simple in practice... This is about something commonly unnoticeable

when using these components in everyday life. It is about contact bounce- a common problem
with m e c h a n i c a l switches. If contact switching does not happen so quickly, several
consecutive bounces can be noticed prior to maintain stable state. The reasons for this are:
vibrations, slight rough spots and dirt. Anyway, whole this process does not last long (a few
micro- or miliseconds), but long enough to be registered by the microcontroller. Concerning
pulse counter, error occurs in almost 100% of cases!
CHAPTER - 6
SOFTWARE
6.1 Simulator/Debugger:
The simulator/ debugger in KEIL can perform a very detailed simulation of a micro controller
along with external signals. It is possible to view the precise execution time of a single assembly
instruction, or a single line of C code, all the way up to the entire application, simply by entering the
crystal frequency. A window can be opened for each peripheral on the device, showing the state of the
peripheral. This enables quick trouble shooting of mis-configured peripherals. Breakpoints may be set
on either assembly instructions or lines of C code, and execution may be stepped through one instruction
or C line at a time. The contents of all the memory areas may be viewed along with ability to find
specific variables. In addition the registers may be viewed allowing a detailed view of what the
microcontroller is doing at any point in time.
The Keil Software 8051 development tools listed below are the programs you use to
compile your C code, assemble your assembler source files, link your program together, create HEX
files, and debug your target program.
Vision2 for Windows Integrated Development Environment:
combines Project Management, Source Code Editing, and Program Debugging in one powerful
environment.
C51 ANSI Optimizing C Cross Compiler: creates relocatable object modules from your C source
code,
A51 Macro Assembler: creates relocatable object modules from your 8051 assembler
source code,
BL51
Linker/Locator:
combines relocatable object modules created by the compiler and
assembler into the final absolute object module,

LIB51 Library Manager: combines object modules into a library, which may be used by the
linker,
OH51 Object-HEX Converter: creates Intel HEX files from absolute object modules.
6.2 EVALUATION OF KEIL SOFTWARE

Start the Vision Program
After the program has started:
Type your assembly file. The following is an example of a toggle program.
Select File, Save from the program menu
The first time you save the program a dialog box will popup and allow you to name your
file and file type.
Save program with filename: xxxxx.asm
The File type is mentioned at last (.asm) means assembly language
Select Project, New Project from the program menu

Give some project name: xxxx.prj
Click on the Add button

A dialog-box appears, allowing you to add files to the project
Change the file type to Assembly.
Select your assembly file.

Click on the Add button then close the Add dialog box.
CHAPTER 8
Advantages:
Cost effective
Highly secured
Application
In congested area.
CHAPTER 8
CONCLUSION
The project Prototype of an Underground Multi-Storied Automated Car
Parking System been successfully designed and tested. It has been developed by
integrating features of all the hardware components used. Presence of every
module has been reasoned out and placed carefully thus contributing to the best
working of the unit.
Secondly, using highly advanced ICs and with the help of growing technology the
project has been successfully implemented.
BIBLOGRAPHY
www.arm.com
www.wikipedia.org
www.zigbee.org
www.nxp.com
www.keil.com
www.cadence.com
www.ieee.org

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S.

SCOPE OF EMBEDDED SYSTEM

INTRODUCTION OF AMR7 LPC2148

BLOCK DIAGRAM DESCRIPTION

PIN DESCRIPTION OF LPC2148

Prototype of an Underground Multi-Storied

2.1.1.1 Application specific systems.

Temporal Requirements (Timeliness)

Data Collection requirements

Signal conditioning requirements

Alarm monitoring requirements

Direct Digital Control requirements

Actuator control requirements

Man-Machine Interaction requirements

Complexity of overall design

OS Support and availability.

A 2-operand format, where instructions have a source and a destination. Register to

Instructions which require multiple clock cycles to execute.

Most CISC hardware architectures have several characteristics in common:

multiple addressing modes.

Microprogramming is as easy as assembly language to implement, and much less

expensive than hardwiring a control unit.

level languages, the compiler does not have to be as complicated.

Earlier generations of a processor family generally were contained as a subset in every

-approximately 20% of the available instructions are used in a typical program.

2.2.1 Consumer appliances:

2.2.5 Computer networking:

Every embedded system consists of custom-built hardware built around a Central

Fig 2.1 The building blocks diagram

As shown in Fig. the building blocks are;

Fig 2.2 Working of cpu in arm7

Instruction sets for loops

Instruction sets for procedure calls

Complex addressing modes

Small program sizes, complex routines completed by hardware

Uniform instruction formats

Identical and many more general purpose registers

Extremely simple addressing modes

Very few data types

A reduced instruction set

Larger program sizes, complex routines are completed by the compiler

Less costly to design, test, and manufacture

Faster instruction execution

32/16-bit RISC architecture (ARM v4T)

32-bit ARM instruction set for maximum performance and flexibility

16-bit Thumb instruction set for increased code density

Very small die size and low power consumption

Fully static operation

Extensive debug facilities:

3.2.4 The ARM7TDMI Core:

Fvector oating-point unit

Fig 3.1 block diagram of pipeline

32-bit address space

Microcontroller v/s microprocessor

The LPC2141/2/4/6/8 microcontrollers are based on a 32/16 bit ARM7TDMI-S

16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory.

128 bit wide interface/accelerator enables high speed 60 MHz operation.

In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.

In addition, the LPC2146/8 provides 8 kB of on-chip RAM accessible to USB by DMA.

Single 10-bit D/A converter provide variable analog output.

Vectored interrupt controller with configurable priorities and vector addresses.

Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.