EXPLORING ALTERNATIVE 3D FPGA ARCHITECTURES:

DESIGN METHODOLOGY AND CAD TOOL SUPPORT

K. Siozios, K. Sotiriadis, V. F. Pavlidist, andD. Soudris

Dept. of Electrical and Computer Engineering

University of Rochester, USA
email: pavlidis@ece.rochester.edu

Dep. of Electrical and Computer Engineering

Democritus University of Thrace, Greece
email: {ksiop, kostsot, dsoudris} @ee.duth.gr
ABSTRACT

This paper introduces a software supported methodology

for exploring/evaluating 3D FPGA architectures. Two new
CAD tools are developed: (i) the 3DPRO for placement and
routing on 3D FPGAs and (ii) the 3DPower for
power/energy estimation on such architectures. We mainly
focus our exploration on the total number of layers and the
amount of vertical interconnects (or vias). The efficiency of
the proposed architecture is evaluated by making an
exhaustive exploration for via connections under the
EnergyxDelay Product criterion. Experimental results
demonstrate the effectiveness of our solution, considering
the 20 largest MCNC benchmarks. Considering 3D
architectures with 4 layers and two scenarios of fabricated
via densities (30% and 70%), we achieve an average
decrease in the delay, the wire length, and the energy
consumption of 18%, 17%, and 310%, respectively, as
compared to 2D FPGAs. We also achieved high utilization
of vias links.
1. INTRODUCTION
In the real estate market, an often-stated truism is that as
land becomes more expensive, there is a tendency to build
upward, rather than outward. This idea has some resonance
in the domain of ICs, where the sizes of the die are limited
by yield and performance constraints. 3D integration can
mitigate many of these limitations. For example, a
considerable reduction in the number and length of the
global wires can be achieved [2]. This decrease results, in
turn, in performance enhancements and decreased power
consumption for 3D ICs as compared to 2D circuits.
Recently many research groups from academia [4, 5, 6,
7, 8], industry [9], and research institutes [1] have
investigated significant effort on designing and
manufacturing applications in 3D technologies. Several
companies [9] develop 3D ICs for commercial purposes by
wafer stacking, where the distance between the layers is
mainly determined by the wafer thickness. Note that the
existing industrial research primarily concerns the
manufacturing and fabrication processes rather than the
development of tools to support the design of emerging 3D

technologies.

This paper is part of the 03ED593 research project, implemented

within the framework of the "Reinforcement Program of Human
Research Manpower" (PENED) and co-financed by National and
Community Funds (75% from E.U.-European Social Fund and 25%
from the Greek Ministry of Development-General Secretariat of
Research and Technology).

1-4244-1060-6/07/$25.00 (C2007 IEEE.

Although 3D integration promises considerable

benefits, several challenges need to be satisfied. Among
others, design space exploration is essential to build highperformance and low energy architectures that exploit all
of the advantages offered by 3D integration. In addition,
CAD tools that facilitate the design of 3D circuits are
required. Up to date there are only a few academic CAD
tools [4, 6] for mapping applications on 3D FPGA
technologies, while there is no complete CAD flow in
order to promote the commercialization of this potent
design paradigm. Furthermore, there is no commercial
CAD tool for realizing applications on 3D FPGAs, similar
to the standalone tools and/or design flows (i.e. provided
by Cadence, Mentor Graphics, and Xilinx) for 2D
technologies. Consequently, there is a significant need to
develop algorithms and software tools to exploit the
advantages of the third dimension, and to solve time
consuming and complex tasks, such as floorplanning,
placement, and routing (P&R) for 3D FPGAs.
In [6], a P&R approach for island style 3D FPGA
architectures is described. A partitioning-based placement
and simulated annealing-based refinement tools are used,
which target on the reduction of the interconnection length.
The authors report gains in wire lengths compared to 2D
architectures, without considering, however, the wire
power consumption and delay. Hence, these tools (PR3D)
cannot be used for exploring alternative 3D architectures.
In [4], a similar P&R approach for 3D FPGAs is
described. The reconfigurable architecture consists of
multiple stacked functional layers, while the
communication among layers is realized by using 3D
Switch Boxes (SBs). A tool, named TPR, for P&R in such
devices was developed. Although TPR is one of the first
attempts in academia to develop tools for 3D FPGA, it
suffers from many limitations. The target architecture
utilized in this tool initially assumes an unlimited number
of vias, while the TPR aims at minimizing this number.
However, such a scenario is not realistic, since the total
number and the spatial distribution of vias are important
problems that need to be addressed. In addition, this tool
cannot estimate other important design parameters, such as
the power/energy consumption.
In this paper a software supported design methodology
for exploring several parameters of 3D FPGAs is
introduced. We evaluate for a number of cost factors, such
as delay, energy consumption, and total wire length over a
plethora of 3D architectures. Then, we perform exploration

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for different number and various locations of the vias that

connect circuits within the 3D FPGA. To best of our
knowledge, this is the first time that a software-supported
approach for exploring/evaluating 3D FPGAs with
different number of vias is presented. Using the 20 largest
MCNC benchmarks [11], we demonstrate the effectiveness
of our methodology.

the interlayer vias with length 5 pm -10 pm is feasible. For

such technologies, the delay of the wires dominates the
delay of the transistors (similarly to 2D architectures).
Two new software tools are developed to support the
proposed exploration/evaluation procedure for 3D
architectures. These tools are integrated onto the existing
MEANDER design flow [12] (Figure 1).
Apphlcation descniption in HDL

2. THE PROPOSED 3D FPGA ARCHITECTURE

AND TOOL FLOW

Existing
design flow

In order to realize the interlayer vias, we have to extend

some conventional 2D SBs to employ connections to the
other layers of the 3D FPGA. Although the utilized SBs
are based on the pattern found in Xilinx XC-4000 FPGA
architecture, the results are applicable for any other SB
pattern found in bibliography. Different SB topologies
utilize a different number of pass transistors leading to
different interconnection delay and power consumption
values. For example, in a 2D SB an incoming routing track
can be connected to three other wires (F, = 3). Similarly,
for a 3D SB, the incoming routing track is possible to be
connected to five other tracks (F, = 5). In the first case,
the SB is formed by 6 transistors, while in the 3D approach
10 transistors are required. As we target FPGAs, the power
consumption is one of the upmost parameters for reduction
and, therefore, the selection of the appropriate connectivity
across the 3D device layers is essential for efficient
designs. Also, a large number of vias occupies large
portion of Si-area, where active circuits and interconnects
must be excluded. Furthermore, the effect of the
distribution and length of these vias on the performance
and power consumption of 3D FPGAs needs to be
addressed.
The proposed 3D architecture can be constructed by
placing a number of identical 2D individual layers,
providing communication by interlayer vias among
vertically adjacent SBs. Hence, the SBs are extended to the
third dimension, while the structure of the individual logic
blocks remains unchanged.
Based on the required number of interconnections for
the successful implementation of an application onto
FPGAs, the nets can be routed by using various channel
segments to enhance both the delay/power efficiency and
resource utilization. For all of the simulation/evaluation
experiments presented in this work, we use a multisegment routing architecture similar to the one that appears
in the Xilinx Virtex devices for horizontal tracks
(composed from routing segments of lengths LI, L2, L6,
and long lines, while the distribution of the segments in
each channel is 8%, 20%, 60%, and 12% respectively). For
the vias we use segment tracks of LI.
In order to model the vertical wires we assume that
each via is electrically equivalent to a horizontal routing
track with the same length. This means that the vertical
tracks of our 3D FPGA have the same delay and power
values as the horizontal segments with length LI. This
assumption is based on the fabrication process [5], where

__/

Proposed

Synte\sdesign flow

I~~~~ecnlllllgy Mapping

BTtsr
**E
amgeneraio

Figure 1: The MEANDER Framework for 2D/3D FPGAs

The 3D branch adopts some existing CAD tools from

the 2D toolset [12, 13], which do not need to be adapted for
the 3rd dimensional topology. Only the tools which are
related to P&R and power estimation tasks should be
replaced by the new tools, because these tools consider the
particular traits of the 3D FPGAs. More specifically we
develop a 3D Placement and Routing Optimizer (3DPRO).
We also the 3DPower a novel tool to model and estimate
the power/energy consumption in 3D architectures. To best
of our knowledge, this toolset is the first complete
framework in academia for mapping applications onto 3D
FPGAs starting from a high level (HDL) description of the
application and ending up to configuration file generation.
More details about the 3D framework can be found in [10].
3. EXPLORATION AND COMPARISON RESULTS
We performed qualitative comparison between 3DPRO and
the TPR (the only public available tool for P&R on 3D
FPGAs) tool (Table 1). Thus, 3DPRO performs architecture
exploration for a significantly larger number of parameters
as compared to TPR.

The effectiveness of the proposed methodology is

exhibited by exploring several 3D architectures for various
parameters. We performed exploration with the following
assumptions: (i) total number of layers is equal to four, (ii)
percentage of vertical interconnects per layer ranges from
0% (i.e., conventional 2D FPGA) to 100% (TPR solution),
(iii) the spatial location (x, y, z) of each via per layer
remains invariant, (iv) a via connection between adjacent
layers (with length L,) is electrically equivalent to L, wires
formed on the 2D FPGA plane, (v) the via width is W=4 in
any layer, (vi) the hardware resources of each layer are
identical (i.e., identical number of Basic Logic Elements

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(BLEs)) among different layers and (vii) the applications

are implemented onto the smallest number of BLEs per
FPGA layer that can be mapped.
Table 1: Qualitative comparison between TRP and 3DPRO

Feature

TRP
Yes
Yes
Yes
No

Architecture exploration
Measure Delay
Measure Wire length
Measure Power

Supported switch boxes

3DPRO
Yes
Yes
Yes
Yes

Subset
Wilton
Universal

sDpesige
spcfe

No
No

Yes
Yes

No
No

Yes
Yes

Heterogeneous interconnect
(simultaneously 2D/3D SBs)
Vias exploration
Belong to complete framework
Full custom 3D interconnections

Dsge

Assuming a layer of size

and
is the available
3D SBs per layer, the pattern of placement of a 3D SB is
derived as follows: Assigning first a 3D SB to a location
of a certain layer, then the neighboring 3D SBs are
uniformly-assigned to the locations (x+r+1, y, z) where is
derived by
. Alsos r indicates the
number of 2D SBs between two neighboring 3D SBs.
In order to evaluate our methodology we performed an
exhaustive exploration with the 20 largest MCNC
benchmarks. The results are summarized in Figure 4. The
horizontal axis corresponds to the percentage of via
connections in each layer of the 3D FPGA (which is
identical to the percentage of 3D SBs of an FPGA layer),
while the vertical axis shows the normalized value of
EnergyxDelay Product (EDP). These points correspond to
Pareto points showing all of the possible solutions. We
normalize the results with the EDP value of a conventional
(i.e., 2D) FPGA. According to the designer requirements,
similar curves to those in Figure 4 can be derived,
considering, for instance, the energy consumption or
performance as the optimizing parameter of the system.

:=

1.05

L-

1.00

-04

ID95

o.90

Layers _

Ly

2D Solution

Layers

Several conclusions can be drawn from the diagram of

Figure 4. As we increase the number of layers, the
applications are realized with smaller delay for critical nets
and energy consumption in 3D FPGAs. Secondly, we can
claim that the developed P&R tools provide promising
results for such architectures, where only a percentage of
SBs forms 3D via connections. More specifically, for the
three layers solution, as we increase the percentage of 3D
SBs per layer, the EDP value increases. Similarly, the EDP
curve for four layer devices gives two local minima of
30% and 70% of 3D SBs.
Choosing the 3D architecture with the two local
minima EDP values from Figure 4, we performed detail
exploration in terms of the delay, the wire length and the
energy requirement for the chosen benchmarks shown in
Table 2. We compare 2D (conventional) with 3D FPGA
architecture consisting of 4 layers with 30% and 70% of
the SBs of each layer to form 3D connections. The
corresponding values of the delay reduction, the wire
length, and the energy consumption are: 16%, 17%, and
30%, and, 18%, 15%, and 31%. Indeed, the wire length
reduction due to 3D integration results in remarkable
improvements in delay and energy consumption.
Furthermore, in Table 2 the columns with 100% vias
give the calculated values of delay, wire length, and energy
consumption, which correspond to the 3D architectures of
[4]. It can be seen that these average values is similar to the
ones of the explored 3D FPGA architecture results (i.e.,
30% and 70% vias). Specifically, a decrease up to 70% in
the utilized vertical interconnects is observed. The last
point is very important because we achieved the same
improvements employing fewer vias.
For 3-D system, the smaller number of vias means: (i)
lower fabrication costs and (ii) larger useful silicon area in
each layer (a via contact occupies much more silicon area
than a simple metal contact).

--+-"2 Layers"

"3Layers"

4 Layers

ULn

>,B 791

.30)691

""
591
; F

10%

Iso

20%

30%

40%

50%

60%

70%

80%

90%

100%

F fabricated vias
Figure 5: Vertical interconnects utilization

D.75-

1.70

1Q%

20%;

30%D

40%e

50%

607;D

70%o

80%o

90%

% fabricated

The utilization degree of the fabricated vias is shown in

Figure 5. We can infer that the number of actually-utilized
vertical interconnects deviates from the average utilization
degree by a small fraction for a given number of layers.
Considering the number of layers 2, 3, and 4, the
corresponding average values are 2.31%, 3.58% and
4.98%, while the largest deviation from the average values

lo(
vias

Figure 4: Average EDP over the 20 largest MCNC

benchmarks for different number of layers and vias.

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are 0.44%, 0.45% and 2.41%, respectively.

More

specifically, given a certain number of layers, the via

utilization degree remains almost invariant - i.e., it is
relatively independent from the percentage of vias per
layer. We observed in Figure 5 that the utilized via links of
the 4-layer architectures with fabricated 30% and 70% are
4.63% and 4%, respectively, which means both
architectures utilized almost the same number of vias.
4. CONCLUSIONS
A systematic methodology for exploring alternative 3D
FPGA architectures is presented. This methodology is
software supported by two new tools, namely 3DPRO and
3DPower, which belong to the first complete 3D FPGA
Design Framework in academia. Comparison results
indicate improvements up to 18% in the delay, 17% in the
wire length, and 31% in the energy consumption for the
proposed 3D FPGAs as compared to existing 2D FPGAs.

5. ACKNOWLEDGMENTS
The authors acknowledge the support from Prof. K. Bazargan and
H. Mogal (Univ. of Minnesota) about specific parts of TPR tool.

6. REFERENCES

[2] J. W. Joyner et al., "Impact of Three-Dimensional

Architectures on Interconnects in Gigascale Integration",
IEEE Trans. on VLSI, Vol. 9, No. 6, pp. 922-927, Dec. 2001
[3] Kara Poon, et. al., "A Flexible Power Model for FPGA's", in
12th Int. Conf FPL, 2002.
[4] Cristinel Ababei, et. al., "Placement and Routing in 3D
Integrated Circuits", IEEE Design and Test, Vol. 22, No. 6,
pp. 520-53 1, Nov-Dec 2005.
[5] R. Reif, et. al., "Fabrication Technologies for ThreeDimensional Integrated Circuits",in ISQED, pp.33-37, 2002.
[6] Shamik Das, et. al., "Technology, Performance, and
Computer Aided Design of Three Dimensional Integrated
Circuits",Int. Symp. Physical Design, pp. 108-115, 2004.
[7] Arifur Rahman, et. al., "Wiring Requirement and ThreeDimensional
Integration
Technology
for
Field
Programmable Gate Arrays", IEEE Trans. on VLSI, Vol. 11,
No. 1, pp. 44-54, Feb. 2003.
[8] V. F. Pavlidis and E. G. Friedman, "Interconnect Delay
Minimization through Interlayer Via Placement in 3-D ICs",
in Proc. of Great Lakes Symp. on VLSI, pp. 20-25, 2005.
[9] 3D IC Industry Summary, available at "http://www.

tezzaron.com/technology/3D%201C%20Summary.htm".

[10] K. Siozios, et. al., "A Software-Supported Methodology for

Designing High-Performance 3D FPGAs", in Proc. of 15th
IFIP VLSI-SoC, 2007.
[11] S. Yang, "Logic Synthesis and Optimization Benchmarks,
Version 3.0", Techical Report, 1991.
[12] http:Hvlsi.ee.duth.gr/amdrel
[13] K. Siozios, et.al., "An Integrated Framework for
Architecture Level Exploration of Reconfigurable Platform",
in 15th FPL, pp. 658-661, 2005.

[1] Eric Beyne, "The Rise of the 3rd Dimension for System
Integration", in Proc. of 8th EPTC, 2006.

Table 2: Comparison results about MCNC benchmarks: Implementation in 2D and 3D FPGA architecture (with 30/o, 700 and 00/ via
links 4 lavers and minimal EnerrvxDelav Product).

bigkey

6.14

spla

10.8
63.2
14.7
15.3
8.19
26.2
25.3
10.5
31.6
10.9
27.4
26.0
31.6
25.7
15.6
21.4

31.3
8.74
16.7
5.25
24.3
18.8
10.7
30.7
12.0
27.4
27.3
34.7
18.6
12.7
18.3

tcRf nQor

I PI

clma
des
diffeq

dsip
elliptic
exIOlO10
ex5p
frisk
misex3
pdc
s298
s38417
s38584
seq

6.50
9.41
29.1
31.1
9.87
8.67
11.3
18.0
5.80
6.38
22.8
25.6
20.3
20.6
10.4
10.6
32.6
32.3
11.1
10.1
24.6
26.8
21.1
21.9
29.3
31.8
19.4
19.8
14.8
11.6
20.8
18.0
1I 47
7
l1

59.03
379.42
94.07
43.48
53.70
116.14
181.30
42.53
122.70
48.83
257.77
62.12
376.48
225.13
64.36
169.22
7 70

50.57
287.23
54.90
36.97
39.87
93.54
167.22
37.17
110.30
39.08
226.94
57.94
230.61
198.58
52.12
127.94
7A44

51.56
283.19
53.94
45.65
39.53
111.04
164.05
38.19
109.19
39.25
222.49
60.14
259.94
192.200

56.85
127.92
7 X4
T

49.65
283.44
55.03
36.04
38.90
96.04
162.82
36.95
108.89
37.94
228.05
57.82
239.13
191.35
50.69
127.96
7A64

13.6
72.6
22.6
24.3
13.3
20.1
18.5
5.45
35.6
8.37
25.7
14.8
53.2
43.4
9.84
15.9
T77 0

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10.2
45.0
13.0
15.1
7.28
12.9
13.1
4.29
25.1
5.72
23.5
10.4
42.1
30.0
7.29
12.1
w5

10.3
45.0
12.9
12.4
7.27
13.3
13.0
4.77
25.9
5.98
19.9
10.0
43.2
30.4
8.92
13.2
l1 I

10.0
44.5
13.0
11.9
7.15
13.3
12.7
4.14
26.4
5.64
19.2
10.2
43.1
31.1
7.15
12.6
I