Xilinx

Tutorial #4
Michigan State University
Department of Electrical and Computer Engineering

Purpose
The purpose of this project is to help students learn the following:
How to create a timing module
How to create a simple finite state machine
Where to find help
How to define/use a variable
How to use multiple processes in 1 VHDL file
How to use an ELSIF statement
How to use nested loops
How to detect the rising edge of a signal
How to create a clock signal using the force command
How to define your own type

Procedure
1. Create a new project called tutorial4". Be sure to use the same method as Tutorial #1.

2. Add a new VHDL source file. Call this source file mytimer".

3. Add the following STD_LOGIC input ports: clk, reset. Add the following STD_LOGIC output ports:
short, long.

4. We will assume that our main clock is running at 50MHz (20ns per period). This timer will count
the number of clock transitions until 0.025 seconds have elapsed. At that time, the output short
will go high. It will then continue counting until 0.05 seconds have elapsed. At that time, the
output long will go high.

5. For 0.025 seconds, we need approximately 1,250,000 clock periods. For 0.05 seconds, we need
approximately 2,500,000 clock periods.

6. Inside the architecture, define a process whose sensitivity list contains clk.

7. Inside the process (but before the begin statement), define 2 variables of type integer. Call the
variables longtemp and shorttemp. These variables will be used to count the clock periods.

8. After the processs begin statement, use an IF statement to assign a 0 to the outputs (short and
long) if reset=1. Also, initialize our temporary variables (longtemp and shorttemp) to 0.

9. Use an ELSIF branch to check for the rising edge of the clock. The rising edge of the clock occurs
every time the clock signal transitions from a 0 to a 1. In order to understand how we check for
a rising edge, you must understand what an event is. An event is whenever a signal transitions
from either a 0 to 1 OR 1 to 0. In order to detect a rising edge, we first try to detect an event. If
an event occurs, we then check to see if the signals value is a 1. If both are true, we have
found the rising edge of a signal. This detection can be completed with one simple statement:

signalEVENT AND signal=1

This statement is usually placed in parenthesis after an IF or ELSIF command. Be sure to replace
signal with the appropriate signal in the circuit.

10. Inside the ELSIF branch that detects the rising edge of clk, we need 2 nested IF statements. One
will check the count of longtemp while the second will check the count of shorttemp. Once
shorttemp reaches 1,250,000 the output short should go high. Once longtemp reaches
2,500,000 the output long should go high.

11. If neither longtemp nor shorttemp have reached their desired value, add 1 to each variable. Be
sure to end all of your IF statements.

12. Check the syntax.

13. Save your file.

14. Create a do file and test your code. Remember that you have to run it for a little more than 0.05
seconds. The default step in lSim is 100ps. You may want to use a command such as run
0.051sec". It will take time for the simulation to complete. Also be sure to define your 50MHz
clock appropriately. Remember that the period of a 50MHz clock is 20ns (2010!! ). Use a force
command such as:
isim force add {/mytimer/clk} 1 -time 0 ns, -value 0 time 10
ns -repeat 20 ns
This force command states that the clock will be a 1 at 0sec. It will then change to a 0 at 10ns.
Every 20ns it will repeat, thereby giving you a 50MHz clock. More information on the on page
94 of the ISIM User Guide available at
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/plugin_ism.pdf.
15. Print your VHDL file, and waveform (be sure to zoom correctly and print in landscape).

16. Add a new VHDL source file to the project. Call this source file mygcgenerator".
17. Add the following STD_LOGIC input ports: clk, reset, x. Add the following STD_LOGIC_VECTOR
output ports: graycode(2:0). This module will generate gray code in the following orders:

x = 0: 000 001 011 111 101 100 110 010 000
x = 1: 000 001 011 010 110 111 101 100 000

18. The best way to implement a circuit to realize the above criteria is to create a state machine.
The values 000 to 111 will each be a state (there are 8 total). The current state is the 3-bit
output of the circuit (graycode). The next state is dependent on the current state and the input
(x). For example, if the current state is 110 and x = 1, the next state should be 111.

19. Lets try to code this machine using 2 processes (see page 173 of the XST User Guide available at
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/xst.pdf). On page 173, I
want you to notice the following things:

(a) We can have more than 1 process inside an architecture. We have 2 processes in this
example (process1 and process2). Notice how each process is labeled and ended. Notice
that process1 is activated on clk and reset, while process2 is activated on state. Basically,
process1 is there to change the states of the machine, while process2 assigns the outputs
according to the state. This is what is called a Moore Machine.

(b) We can define signals of our own type. So far we have only used signals called STD_LOGIC
and STD_LOGIC_VECTOR. Notice the type statement just below the architecture. This
statement allows us to define signals of type state_type. The only values of these signals are
s1, s2, s3, and s4.

20. In order to successfully code the given state machine, utilize the example on page 189. You will
have to make at least the following changes:

(a) state_type should have 8 states. Label them s0 to s7.
(b) The case statement in process1 needs to have 8 options, all similar to the first when
statement.
(c) The case statement in process2 needs to output 3 bits to graycode. It will also require 8
options instead of 4.
(d) Upon reset, state should become s0.

21. Check the syntax.

22. Save your file.

23. Use the following test of your code:
isim force add {/mytimer/clk} 1 -time 0 ns, -value 0 time 10 ns
-repeat 20 ns
isim force add {/mytimer/reset} 0
isim force add {/mytimer/x} 0
run 50ns
isim force add {/mytimer/reset} 1
3

run 25ns
isim force add {/mytimer/reset} 0
run 180ns
isim force add {/mytimer/x} 1
run 180ns

24. Print your VHDL file and waveform. Be sure to zoom correctly in landscape.