Chapter # 4: Programmable and

Steering Logic
Contemporary Logic Design
Randy H. Katz
University of California, Berkeley
June 1993

No. 4-1

PALs and PLAs

Pre-fabricated building block of many AND/OR
gates (or NOR, NAND) "Personalized" by making
or breaking connections among the gates
Programmable Array Block Diagram for Sum of Products Form

Inputs

Dense array of
AND gates

Product
terms

Dense array of
OR gates

Outputs

No. 4-2

Key to Success: Shared Product Terms

Example:

F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Input Side:

Personality Matrix
Product
term
AB
BC
AC
BC
A

Inputs
A B C
1 1 - 0 1
1 - 0
- 0 0
1 - -

Outputs
F0 F 1 F 2 F 3
0 1 1 0
0 0 0 1
0 1 0 0
1 0 1 0
1 0 0 1

1 = asserted in term
0 = negated in term
- = does not participate
Reuse
of
terms

Output Side:

1 = term connected to output

0 = no connection to output

No. 4-3

Example Continued

All possible connections are available

before programming

No. 4-4

Example Continued

Unwanted connections are "blown"

Note: some array structures

work by making connections
rather than breaking them

No. 4-5

Alternative representation for high fan-in structures

Short-hand notation
so we don't have to
draw all the wires!

Notation for implementing

F0 = A B + A' B
F1 = C D' + C' D

No. 4-6

Design Example
Multiple functions of A, B, C

ABC
A

F1 = A B C

B
C
A

F2 = A + B + C

B
C

F3 = A B C

ABC
ABC
ABC

F4 = A + B + C

ABC
ABC

F5 = A xor B xor C

ABC
ABC

F6 = A xnor B xnor C
F1

F2

F3

F4 F5

F6

No. 4-7

What is difference between Programmable Array Logic (PAL) and

Programmable Logic Array (PLA)?

PAL concept implemented by Monolithic Memories

constrained topology of the OR Array

A given column of the OR array

has access to only a subset of
the possible product terms

PLA concept generalized topologies in AND and OR planes

No. 4-8

Design Example: BCD to Gray Code Converter

A

AB

A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

W
0
0
0
0
0
1
1
1
1
1
X
X
X
X
X
X

X
0
0
0
0
1
1
0
0
0
0
X
X
X
X
X
X

Y
0
0
1
1
1
1
1
1
0
0
X
X
X
X
X
X

Z
0
1
1
0
0
0
0
1
1
0
X
X
X
X
X
X

AB

00

01

11

10

00

01

CD

00

01

11

10

00

01

11

10

CD

D
11

10

D
C

K-map for W

K-map for X

AB

AB

00

01

11

10

00

01

11

10

CD

00

01

11

10

00

01

11

10

CD

W=A+BD+BC

D
C

X = B C
Y=B+C

K-map for Y

K-map for Z

Z = A'B'C'D + B C D + A D' + B' C D'

No. 4-9

Programmed PAL:

0
0
0

0
0
ABCD

4 product terms per each OR gate

No. 4-10

Code Converter Discrete Gate Implementation

\A

B
D

B
C

\A
\B
\C
D

W
B
C
D
A
D

B
C

22

1
X

3
4 4

\D
\B
C
\D

\C

1: 7404 hex inverters

2,5: 7400 quad 2-input NAND
3: 7410 tri 3-input NAND
4: 7420 dual 4-input NAND

\B

4 SSI Packages vs. 1 PLA/PAL Package!

No. 4-11

Another Example: Magnitude Comparator

AB

AB

00

01

11

10

00

01

11

10

CD

01

11

10

00

01

11

ABCD

10

AC

D
C

ABCD

00

CD

ABCD
ABCD
D

K-map for EQ

K-map for NE

AB
01

11

10

00

01

BD

AB

00

CD

AC

BD

00

01

11

10

00

01

CD

ABD
BCD

D
11

ABC

11

10

BCD

C
10

K-map for LT

K-map for GT

EQ NE LT

GT

No. 4-12

Non-Gate Logic

Introduction
AND-OR-Invert
PAL/PLA

Generalized Building Blocks

Beyond Simple Gates

Kinds of "Non-gate logic":

switching circuits built from CMOS transmission gates
multiplexer/selecter functions
decoders
tri-state and open collector gates
read-only memories
No. 4-13

Selection Function/Demultiplexer Function with Transmission Gates

Selector:
Choose I0 if S = 0
Choose I1 if S = 1

S
I

0
S

1
S

Demultiplexer:
I to Z0 if S = 0
I to Z1 if S = 1

Z0
I

S
Z1
S

No. 4-14

Well-formed Switching Networks

Problem with the Demux implementation:
multiple outputs, but only one connected to the input!
S
Z0
S
"0"
I
S

Z1
S
"0"
S

The fix: additional logic to drive every output to a known value

Never allow outputs to "float"

No. 4-15

Multiplexers/Selectors
Multi-point connections

A0

Sa

A1

B0

B1

MUX

MUX

Multiple input sources

Sb

Sum

Ss

DEMUX

S0

Multiple output destinations

S1

No. 4-16

General Concept
2

data inputs, n control inputs, 1 output

n

used to connect 2

points to a single point

control signal pattern form binary index of input connected to output

Z = A' I0 + A I1

A
0
1

Z
I0
I1

Functional form

Logical form

I1
0
0
0
0
1
1
1
1

I0
0
0
1
1
0
0
1
1

A
0
1
0
1
0
1
0
1

Z
0
0
1
0
0
1
1
1

Two alternative forms

for a 2:1 Mux Truth Table
No. 4-17

I0

2:1
mux

I1

Z = A' I 0 +

A I1

A
I0
I1
I2
I3

4:1
mux

Z = A' B' I0 + A' B I1 + A B' I 2 + A B I3

Z = A' B' C' I0 + A' B' C I1 + A' B C' I2 + A' B C I3

+ A B' C' I4 + A B' C I5 + A B C' I6 + A B C I7

I0
I1
I2
I3

8:1
mux

I4
I5
I6
I7

In general, Z =
A

n
2 -1
m I
k=0
k k

n
in minterm shorthand form for a 2 :1 Mux
No. 4-18

Alternative Implementations
A

I0

I1

I2

I3

Gate
GateLevel
Level
Implementation
Implementation
of
of4:1
4:1Mux
Mux

Transmission
TransmissionGate
Gate
Implementation
Implementationof
of
4:1
4:1Mux
Mux

thirty six transistors

twenty transistors
No. 4-19

Large multiplexers can be implemented by cascaded smaller ones

I0
I1
I2
I3

0 4:1
1 mux
2
3 S1 S0

I4
I5
I6
I7

0 4:1
1 mux
2
3 S1 S0
B

Control signals B and C simultaneously

choose one of I0-I3 and I4-I7

8:1
mux
0 2:1
mux
1 S

Control signal A chooses which of the

upper or lower MUX's output to gate to Z
I0

I1

1 S

I2

I3

1 S

0
1

Alternative 8:1 Mux Implementation

I4

I5

1 S

I6

I7

1 S

2
3 S0

S1

C
No. 4-20

Multiplexers/selectors as a general purpose logic block

2

n-1

:1 multiplexer can implement any function of n variables

n-1 control variables; remaining variable is a data input to the mux

Example:

F(A,B,C) = m0 + m2 + m6 + m7
= A' B' C' + A' B C' + A B C' + A B C
= A' B' (C') + A' B (C') + A B' (0) + A B (1)
1
0
1
0
0
0
1
1

0
1
2
3
4
5
6
7

A
0
0
0
0
1
1
1
1

8:1
MUX

S2 S1 S0
A

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

F
1
0
1
0
0
0
1
1

C
C
0
1

C
C
0

0
1
2
3

4:1
MUX
S1

S0

"Lookup Table"
No. 4-21

Generalization

I1 I2

n-1 Mux
control variables

single Mux
data variable

In
0
1

F
0
0

0
1

1
0

1
1

In

In

Four possible
configurations
of the truth table rows
Can be expressed as
a function of In, 0, 1
No. 4-22

Example:
G(A,B,C,D) can be implemented by an 8:1 MUX:

K-map
Choose A,B,C
as control variables

1
D
0
1
D
D
D
D

0
1
2
3
4
5
6
7

8:1
mux

S2
A

S1
B

S0
C

Multiplexer
Implementation

TTL
TTLpackage
packageefficient
efficient
May
Maybe
begate
gateinefficient
inefficient
No. 4-23

Decoders/Demultiplexers
Decoder: single data input, n control inputs, 2 n outputs
- control inputs (called select S) represent Binary index of
output to which the input is connected
- data input usually called "enable" (G)
1:2 Decoder:

3:8 Decoder:
O0 = G S0 S1 S2

O0 = G S; O1 = G S
O1 = G S0 S1 S2

2:4 Decoder:

O2 = G S0 S1 S2

O0 = G S0 S1

O3 = G S0 S1 S2

O1 = G S0 S1

O4 = G S0 S1 S2

O2 = G S0 S1

O5 = G S0 S1 S2

O3 = G S0 S1

O6 = G S0 S1 S2
O7 = G S0 S1 S2
No. 4-24

Alternative Implementations
G

Output0

Select

/G
Select

Output0
Output1

Output1

1:2 Decoder, Active Low Enable

1:2 Decoder, Active High Enable

/G

Select0

Output0

Output0

Output1

Output1

Output2

Output2

Output3

Output3

Select0

Select1

2:4 Decoder, Active High Enable

Select1

2:4 Decoder, Active Low Enable

No. 4-25

Switch Logic Implementations

Select

Select
G

Output

Output
0
Select
Select

Select
Select
"0"
Select

Output
1

Select

Select

Output

Select

Naive, Incorrect Implementation

Select

All outputs not driven at all times

"0"
Select

Correct 1:2 Decoder Implementation

No. 4-26

Switch Implementation of 2:4 Decoder

Select

Select

Output

Operation of 2:4 Decoder

"0"
"0"

S0 = 0, S1 = 0

Output
1

"0"

one straight thru path

three diagonal paths

"0"

Output

"0"
"0"

Output

"0"
"0"

No. 4-27

Decoder as a Logic Building Block

0
1
Enb

3:8
dec

S2
A

S1
B

S0

2
3
4
5
6
7

ABC
ABC
ABC
ABC
ABC
ABC

Decoder Generates Appropriate

Minterm based on Control Signals

ABC
ABC

Example Function:
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D' + A B C
F3 = (A' + B' + C' + D')

No. 4-28

Decoder/Demultiplexer
Decoder as a Logic Building Block

Enb

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

4:16
dec

S3 S2 S1 S0
A

B C

A BCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD
ABCD

F1

F2

ABCD
ABCD
ABCD
ABCD

F3

If active low enable, then use NAND gates!

No. 4-29

Multiplexers/Decoders
Alternative Implementations of 32:1 Mux

I7
I6
I5
I4
I3
I2
I1
I0
C
D
E

EN
I31 7 151
EN 1 6
5
1
Y5
I23 7 151
41 4
6
3
W 6
EN 1 5 52 2
1 4
3 1Y 5
I15 7 151
4
40
1 6 51 3
6
W
EN 1 5
22
3
3 1 Y 19
1 4
5C
7 151
4
B
4 0W 1 6A
6 51 3
22
5
9C 0
1
3
1
5B
4
4 0Y 1
13
1 6A
W0
2
9
1
1 1 C
B
0 1A
S2 0
1
S1
S0

A
B

1 GA
3 A3
4 A2
5 A1
6 A0
13
12
11
10
1
5

Multiplexer Only

153
YA 7

B3
B2
YB 9
B1
B0
GBS1SO
2 14
A B

F(A, B, C, D, E)

1 1G 1Y3
1Y2
3 139
1B
2 1A 1Y1
1Y0
15 2G 2Y3
2Y2
13 2B 2Y1
14 2A 2Y0

7
6
5
4
9
10
11
12

7 EN 146
5
154
I31 7 151
13
6
7 EN
22
I5 145
3
154
I23 7 I4151
1 5
40 Y
3
7 EN 146 I3 1
W 6
I5 5 I2 2 2
9
154 I1 3 1 Y 10
5C
I15 7 I4151
B
4
1
I3
3
I0
0
7 EN 146
W 116A
I5 5 I2 2 2 C 9 C
S2
154 I1 3 1Y 10
5 S1
I7 7 I4 151
D 116B
I6 6 I3 1 3 I0 4 0W
A
I5 5 I2 2 2 C 9 C
S2E S0
5B
I4 4 I1 3 1 Y 10
D 11S1
I3 3 I0 4 0 W
6A
I2 2 C 9 C
S2E S0
I1 1 10B
S1
I0 0 D 11A
C S2E S0
D S1
E S0

F(A, B, C, D, E)

Multiplexer + Decoder

No. 4-30

Multiplexers/Decoders
5:32 Decoder
\EN
S4
S3

1G 1Y3
139 1Y2
1B 1Y1
1A 1Y0
2G 2Y3
2Y2
2B 2Y1
2A 2Y0

\EN

S2
S1
S0

\Y31
5:32
Decoder
Subsystem

.
.
.

S2
S1
S0

\Y0
S4 S3 S2 S1 S0
S2
S1
S0

S2
S1
S0

G1
G2A
G2B

Y7
Y6
Y5
Y4
138 Y3
Y2
C
Y1
B
Y0
A

\Y31
\Y30
\Y29
\Y28
\Y27
\Y26
\Y25
\Y24

Y7
G1
G2A Y6
G2B Y5
Y4
138 Y3
Y2
C
Y1
B
Y0
A

\Y23
\Y22
\Y21
\Y20
\Y19
\Y18
\Y17
\Y16

Y7
G1
G2A Y6
G2B Y5
138 Y4
Y3
C
Y2
Y1
B
Y0
A

\Y15
\Y14
\Y13
\Y12
\Y11
\Y10
\Y9
\Y8

G1 Y7
G2A Y6
G2B Y5
138 Y4
Y3
Y2
C
Y1
B
Y0
A

\Y7
\Y6
\Y5
\Y4
\Y3
\Y2
\Y1
\Y0

No. 4-31

Tri-State and Open-Collector

The Third State
Logic States: "0", "1"
Don't Care/Don't Know State: "X" (must be some value in real circuit!)
Third State: "Z" high impedance infinite resistance, no connection
Tri-state gates: output values are "0", "1", and "Z"
additional input: output enable (OE)

A OE F
X 0 Z
0 1 0
1 1 1

When OE is high, this gate is a non-inverting "buffer"

When OE is low, it is as though the gate was
disconnected from the output!
This allows more than one gate to be connected to the
same output wire, as long as only one has its
output enabled at the same time
100

Non-inverting buffer's
timing waveform

A
OE
F

"Z"

"Z"
No. 4-32

Tri-state and Open Collector

Using tri-state gates to implement an economical multiplexer:
Input

OE
Input

When SelectInput is asserted high

Input1 is connected to F

When SelectInput is driven low

Input0 is connected to F

OE

This is essentially a 2:1 Mux

SelectInput

No. 4-33

Tri-state and Open Collector

Alternative Tri-state Fragment
Input

Active low tri-state enables

plus inverting tri-state buffers

OE
Input

OE

SelectInput
F

I
OE

Switch Level Implementation

of tri-state gate

0
No. 4-34

Tri-State and Open Collector

4:1 Multiplexer, Revisited

\EN
S1
S0

1G 1Y3
1Y2
3 139 1Y1
2 1B
1A 1Y0

15

2G 2Y3
2Y2
13 2B 2Y1
14 2A 2Y0

7
6
5
4
9
10
11
12

D3

D2

D1

D0

Decoder + 4 tri-state Gates

No. 4-35

Tri-State and Open Collector

Open Collector
another way to connect multiple gates to the same output wire
gate only has the ability to pull its output low; it cannot actively
drive the wire high
this is done by pulling the wire up to a logic 1 voltage through a
resistor
+5 V
Pull-up resistor
Open-collector
NAND gate
F
0V
A

OC NAND gates
Wired AND:
If A and B are "1", output is actively pulled low
if C and D are "1", output is actively pulled low
if one gate is low, the other high, then low wins
if both gates are "1", the output floats, pulled
high by resistor
Hence, the two NAND functions are AND'd
together!

No. 4-36

Tri-State and Open Collector

4:1 Multiplexer

\EN 1

Y3
139 Y2
Y1
S1 3 B
Y0
S0 2 A
G

+5V

7
6
5
4
\I3

OR

\I2

OR

\I1

OR

\I0

OR

Decoder + 4 Open Collector Gates

No. 4-37

Read-Only Memories
ROM: Two dimensional array of 1's and 0's
Row is called a "word"; index is called an "address"
Width of row is called bit-width or wordsize
Address is input, selected word is output
+5V +5V +5V +5V

n
2 -1

Dec

Word Line 0011

Word Line 1010

n-1

Bit Lines

Address

Internal Organization

No. 4-38

Read-Only Memories
Example: Combination Logic Implementation
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A
0
0
0
0
1
1
1
1

Address

ROM
8 w ords by
4 bits

A B C
address

F0

F1

F2

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

F0
0
1
0
0
1
1
0
0

F1
0
1
1
0
0
0
0
1

F2
1
1
0
0
1
0
0
0

F3
0
0
0
1
1
0
1
0

Word Contents

F3

outputs
No. 4-39

Read-Only Memories
Memory array

Not
Notunlike
unlikeaaPLA
PLA
structure
structurewith
withaa
fully
fullydecoded
decoded
AND
ANDarray!
array!

Decoder

2n word
lines

n address
lines

2n words by
m bits

m output
lines

ROM vs. PLA:

ROM approach advantageous when
(1) design time is short (no need to minimize output functions)
(2) most input combinations are needed (e.g., code converters)
(3) little sharing of product terms among output functions
ROM problem: size doubles for each additional input, can't use don't cares
PLA approach advantangeous when
(1) design tool like espresso is available
(2) there are relatively few unique minterm combinations
(3) many minterms are shared among the output functions
PAL problem: constrained fan-ins on OR planes
No. 4-40

Read-Only Memories
2764 EPROM
8K x 8
2764
VPP
PGM
A12
A11
A10 O7
A9
O6
A8
O5
A7
O4
A6
O3
A5
O2
A4
O1
A3
O0
A2
A1
A0
CS
OE

2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U3
OE

A13
/OE
A12:A0
D15:D8
D7:D0
+

2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U2
OE

2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U1
OE

2764
VPP
PGM
A12
A11
A10 O7
A9 O6
A8 O5
A7 O4
A6 O3
A5 O2
A4 O1
A3 O0
A2
A1
A0
CS U0
OE

16K x 16
Subsystem
No. 4-41

Combinational Logic Word Problems

General Design Procedure
1. Understand the Problem
what is the circuit supposed to do?
write down inputs (data, control) and outputs
draw block diagram or other picture
2. Formulate the Problem in terms of a truth table or other suitable
design representation
truth table or waveform diagram
3. Choose Implementation Target
ROM, PAL, PLA, Mux, Decoder + OR, Discrete Gates
4. Follow Implementation Procedure
K-maps, espresso, misII

No. 4-42

Combinational Logic Word Problems

Process Line Control Problem
Statement of the Problem
Rods of varying length (+/-10%) travel on conveyor belt
Mechanical arm pushes rods within spec (+/-5%) to one side
Second arm pushes rods too long to other side
Rods too short stay on belt
3 light barriers (light source + photocell) as sensors
Design combinational logic to activate the arms
Understanding the Problem
Inputs are three sensors, outputs are two arm control signals
Assume sensor reads "1" when tripped, "0" otherwise
Call sensors A, B, C
Draw a picture!

No. 4-43

Combinational Logic Word Problems

Process Control Problem
+10%
+ 5%

+ 5%

Spec

Spec

Spec

- 5%

- 5%
- 10%

ROD
Too
Long

ROD
Within
Spec

ROD
Too
Short

Where to place the light sensors A, B, and C to distinguish among

the three cases?
Assume that A detects the leading edge of the rod on the conveyor

No. 4-44

Combinational Logic Word Problems

Process Control Problem
A

Too
Long

Too
Short

Within
Spec

Spectification
- 5%
Specification
+ 5%

A to B distance place apart at specification - 5%

A to C distance placed apart at specification +5%

No. 4-45

Combinational Logic Word Problems

Process Control Problem

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

Function
X
X
X
X
too short
X
in spec
too long

Truth table and logic implementation

now straightforward
"too long" = A B C
(all three sensors tripped)
"in spec" = A B C'
(first two sensors tripped)

No. 4-46

Combinational Logic Word Problems

BCD to 7 Segment Display Controller
Understanding the problem:
input is a 4 bit bcd digit
output is the control signals for the display
4 inputs A, B, C, D
7-Segment
display

7 outputs C0 C6

C0 C1 C2 C3 C4 C5 C6

C0
C5

C6
C4
C3

C1

BCD-to-7-segment
control signal
decoder

C2

C C C C C C C
0 1 2 3 4 5 6

Block Diagram
No. 4-47

Combinational Logic Word Problems

BCD to 7 Segment Display Controller
Formulate the problem in terms of a
truth table

Choose implementation target:

if ROM, we are done
don't cares imply PAL/PLA may be
attractive
Follow implementation procedure:
hand reduced K-maps
vs.
espresso

No. 4-48

Combinational Logic Word Problems

BCD to 7 Segment Display Controller
A

AB

AB

00

01

11

10

00

01

11

10

CD

01

11

10

00

01

11

10

10

00

01

11

10

D
C

K-map for C1

K-map for C2

AB

00

01

11

10

00

01

11

01

11

10

00

01

11

01

11

10

00

01

11

00

01

11

10

00

01

11

10

CD

D
C

C
10

AB

00

CD

C
1

AB

00

CD

11

K-map for C0
AB

10

01

D
C

CD

00

CD

D
C

AB

00

CD

10

K-map for C3

K-map for C4

K-map for C5

K-map for C6

C0 = A + B D + C + B' D'
C1 = A + C' D' + C D + B'
C2 = A + B + C' + D

C3 = B' D' + C D' + B C' D + B' C

C4 = B' D' + C D
C5 = A + C' D' + B D' + B C'
C6 = A + C D' + B C' + B' C

14 Unique Product Terms

No. 4-49

Combinational Logic Word Problems

BCD to 7 Segment
Display Controller
Increment

First
fuse
numbers

12

16

20

24

28

0
32
64
96
128
160
192
224

19

256
288
320
352
384
416
448
480

18

512
544
576
608
640
672
704
736

17

768
800
832
864
896
928
960
992

16

1024
1056
1088
1120
1152
1184
1216
1248

15

1280
1312
1344
1376
1408
1440
1472
1504

14

1536
1568
1600
1632
1664
1696
1728
1760

13

16H8PAL
Can Implement
the function

8
1792
1824
1856
1888
1920
1952
1984
2016

12

11
Note: Fuse number = first fuse number + increment

No. 4-50

Combinational Logic Word Problems

BCD to 7 Segment
Display Controller
Increment

01 2 3

10

12

14

16

18

20

24

27

First
fuse
numbers

14H8PAL
Cannot Implement
the function

23

0
28
56
84

22
1

112
140

21

168
196

20

224
252

19

280
308

18

336
364

17

392
420

16

448
476
504
532

15

10

14

11

13

Note: Fuse number = first fuse number + increment

No. 4-51

Combinational Logic Word Problems

BCD to 7 Segment Display Controller
PLA Implementation

No. 4-52

Combinational Logic Word Problems

BCD to7 Segment Display Controller
Multilevel Implementation
X = C' + D'
Y = B' C'
C0 = C3 + A' B X' + A D Y
C1 = Y + A' C5' + C' D' C6
C2 = C5 + A' B' D + A' C D
C3 = C4 + B D C5 + A' B' X'

52 literals
33 gates
Ineffective use of don't cares

C4 = D' Y + A' C D'

C5 = C' C4 + A Y + A' B X
C6 = A C4 + C C5 + C4' C5 + A' B' C

No. 4-53

Combinational Logic Word Problems

Logical Function Unit
Statement of the Problem:

3 control inputs: C0, C1, C2

2 data inputs: A, B
1 output: F

No. 4-54

Combinational Logic Word Problems

Logical Function Unit
Formulate as a truth table
Choose implementation technology
5-variable K-map
espresso
multiplexor implementation
A
B

4 TTL packages:
4 x 2-input NAND
4 x 2-input NOR
2 x 2-input XOR
8:1 MUX

A
B
A
B
+
5
V

DD D D D D D D S
01 2 3 4 5 6 7 0
S
E
1
N
Q
S
O
2

C2
C1
C0

F
No. 4-55

Combinational Logic Word Problems

Logical Function Unit
Follow implementation procedure
C1 C 2
00
00 1

AB
C 0=0

01

11
10

1
1

11

10
1
1

C1 C 2
00
00 1

F = C2' A' B' + C0' A B'

+ C0' A' B + C1' A B
5 gates, 5 inverters

AB
C 0=1

01

01

11

Also four packages:

4 x 3-input NAND
1 x 4-input NAND
10
1

Alternative: 32 x 1-bit ROM

01

single package
11

10

No. 4-56

Device A - 1st
Device B - 2nd
Device C - 3rd
Device D - 4th

Device B
RB

OB

SB

Device C
RC

OC

SC

RD

RA

Device A

OD

OA

Device D

Priority Multiplexer
SD

SA

OUTPUT

The Priority Mux connects a device output (OA, OB, OC, OD) to the
output line (OUTPUT) based on priorities. Each device has a request
line (RA, RB, RC, RD) that is asserted when the system output line is
requested by that device. The Mux must return a signal (SA, SB, SC,
SD) to each device indicating whether the request was accepted.
These signals should be asserted only if a request has been received
from the device and the device output has been connected to the
system output.
No. 4-57

7-Level Priority Encoder

Enable
Inactive

7
6

Inputs

7-LPE

4
3

MSB

2
1

LSB

The output of this Priority Encoder represent the binary

code of the highest asserted input at any point in time.
The Inactive output indicates when no input is asserted.

No. 4-58

Chapter Review

Non-Simple Gate Logic Building Blocks:

PALs/PLAs
Multiplexers/Selecters
Decoders
ROMs
Tri-state, Open Collector

Combinational Word Problems:

Understand the Problem
Formulate in terms of a Truth Table
Choose implementation technology
Implement by following the design procedure
No. 4-59