MKCE-ECE

VLSI Design
Unit-2
MOSFET TRANSISTOR
2 MARK QUESTIONS & ANSWERS:
1. What is MOSFET?(Apr/May 2011)
Metal oxide semiconductor field effect transistor. A type of transistor that is
controlled by voltage rather than current.
2. What is the fundamental goal in Device modeling?
To obtain the functional relationship among the terminal electrical variables of the
device that is to be modeled.
3. Define Short Channel devices?
Transistors with Channel length less than 3- 5 microns are termed as Short
channel devices. With short channel devices the ratio between the lateral & vertical
dimensions are reduced.
4. What is pull down device? [Nov/Dec-2009]
A device connected so as to pull the output voltage to the lower supply voltage
usually 0V is called pull down device.
5. What is pull up device?
A device connected so as to pull the output voltage to the upper supply voltage
usually VDD is called pull up device.
6. Why NMOS technology is preferred more than PMOS technology?
N- Channel transistors has greater switching speed when compared tp PMOS
transistors.
7. What are the different operating regions for an MOS transistor?
a. Cutoff region
b. Non- Saturated Region
c. Saturated Region
8. What are the different MOS layers?
a. n-diffusion
b. p-diffusion
c. Polysilicon
d. Metal

9. What are the different operating regions for an NMOS transistor?

a. Accumulation Mode.
b. Depletion Mode
c. Inversion Mode
10. Compare between CMOS and bipolar technologies. (Nov 2007)
CMOS Technology Bipolar technology
Low static power dissipation
High input impedance (low drive current)
Scalable threshold voltage
High noise margin
High packing density
High delay sensitivity to load (fan-out limitations)
Low output drive current
Low gm (gm V
in)
11. Define Threshold voltage in CMOS. (Dec 2006)
The Threshold voltage, VT for a MOS transistor can be defined as the voltage
applied between the gate and the source of the MOS transistor below which the drain to
source current, IDS effectively drops to zero.
12. Define the mos equation
Ids=

0
Vgs<Vt
(Vgs-Vt-Vds/2) Vds<Vdsat
(Vgs-Vt)2
Vds>Vdsat

13. What are the parameters depending on threshold voltage?

a. Gate material
b. Gate insulator
c. Insulator thickness
d. Voltage at source and substrate.
14. What is Body effect? [May/June 2010], [April/May2010]
The threshold voltage VT is not a constant w. r. to the voltage difference between
the substrate and the source of MOS transistor. This effect is called substrate-bias effect
or body effect.
15. What is Channel-length modulation? (Nov/Dec 2010)
The current between drain and source terminals is constant and independent of the
applied voltage over the terminals. This is not entirely correct. The effective length of the
conductive channel is actually modulated by the applied VDS, increasing VDS causes the

depletion region at the drain junction to grow, reducing the length of the effective
channel.
16. Define Rise time (Dec 2008)
Rise time is the time taken for a waveform to rise from 10% to 90% of its steadystate value.
17. Define Fall time (Dec 2008)
Fall time is the time taken for a waveform to fall from 90% to 10% of its steady-state
value.
18. Define Delay time
Delay time is the time difference between input transition (50%) and the 50%
output level. This is the time taken for a logic transition to pass from input to output.
19. What are two components of Power dissipation?
There are two components that establish the amount of power dissipated in a
CMOS circuit. These are:
i) Static dissipation due to leakage current or other current drawn
Continuously from the power supply.
ii) Dynamic dissipation due to
Switching transient current
Charging and discharging of load capacitances.
20. Define mobility. (Dec 2006)
Mobility is defined as average carrier drift velocity to electric field. It is expressed
in cm -2/V sec
21. Give the expression for power dissipation in Cmos inverter (Dec 2008)
P total=P static+P dyn+P shortckt
Psc=I mean.V dd
P dynamic=C Vdd2. fss
22. Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the voltage
applied between the gate and the source of the MOS transistor below which the drain to
source current, IDS effectively drops to zero.
23. What is Latch up?
Latch up is a condition in which the parasitic components give rise to the
establishment of low resistance conducting paths between VDD and VSS with disastrous
results. Careful control during fabrication is necessary to avoid this problem.

24. What is effective channel length?

A new definition of Leff which agrees well with electrical measurements using the
channel resistance method is proposed, based on numerically simulated surface potential.
Using the Leff definition, the physics underlying the fact that Leff can be considerably
longer than the metallurgical channel length Leff is explored, and the independence of Leff
on substrate bias Vsub is clarified.
25. Why NMOS technology is preferred more than PMOS technology?
N- Channel transistors has greater switching speed when compared tp PMOS
transistors.
26. What are the different operating regions fore an MOS transistor?
Cutoff region
Non- Saturated Region
Saturated Region
27. What is mean by CMOS?
Complementary Metal Oxide Semiconductor structure; consists of N-channel and
P-channel MOS transistors; due to very low power consumption and dissipation as well
minimization of the current in "off" state CMOS is a very effective device configuration
for implementation of digital functions; CMOS is a key device in state-of-the-art silicon
microelectronics.
28. What is mean by CMOS inverter? (Apr/May 2011)
A pair of two complementary transistors (a p-channel and an n-channel) with the
source of the n-channel transistor connected to the drain of the p-channel one and the
gates connected to each other. The output (drain of the p-channel transistor) is high
whenever the input (gate) is low and the other way round. CMOS inverter is the basic
building block of CMOS digital circuits.
29. What is mean by bulk?
The p-type substrate is referred to as bulk.
CMOS circuitry implemented on a standard bulk Si wafer rather than in a thin layer of
active Si on insulator (SOI substrate).
30. What is mean by Breakdown? (Apr/May 2010)
A condition that occurs when maximum reverse voltage in a diode is exceeded.
Breakdown will cause a diode to fail and pass a large amount of current in the reverse
direction.

12 MARK QUESTIONS:
1. Explain about the MOSFET operation. Pg No: [108 118] (Apr/May 2010)
Book: John P.Uyemura
2. Explain about the MOSFET switch model. Pg No: [119 120]
Book: John P.Uyemura
3. Explain about the square law model. Pg No: [121 125] (Apr/May 2011)
Book: John P.Uyemura
4. Explain the MOSFET parasitic. Pg No: [126 131] (Apr/May 2011)
Book: John P.Uyemura
5. Explain the MOSFET SPICE modeling. Pg No: [134 136]
Book: John P.Uyemura
6. Explain the CMOS inverter and voltage transfer curve. Pg No: [157 168]
Book: John P.Uyemura
7. Explain about body effect and channel length modulation (Dec 2006)
Pg No: [121 126] Book: John P.Uyemura
8. What do you mean by latch-up in CMOS circuits and explain the latch up
prevention techniques? (Dec 2007), [May/June2010] [Refer Notes]
Text Book: Chip design for submicron VLSI; Author: John P.Uyemura