There are two basic reasons for the preference for NPN BJTs over PNP devices:

The mobility of N type charge current carriers (negative electrons) in silicon (Si) is more than two
times greater than the mobility of P type charge carriers (positive holes) in Si. Resulting in faster
transistor operating speed.
The mass processing of Si based BJTs and integrated circuits (ICs) are most economically
manufactured using large N type silicon wafers.
mre from this link:
http://www.madsci.org/posts/archives/2003-05/1051807147.Ph.r.html

CMOS is preffered over NMOS

as CMOS propogates both logic '1', and '0', without a voltage drop
when using NMOS only, logic '1' (i.e Vdd) suffers a thresold drop and the output after passing through
one NMOS gate would be Vdd-Vt(thresold voltage of the NMOS gate).
Hence signal margin is very important in NMOS causing possible SI(signal integrity) issues.
Hence CMOS is preferred. By the way CMOS and NMOS and also PMOS are all low powered. Static
power consumption is the same, dynamic power consumption depends on signal swing (i.e number of
times data line varies)

Murali

Oct 20th, 2011

The most important advantage of CMOS is the very low static power consumption in compare with
NMOS technology.
CMOS provides more noise margin than NMOS.