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Abstract On chip routers typically have buffers dedicated to their input or output ports for temporarily storing packets
in case contention occurs. Buffers consume significant portions of router area. While running a traffic trace, however not
all input ports of routers have incoming packets needed to be transferred simultaneously. So large numbers of buffer
queues in the network are empty and other queues are mostly busy. This observation motivates us to design Router
architecture with Shared Queues (RoShaQ), router architecture that maximizes buffer utilization by allowing the sharing
multiple buffer queues among input ports. In the network design of the NoC the most essential things are a network
topology and a routing algorithm. Routers route the packets based on the algorithm that they use. Every system has its
own requirements for the routing algorithm. A new adaptive weighted XY routing algorithm for eight port router
Architecture is proposed in order to decrease the latency of the network on chip router.
Index Terms adaptive weighted routing, Networks on Chip, router architecture, shared buffer.
1 INTRODUCTION
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2.
3.
Input queue, output port, and shared queue states maintain the status
(idle, wait, or busy) of all queues and output ports, and incorporate
with SQA and OPA to control the overall operation of the router
Only input queues of RoShaQ have routing computation logic
because packets in the shared queues were written from input queues
hence they already have their output port information. RoShaQ has
the same I/O interface as a typical router that means they have the
same number of I/O channels with it level ow control and credit
based backpressure management.
BN | yd y | + Bmax,
WN = 0,
BN,
yd y < 0
BN < Bp
else
(1)
BS ( yd y ) + Bmax,
WS= 0,
BS,
yd y < 0
BS < Bp
else
(2)
BW | xd x | + Bmax,
WW= 0,
BW,
xd x < 0
BW < Bp
else
(3)
BE ( xd x ) + Bmax,
WE= 0,
BE,
xd x < 0
BE < Bp
else
(4)
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(5)
else
Fig.5.shows the RTL schematic diagram in which it indicates clearly
(6)
(7)
(8)
6 CONCLUSION
In this paper, an eight port networks on chip router using shared buffer
was proposed. A new routing algorithm that supports real-time traffic
direction arbitration while avoiding deadlock and starvation has been
Fig.4. Northwest port Output.
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REFERENCES
[1] A. Banerjee, P. T. Wolkotte, R. D. Mullins, S. W. Moore, and G. J. M. Smit,
An energy and performance exploration of network-on- chip
architectures, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17,
no. 3, pp. 319329, Mar. 2009.
[2] E. Beigne, An asynchronous power aware and adaptive NoC based
circuit, IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 11671177,
Apr. 2009.
[3] D. Bertozzi, A. Jalabert, S. Murali, R. Tamhankar, S. Stergiou, L.
Benini, and G. De Micheli, NoC synthesis ow for customized
domain specic multiprocessor systems-on-chip, IEEE Trans.
Parallel Distrib. Syst., vol. 16, no. 2, pp. 113129, Feb. 2005.
[4] A.Bianco, P. Giaccone, G. Masera, and M. Ricca, Power control
for crossbar-base queued Switches, IEEE Trans. Comput., vol .
62,no.1, pp. 74-84, Jan. 2013.
[5] S.T. Chuang, A. Goel, N. McKeown, and B. Prabhakar, Matching
output queueing with a combined input/output-queued switch,
IEEE J. Selected Areas Commun., vol. 17, no. 6, pp. 10301039,
Jun. 1999.
[6] M. Galles, Spider: A high-speed network interconnect, IEEE Micro,
vol. 17, no. 1, pp. 3439, Jan. 1997.
[7] D. Gebhardt, J. You, and K. S. Stevens, Design of an energy-efcient
asynchronous NoC and its optimization tools for heterogeneous
SoCs, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol.
30, no. 9, pp. 13871399, Sep. 2011.
[8] O. He, S. Dong, W. Jang, J. Bian, and D. Z. Pan, UNISM: Unied
scheduling and mapping for general networks on chip, IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 8, pp. 14961509,
Aug. 2012.
[9] M. G. Hluchyj and M. J. Karol, Queueing in high-performance
packet switching, IEEE J. Sel. Areas Commun., vol. 6, no. 9, pp.
15871597, Dec. 1988.
[10] J.Hu and R.Marculescu , Energy-and Performance-aware mapping
For NOC architecture, IEEE Trans. Comput-Aided Design Integr
Circuits Syst., vol. 24,
no. 4, pp. 551562, Apr. 2005.
[11] H. Ito, M. Kimura, K. Miyashita, T. Ishii, K. Okada, and K. Masu,
A bi- directional and multi-drop-transmission-line interconnect for
multipoint- to-multipoint on-chip communications, IEEE J. SolidState Circuits, vol. 43, no. 4 pp. 10201029, Apr. 2008.
[12] J. Kim, C. Nicopoulos, P. Dongkook, V. Narayanan, M. S. Yousif,
and C. R. Das, A gracefully degrading and energy-efcient modular
router architecture for on-chip networks, in Proc. 33rd IEEE/ACM
ISCA, Jun. 2006, pp. 415.
[13] A. Kumar, L.S. Peh, P. Kundu, and N. K. Jha, Towards ideal onchip communication using express virtual channels, IEEE Micro,
vol. 28, no. 1, pp. 8090, Jan. 2008.
[14] Y.C. Lan, H.A. Lin, S.H. Lo, Y. H. Hu, and S.J. Chen, A
bidirectional Noc(BiNoC) architecture with dynamic selfreconfigurable channel,IEEE Trans.Comput. Aided Design Integr.
Circuits Syst., vol. 30, no. 3, pp. 427440, Mar. 2011.
[15] B. Lin and I. Keslassy, The concurrent matching switch
89