Static Timing Analysis Facts

1.
Static Timing Analysis is a technique of analysing timing paths in a digitallogic by adding up
delays along a timing path (gates and interconnect) and comparingit with constraints (like
clock period) to check whether the path meets the constraint.2.
Static Timing Analysis is popular because it is simple to use and only needscommonly
available inputs like technology library, netlist, constraints, andparasitics(R and C).3.
Static Timing Analysis tend to be comprehensive and provides a very high level of timing
coverage. Static Timing also honours timing exception to exclude the pathsthat are either not
true path are not exercised in an actual design. A good static timingtool corelates well with
timing in silicon.4.
A digital logic can be broken down into a number of timing paths. A timing path canbe any of
the following:i.
a path between the clock pin of register/latch to the d-pin of anotherregister/latch.ii.
a path between primary input to the d-pin of a register or latch.iii.
a path between clock-pin of a register to a primary output.iv.
a path between input pin and output pin of a block.5.
Static Timing Analysis is used to check the following:i.
Setup Timingii.
Hold timingiii.
max/min timing between two points on a segment of timing path.iv.
Latch Time Borrowingv.
Removal and Recovery Timing on resetsvi.
clock gating checksvii.
clock pulse width requirmentsviii.
min max transition timesix.
min/max fanoutx.
max capacitance6.

Capture edge time of a setup path = launch clock edge time + 1 period7.
Max Timing Equation
Launch time clock edge + clock network delay + clock-q delay + path delay (cell
+internconnect)
=<
(capture edge time of setup path) + clock network delay - clock uncertainty- setup time output external delay (only for paths to output ports) 7.
Min Timing EquationLaunch clock edge + clock network delay + input external delay +
clock-q delay + path delay
(cell + internconnect delays)
>=
(Capture edge time of the corresponding setup path - 1clock period) + clock network delay +
clock uncertainty + library hold time - output externaldelays (only for paths to output port) 8.
Capture edge time of a setup path = launch clock edge time + 1 period9.
Multicycle paths are paths that are allowed to take more than one clock period tocomplete.
Multicycle paths make setup easy but hold difficult unless corrected.10.
Recovery time is like setup time on a reset pin.11.
Removal time is like hold time on a reset pin