Escolar Documentos
Profissional Documentos
Cultura Documentos
Volume
No.2, March
April
2015 4(2), March - April 2015, 36 - 43
Vikas Shinde, International Journal of Advanced
Trends4,
in Computer
Science- and
Engineering,
ABSTRACT
power, etc.
1.
INTRODUCTION
the
jobs.
As
parallel
computing
systems
processing
programs,
the
compilers,
etc.,)
and
on
36
systems
via
queue
theoretic
Vikas Shinde, International Journal of Advanced Trends in Computer Science and Engineering, 4(2), March - April 2015, 36 - 43
heterogeneous processors.
accelerator
adequately
section 4.
demanding
studied
design
method
embedded
that
applications.
communication
Jan
architectures
[7]
for
2. MODEL DESCRIPTION
as illustrated in figure 1.
was
implemented
queueing.
Tomic
using
machine repair
[14]
gave
the
which
matrix
element (PE).
37
Vikas Shinde, International Journal of Advanced Trends in Computer Science and Engineering, 4(2), March - April 2015, 36 - 43
PE1
PE2
PE3
PEn
Interconnection network N
Memory M
SM1
P1
LM2
P2
LMN
I/O
PN
38
Manager
Vikas Shinde, International Journal of Advanced Trends in Computer Science and Engineering, 4(2), March - April 2015, 36 - 43
SM2
SM1
I/ O
Cluster 2
Manager
HCN 1
VCN 1
cluster in i
th
39
Vikas Shinde, International Journal of Advanced Trends in Computer Science and Engineering, 4(2), March - April 2015, 36 - 43
SMi
I/OCi-1
PCi-1
MCi-1
PCi-1
have
other
parameter .
jobs.
Therefore several
queues can
be
each
basic cluster.
shared memories.
exponentially
distributed
with
40
Vikas Shinde, International Journal of Advanced Trends in Computer Science and Engineering, 4(2), March - April 2015, 36 - 43
PROC
v1
1P1
Conflict
over
memory
P1
modules
HCN1
and
VCN1
v2
h2 1P2
P2
M/G/1.
VCN2
HCN2
SM1
FromVCNs-2
h3
vs1
Ps1
1 P3 P3
To VCN3
other request.
SM2
HCN3
VCNS-1
hs
HCNS
SM3
m3
SMs
41
Vikas Shinde, International Journal of Advanced Trends in Computer Science and Engineering, 4(2), March - April 2015, 36 - 43
v 1 P1 ( C 0 1 ) P1
(1)
C 0 P1
m1 h1 (1 P1 ) (C 0 1)(1 P1 )
C 0 (1 P1 )
L 1
2 2 2 s
L W or W
2(1 ) (8)
2 2 2 2 s
2 (1 )
(2)
The input request rate at the ith stage from each PCs is
(vi-1)
vi Pi v( i 1) (C i 1 1) Pi v (i 1) C i 1 Pi v( i1)
(3)
a processor request to
mi hi (1 Pi ) v (i 1) (C i 1 1) (1 Pi ) v ( i 1)
C i 1 (1 Pi ) v (i 1)
i 1
Pvi Pj 1
(4)
(9)
j0
Pmi Phi
(1 Pi ) i 1
Pj 1
Pi
j 0
(10)
vs 0
(5)
ms hs C s 1 (1 Ps ) v ( s 1) C s 1 Ps v ( s 1)
C s 1 v ( s 1)
(6)
Processor
Utilization
1
2( )
w 2 2 2 s
PU
(11)
computed as.
(SPP). Thus
2(1 )
2( ) SPP
2 2 2 s
(7)
PU
SPP
(12)
(7)
i 0
4. CONCLUSIONS
In
this
investigation,
the
performance
Vikas Shinde, International Journal of Advanced Trends in Computer Science and Engineering, 4(2), March - April 2015, 36 - 43
1450-1463. (2012)
8.
REFERENCES
9.
(1975)
Performance
348. (1997)
(2000)
master-slave
(1999)
Jan,
Y.
and
Jozwiak,
L.
based
of
cluster
evaluation
of
performance
analysis
5.
Scalable
43