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KXSD9-2050
Rev. 3
Jul-2010
Product Description
The KXSD9 is a tri-axis silicon micromachined accelerometer with
a user selectable full-scale output range of 2g, 4g, 6g or 8g.
The sense element is fabricated using Kionixs proprietary plasma
micromachining process technology. Acceleration sensing is based
on the principle of a differential capacitance arising from
acceleration-induced motion of the sense element, which further
utilizes common mode cancellation to decrease errors from
process variation, temperature, and environmental stress. The
sense element is hermetically sealed at the wafer level by bonding
a second silicon lid wafer to the device using a glass frit. A
separate ASIC device packaged with the sense element provides
signal conditioning, self-test, and temperature compensation. The
accelerometer is delivered in a 3 x 3 x 0.9 mm LGA plastic package
operating from a 1.8 3.6V DC supply. Either I2C or SPI interfaces can be used to communicate to
the chip to trigger A/D conversions or manage power consumption.
Functional Diagram
X
Sensor
Y
Sensor
Charge
Amp
Z
Sensor
LPF
Temp
Sensor
Vdd 5
A/D
SPI/I 2C
Motion Detection
IO Vdd 1
3 AUX IN
GND 4
6
10
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Product Specifications
Table 1. Mechanical
(specifications are for operation at 3.3V and T = 25C unless stated otherwise)
Parameters
Units
Min
Typical
-40
85
Zero-g Offset
counts
1843
2048
2253
mg/C
Sensitivity
counts/g
0.5 (xy)
3 (z)
794
819
844
390
410
430
257
273
289
205
221
189
0.01 (xy)
0.04 (z)
%/C
%
0.3
1.1 (xy)
0.6 (z)
Max
1.1
0.03
1.5 (xy)
0.5 (z)
Hz
4000 (xy)
2000 (z)
% of FS
0.1
g / Hz
750
1.9
1.1
Notes:
1. User selectable from CTRL_REGC
2. Resonance as defined by the dampened mechanical sensor.
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Table 2. Electrical
(specifications are for operation at 3.3V and T = 25C unless stated otherwise)
Parameters
Supply Voltage (Vdd)
Operating
I C Communication Rate
Bandwidth (-3dB)
Units
Min
Typical
Max
1.8
1.7
3.3
3.6
Vdd
120
220
320
40
75
V
A
V
V
V
V
0.9 * Vio
0.8 * Vio
ms
s
MHz
0.1
0
15.9
8.0
1.6
0.8
0.4
200
1
400
KHz
Hz
0.3 * Vio
0.2 * Vio
-
40
50
60
Notes:
2
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
t2
t1
t3
t4
t5
t6
t7
nCS
SCLK
SDI
bit 7
bit 6
bit 1
bit 0
SDO
bit 7
bit 7
t8
bit 6
bit 1
bit 0
bit 6
bit 1
bit 0
t10
t11
t9
Description
MIN
MAX
Units
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
1
130
130
130
200
350
350
130
10
100
0
1
200
130
-
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
Notes
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Table 4. Environmental
Parameters
Units
Min
Typical
Max
V
C
C
-0.3
-40
-55
ESD
6.0
85
150
5000 for 0.5ms
10000 for 0.2ms
2000
HBM
Caution: ESD Sensitive and Mechanical Shock Sensitive Component, improper handling
can cause permanent damage to the device.
This product conforms to Directive 2002/95/EC of the European Parliament and of the
Council of the European Union (RoHS). Specifically, this product does not contain lead,
mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or
polybrominated diphenyl ethers (PBDE) above the maximum concentration values
(MCV) by weight in any of its homogenous materials. Homogenous materials are "of
uniform composition throughout."
HF
This product is halogen-free per IEC 61249-2-21. Specifically, the materials used in this
product contain a maximum total halogen content of 1500 ppm with less than 900-ppm
bromine and less than 900-ppm chlorine.
Soldering
Soldering recommendations are available upon request or from www.kionix.com.
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Application Schematic
SDA/SDO
10
IO Vdd
SCL/SCLK
ADDR/SDI
MOT
CS
KXSD9
AUX IN
C1
Vdd
Name
Description
IO Vdd
DNC
AUX IN
GND
Ground
Vdd
The power supply input. Decouple this pin to ground with a 0.1uF ceramic capacitor.
nCS
SPI Enable
I2C/SPI mode selection (1 = I2C mode, 0 = SPI mode)
MOT
ADDR/SDI
SCL/SCLK
10
SDA/SD0
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Test Specifications
Special Characteristics:
These characteristics have been identified as being critical to the customer. Every part is tested to verify
its conformance to specification prior to shipment.
Table 6. Test Specifications
Parameter
Zero-g Offset @ RT
Sensitivity @ RT
Current Consumption -- Operating
Specification
2048 +/- 205 counts
819 +/- 25 counts/g
120 <= Idd <= 320 uA
Test Conditions
25C, Vdd = 3.3 V
25C, Vdd = 3.3 V
25C, Vdd = 3.3 V
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Orientation
+Y
Pin 1
+X
+Z
When device is accelerated in +X, +Y or +Z direction, the corresponding output will increase.
5
Top
6
Bottom
Bottom
Top
2048
counts
2867
counts
2048
counts
1229
counts
2048
counts
2048
counts
2867
counts
2048
counts
1229
counts
2048
counts
2048
counts
2048
counts
2048
counts
2048
counts
2048
counts
2048
counts
2867
counts
1229
counts
0
+
0
+
0
0
0
0
0
0
0
0
+
0
0
-
X-Polarity
Y-Polarity
Z-Polarity
(1-g)
Earths Surface
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Description
The device that transmits data to the bus.
The device that receives data from the bus.
The device that initiates a transfer, generates clock signals and terminates a transfer.
The device addressed by the Master.
Table 7. Serial Interface Terminologies
PART NUMBER:
SDA SCL
KXSD9-2050
Rev. 3
Jul-2010
Vdd
SDA
MCU
SCL
SDA
KXSD9
SCL
ADDR
SDA
KXSD9
SCL
ADDR
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
PART NUMBER:
Term
S
Sr
SAD
W
R
ACK
NACK
RA
Data
P
KXSD9-2050
Rev. 3
Jul-2010
Definition
Start Condition
Repeated Start Condition
Slave Address
Write Bit
Read Bit
Acknowledge
Not Acknowledge
Register Address
Transmitted/Received Data
Stop Condition
Table 8. I2C Terms
SAD + W
RA
ACK
DATA
ACK
ACK
SAD + W
RA
ACK
DATA
DATA
ACK
ACK
P
ACK
Sequence 3. The Master is receiving one byte of data from the Slave.
Master
Slave
SAD + W
RA
ACK
Sr
SAD + R
ACK
NACK
ACK
DATA
Sequence 4. The Master is receiving multiple bytes of data from the Slave.
Master
Slave
SAD + W
RA
ACK
Sr
SAD + R
ACK
ACK
ACK
DATA
NACK
DATA
Sequence 5. The Master is receiving acceleration bytes from the Slave (ADDR = 0, CLKhld = 1).
Master
Slave
0x30h
0x00h
ACK
200S
ACK CLKhld
Sr
0x31h
ACK
ACK XOUT_H
Master ACK
ACK
ACK
ACK
NACK
Slave
YOUT_H
YOUT_L
ZOUT_H
ZOUT_L
36 Thornwood Dr. Ithaca, NY 14850
tel: 607-257-1080 fax:607-257-1146
www.kionix.com - info@kionix.com
XOUT_L
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
SPI Interface
The KXSD9 also utilizes an integrated Serial Peripheral Interface (SPI) for digital communication. The SPI
interface is primarily used for synchronous serial communication between one Master device and one or
more Slave devices. The Master, typically a micro controller, provides the SPI clock signal (SCLK) and
determines the state of Chip Select (nCS). The KXSD9 always operates as a Slave device during standard
Master-Slave SPI operation.
SPI is a 4-wire synchronous serial interface that uses two control and two data lines. With respect to the
Master, the Serial Clock output (SCLK), the Data Output (SDI or MOSI) and the Data Input (SDO or MISO)
are shared among the Slave devices. The Master generates an independent Chip Select (nCS) for each
Slave device that goes low at the start of transmission and goes back high at the end. The Slave Data
Output (SDO) line, remains in a high-impedance (hi-z) state when the device is not selected, so it does not
interfere with any active devices. This allows multiple Slave devices to share a master SPI port as shown
in Figure 2 below.
Master
Serial Clock
CS0
CS1
Slave 0
SCLK
CS
KXSD9
MCU
SDI
MOSI (Data Out)
MISO (Data In)
SDO
Slave 1
SCLK
CS
KXSD9
SDI
SDO
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
and the host must return nCS high for at least 130nS before the next data request. Figure 3 below shows
the timing diagram for carrying out the 8-bit control register write operation.
SCLK
SDI
A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
(MSB)
SDO
CS
(MSB)
HI-Z
HI-Z
In order to read an 8-bit control register, an 8-bit read command must be written to the accelerometer to
initiate the read. The MSB of this control register address byte will indicate 0 when writing to the register
and 1 when reading from the register. Upon receiving the command, the accelerometer returns the 8-bit
operational-mode data stored in the appropriate control register. This operation also occurs over 16 clock
cycles. All returned data is sent MSB first, and the host must return nCS high for at least 130nS before the
next data request. Figure 4 shows the timing diagram for an 8-bit control register read operation.
SCLK
SDI
A7 A6 A5 A4 A3 A2 A1 A0
(MSB)
SDO
CS
HI-Z
D7 D6 D5 D4 D3 D2 D1 D0
HI-Z
(MSB)
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
200s
SCLK
SDI
A7 A6 A5 A4 A3 A2 A1 A0
(MSB)
SDO
CS
HI Z
D7
D6
D5
D4
D3
D2
D1
(MSB)
D0
D7
D6
D5
D4
D3
D2
D1
HI Z
D0
(MSB)
Figure 5 Timing Diagram for an A/D conversion and 12-Bit data read operation.
SDO
A7 A6 A5 A4 A3 A2 A1 A0
MSB
X
MSB
D11 D10 D9 D8 D7 D6 D5 D4
D3 D2 D1 D0 X
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Read/Write
R
R
R
R
R
R
R
R
W
R/W
R/W
R
Address
Hex
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
xxxx
xxxx
0x0A
xxxx
0x0C
0x0D
0x0E
Binary
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
xxxx xxxx
xxxx xxxx
0000 1010
xxxx xxxx
0000 1100
0000 1101
0000 1110
Read/Write
R
R
R
R
R
R
R
R
W
R/W
R/W
R
Read Address
Hex
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
xxxx
xxxx
xxxx
xxxx
0x8C
0x8D
0x8E
Binary
1000 0000
1000 0001
1000 0010
1000 0011
1000 0100
1000 0101
1000 0110
1000 0111
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
1000 1100
1000 1101
1000 1110
Write Address
Hex
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0x0A
xxxx
0x0C
0x0D
xxxx
Binary
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 1010
xxxx xxxx
0000 1100
0000 1101
xxxx xxxx
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Register Descriptions
XOUT_H
X-axis accelerometer output most significant byte
R
R
R
XOUTD11 XOUTD10 XOUTD9
Bit7
Bit6
Bit5
R
XOUTD8
Bit4
R
XOUTD7
Bit3
R
XOUTD6
Bit2
R
XOUTD5
Bit1
R
XOUTD4
Bit0
I C Address: 0x00h
SPI Read Address: 0x80h
XOUT_L
X-axis accelerometer output least significant byte
R
XOUTD3
Bit7
R
XOUTD2
Bit6
R
XOUTD1
Bit5
R
XOUTD0
Bit4
R
X
Bit3
R
X
Bit2
R
X
Bit1
R
X
Bit0
I C Address: 0x01h
SPI Read Address: 0x81h
YOUT_H
Y-axis accelerometer output most significant byte
R
R
R
YOUTD11 YOUTD10 YOUTD9
Bit7
Bit6
Bit5
R
YOUTD8
Bit4
R
YOUTD7
Bit3
R
YOUTD6
Bit2
R
YOUTD5
Bit1
R
YOUTD4
Bit0
I C Address: 0x02h
SPI Read Address: 0x82h
YOUT_L
Y-axis accelerometer output least significant byte
R
YOUTD3
Bit7
R
YOUTD2
Bit6
R
YOUTD1
Bit5
R
YOUTD0
Bit4
R
X
Bit3
R
X
Bit2
R
X
Bit1
R
X
Bit0
I C Address: 0x03h
SPI Read Address: 0x83h
ZOUT_H
Z-axis accelerometer output most significant byte
R
R
2009 Kionix All Rights Reserved
310-1547-1007221647
Page 18 of 25
PART NUMBER:
ZOUTD8
Bit4
ZOUTD7
Bit3
ZOUTD6
Bit2
ZOUTD5
Bit1
KXSD9-2050
Rev. 3
Jul-2010
ZOUTD4
Bit0
I C Address: 0x04h
SPI Read Address: 0x84h
ZOUT_L
Z-axis accelerometer output least significant byte
R
ZOUTD3
Bit7
R
ZOUTD2
Bit6
R
ZOUTD1
Bit5
R
ZOUTD0
Bit4
R
X
Bit3
R
X
Bit2
R
R
X
X
Bit1
Bit0
I2C Address: 0x05h
SPI Read Address: 0x85h
AUXOUT_H
Auxiliary output most significant byte
R
R
R
R
R
R
R
R
AUXOUTD11 AUXOUTD10 AUXOUTD9 AUXOUTD8 AUXOUTD7 AUXOUTD6 AUXOUTD5 AUXOUTD4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
2
I C Address: 0x06h
SPI Read Address: 0x86h
AUXOUT_L
Auxiliary output least significant byte
R
R
R
R
AUXOUTD3 AUXOUTD2 AUXOUTD1 AUXOUTD0
Bit7
Bit6
Bit5
Bit4
R
X
Bit3
R
X
Bit2
R
R
X
X
Bit1
Bit0
I2C Address: 0x07h
SPI Read Address: 0x87h
Reset_write
When the key (11001010) is written to this register the offset, sensitivity and temperature correction
values will be loaded into RAM and used for all further measurements. This is also accomplished at
power-up by an internal power-up reset circuit.
W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
I C Address: 0x0Ah
36 Thornwood Dr. Ithaca, NY 14850
tel: 607-257-1080 fax:607-257-1146
www.kionix.com - info@kionix.com
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
CTRL_REGC
Read/write control register: Factory programmed power up/reset default value (0xE1h)
R/W
LP2
Bit7
R/W
LP1
Bit6
R/W
LP0
Bit5
R/W
MOTLev
Bit4
R/W
MOTLat
Bit3
R/W
0
Bit2
R/W
FS1
Bit1
R/W
FS0
Bit0
Reset Value
11100001
I C Address: 0x0Ch
SPI Write Address: 0x0Ch
FS0 is the first of two bits used to select the full scale sensing range of the accelerometer. See
Table 11 below.
FS1 is the second of two bits used to select the full scale sensing range of the accelerometer. See
Table 11 below.
FS1
FS0
0
0
1
1
0
1
0
1
Full Scale
12-bit Sensitivity
Range
+/-8 g
+/-6 g
+/-4 g
+/-2 g
205 counts/g
273 counts/g
410 counts/g
819 counts/g
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
0g
MOTLev Threshold
Accelerometer Output
MOT
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
0g
MOTLev Threshold
Accelerometer Output
MOT
CRTL_REGA Read
MOTLev sets the motion wakeup threshold to an acceleration level as defined in Table 12.
MOTLev
FS1
FS0
Motion Wake Up
Threshold
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+/-6 g
+/-4.5 g
+/-3 g
+/-1.5 g
+/-4 g
+/-3 g
+/-2 g
+/-1 g
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
LP1 is the second of three bits used to select the operational bandwidth of the accelerometer. See
Table 13 below.
LP2 is the third of three bits used to select the operational bandwidth of the accelerometer. See
Table 13 below.
LP2
LP1
LP0
Filter Corner
Frequency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Filter
2000 Hz
2000 Hz
2000 Hz
1000 Hz
500 Hz
100 Hz
50 Hz
R/W
ENABLE
Bit6
R/W
ST
Bit5
R/W
0
Bit4
R/W
0
Bit3
R/W
MOTIen
Bit2
R/W
0
Bit1
R/W
0
Bit0
Reset Value
01000000
I C Address: 0x0Dh
SPI Write Address: 0x0Dh
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
CTRL_REGA
Read-only status register
R
X
Bit7
R
X
Bit6
R
X
Bit5
R
X
Bit4
R
X
Bit3
R
X
Bit2
R
MOTI
Bit1
R
X
Bit0
I C Address: 0x0Eh
SPI Write Address: 0x0Eh
MOTI reports the status of the motion wakeup interrupt. Reading CTRL_REGA clears the
MOTI bit and MOT pin (7).
MOTI = 1 - a motion wake up event has occurred and the MOT pin (7) is high.
MOTI = 0 - a motion wake up event has not occurred and the MOT pin (7) is low.
PART NUMBER:
KXSD9-2050
Rev. 3
Jul-2010
Revision History
REVISION
1
DESCRIPTION
Initial release
Changed Current Consumption, Operating (15Hz) to Motion Wake Up 15Hz Mode and added typ. and
max fields for it.
DATE
16-May2008
12-Oct2009
08-Jul-2010
"Kionix" is a registered trademark of Kionix, Inc. Products described herein are protected by patents issued or pending. No license is granted by implication or
otherwise under any patent or other rights of Kionix. The information contained herein is believed to be accurate and reliable but is not guaranteed. Kionix does not
assume responsibility for its use or distribution. Kionix also reserves the right to change product specifications or discontinue this product at any time without prior
notice. This publication supersedes and replaces all information previously supplied.