OPERATIONAL AMPLIFIER

FABRICATION

Submitted by,
JIJO JOSE B120010EC
JOEL V GEORGE B120650EC
ARJUN SS B120597EC
JESWIN THOMAS MATHEWS B120294EC
BENJAMIN V MATHEW B120214EC

GUIDE: Dr. P. C. Subramaniam

AIM
The overall aim of the project was to implement an LM741-like
Operational Amplifier. We had planned to realise the same using
commonly available transistors to replace the ones in the IC. The
complications of assembling the entire module summed with the lack
of clarity of a unique design of the circuit made us to decide upon
assembling it stage by stage. What we had in mind was a three stage
implementation of the differential amplifier, the gain stage and the
output power amplifier stage.

INTENDED METRICS
The set of specifications of the Op Amp as per our abstract were:
Input Resistance: 6 M
Common Mode Rejection Ratio: 90dB
Bandwidth: 1.5 MHz
Input bias current: 30nA
Slew Rate: 0.5V/A

METHODOLOGY EMPLOYED
As with any Op Amp, we divided the circuit between a differential
amplifier, a gain stage with frequency compensation capacitor, and a
power amplifier. These stages were intended to be done separately
and then to be joined together.

THE DIFFERENTIAL AMPLIFIER STAGE

Differential amplifiers could either be implemented using resistive or
active load. For both of these, two matched transistors were used as
differential pair and current mirror circuit was used to bias this with constant
current. For the load we had the option of choosing from two resistors or two
transistors which were responsible for their respective names. For simplicity,
we first assembled the resistively loaded differential amplifier(shown below).
Differential gain was found for this circuit by grounding one of the differential

inputs and giving a small signal at the other terminal. Similarly, the common
mode gain was also found for this circuit by shorting the differential inputs.

We then proceeded to assemble the circuit with active load as shown

below. Values for differential gain and common mode gain were
derived in a similar fashion. The CMRR was also noted for this circuit.

THE SECOND AND THIRD STAGES

The second and third stages of the circuit were assembled as per the
diagram shown below and interfaced with the first stage.

PCB Layout of the whole circuit is given below

CHALLENGES FACED
The first concern of design was getting a working circuit diagram of the Op
Amp employing commonly available transistors. Many circuit diagrams were
available from various sources, but almost all of them were negligent on the
type of transistors used. This was important as one of the several basic
problems involved was to select a matching pair of npn and pnp devices.
BC547 had poor performance with regard to this criteria. The entire biasing of

the circuitry assumed that the transistors functioned as ideal ones and all of
them possessed uniform characteristics. We initially settled for 2N3906 (PNP)
and 2N3904 (NPN). These were commonly-used bipolar junction transistors
intended for general purpose low-power amplifying or switching applications.
We implemented the first stage of the design, the differential amplifier stage
using the aforementioned transistors. It was observed that the gain was very
less (about 80); certainly not fit for our desired values. We inferred that it was
due to its low collector current operation conditions.
After changing transistors to SL100(npn) and SK100(pnp) we managed to get
more gain for the circuit, also for the first stage. This was so in the case of
resistive load, but for the active loaded circuit the output voltage had a DC
level at around 20V. Thus it was nearly impossible to get a non-clipped sine
under such poor voltage swing and relatively high gain of the circuit.
Owing to all these, we decided to proceed with the resistive loaded circuit.

RESULTS
Results of the first stage, differential amplifier(active load):
Differential gain: 382
Common mode gain: 2
CMRR: 45dB