Electrical Power and Energy Systems 63 (2014) 363372

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Electrical Power and Energy Systems

journal homepage: www.elsevier.com/locate/ijepes

Comparative study on different ve level inverter topologies

K.S. Gayathri Devi , S. Arun, C. Sreeja
Dept. of Electrical & Electronics, Amal Jyothi College of Engineering, Kottayam, India

a r t i c l e

i n f o

Article history:
Received 30 July 2013
Received in revised form 17 May 2014
Accepted 20 May 2014
Available online 3 July 2014
Keywords:
Diode clamped inverter
Multilevel inverter
Pulse width modulation
Switched-capacitor converter

a b s t r a c t
The diode-clamped multilevel topology has the problem of voltage unbalance of dc link capacitors. This
can be solved by using separate DC sources, or adding auxiliary circuits or adopting space vector modulation control in three-level inverter applications. For higher level applications, the use of separate DC
sources is not viable and the control techniques for other two methods will be more complicated to
implement. Hence the Hybrid Multilevel Inverter Based on Switched-Capacitor and Diode-Clamped units
can be used for higher levels. This topology can balance the capacitor voltage and also step up the output
voltage. The boosting of output voltage contributes to lessen the transformation ratio of the input transformer or even eliminate it, thereby reducing the cost, which will benet the design of converters in mediumhigh voltage applications. The topology is simulated using MAT lab simulink software and compared
with other voltage balancing techniques.
2014 Elsevier Ltd. All rights reserved.

Introduction

Voltage balancing techniques

Recently, multilevel inverters [6] have drawn tremendous interest in the eld of high-voltage and high-power applications
because it can realize high voltage and high power output through
low-voltage switches without transformer and dynamic voltage
balance circuits, with the number of output level increasing,
harmonics of the output voltage and current are decreasing and
EM1 are decreasing Multilevel inverters are mainly classied as
diode-clamped, capacitor-clamped and cascaded H-bridge
inverters.
Among the basic multilevel inverters the problem of voltage
unbalance of dc link capacitors exists inherently in the diodeclamped converter topology [13,15], which limits the further application [5] of it, especially at the level above three. To balance the
voltage of DC link series capacitors, three main approaches have
been proposed. They are: (1) using separate DC sources, [3,7], (2)
adding some auxiliary balancing circuits [8,9,16] and (3) improving
the control method by selecting redundant switching states, [4,10].
By auxiliary circuits, the transferred current or power can be controlled accurately, but the additional feedback control strategies
are also needed, so the control of these converters becomes more
complicated, and converters are less reliable.

Cascaded H-bridge inverter

A multilevel CHB consists of a number of H-bridge cells connected
in series per phase, and each module requires a separate DC source to
generate voltage levels at the output of inverter. The output of each
bridge is +Vdc, 0 and Vdc and the combinations of the output voltages of series connected bridges give the total output voltage.
According to the number of bridges the number of levels of the output voltage changes. The number of bridges is equal to (n 1)/2
where n is the number of levels of output voltage. To operate a cascade multilevel inverter [3,7] using a single DC source, it is proposed
to use capacitors as the DC sources for all but the rst source. Consider a simple inverter with two H-bridges as shown in Fig. 1.
Each H-bridge has a DC power source with an output voltage of
Vdc. The output voltage of the rst H-bridge is denoted by V1 and
the output of the second H-bridge is denoted by V2 so that the output of this two DC source cascade multilevel inverter is V = V1 + V2.
By opening and closing the switches of H1 and H2 appropriately,
the output voltage V1 and V2 can be made equal to +Vdc, 0, or Vdc.
Therefore, the output voltage of the inverter can have the values,
+Vdc, +Vdc/2, 0, Vdc/2, Vdc. The ring instants can be obtained
by using phase disposition multicarrier PWM technique.
Voltage balancing using resonant switched capacitor converter

Corresponding author. Tel.: +91 9495686300.

E-mail addresses: gayathrideviks@yahoo.co.in (K.S. Gayathri Devi), aruns@
amaljyothi.ac.in (S. Arun), csreeja@amaljyothi.ac.in (C. Sreeja).
http://dx.doi.org/10.1016/j.ijepes.2014.05.053
0142-0615/ 2014 Elsevier Ltd. All rights reserved.

Fig. 2 shows a system conguration of a three-phase diode

clamped ve-level inverter equipped with RSCC voltage balancing

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K.S. Gayathri Devi et al. / Electrical Power and Energy Systems 63 (2014) 363372

Fig. 1. Five level H-bridge inverter.

Fig. 2. Five level DCI with RSCC.

circuits [8]. The dc link consists of four dc capacitors C1C4, and it is

connected to a three-phase diode rectier. The rectier keeps the
total voltage across the four dc capacitors as 4Vdc, but each capacitor voltage may deviate from Vdc. Therefore, two voltage-balancing circuits are employed to balance their voltages. One is
connected to C1 and C2, and the other is connected to C3 and C4
Symmetrical operation of the ve-level inverter makes it possible
to maintain the voltage of node M at the center of the dc-link
voltage.
While considering the section between P2 and M, the circuit
consists of two half-bridge inverters with four switching devices
S1S4 and a series resonant circuit Lr and Cr. The dc terminals of
the half-bridge inverters are connected in parallel with the dc
capacitor, while an ac terminal is connected to the other one
through the series resonant circuit. Dc voltage source 2Vdc keeps
the total capacitor voltage vC1 + vC2 as 2Vdc. When the vC2 decreases
by some cause, the dc voltage source supplies an amount of power
to both C1 and C2, and then vC1 increases. The voltage balancing circuit ows a positive current in iPB to discharge C1 and to charge C2.
The four switching devices enables the bidirectional power ow

from C1 to C2 or opposite direction. The circuit essentially acts as

a switched-capacitor converter or a charge pump circuit, which
stores transferred energy in the resonant capacitor Cr, instead of
an inductor. The resonant inductor Lr makes it possible to suppress
the spike currents, power losses, and electromagnetic noises.
All switching devices are operated with a 50% duty ratio, but
their switching frequency is higher than the resonant frequency
of the resonant circuit. Therefore, the resonant circuit acts as
inductive impedance. The amplitude of the resonant current by
means of phase shift between the two half bridge inverters. The
proposed method delays S3 and S4 from S1 and S2 for a phase-shift
time T1. Power Prscc will be maximum when the value of T1 lies
between Tsw/4 and +Tsw/4 where Tsw is the time corresponding
to the switching frequency of RSCC.
Hybrid Multilevel Inverter Based on Switched Capacitor and Diode
Clamped units
The circuit diagram of three-phase topology [1,2] is deduced by
combination of three HMI-BSD single-leg circuits sharing common

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365

dc link capacitors, shown in Fig. 3. All the elements sustain the

same voltage stresses, which equal 1/(n 1)of the dc link voltage.
Principle of operation
A single-leg ve-level inverter topology based on HMI-BSD is
shown in Fig. 4. The topology can be divided into two parts, which
are, respectively, indicated by a dash dotted frame and a dashed
frame. Part 1 is called switched-capacitor part and part 2 is called
diode-clamped part. The switched-capacitor part is composed of
the dc link capacitors (C1, C2), the ying capacitors (C3, C4, C5),
and the clamping switching devices (Sc1, Sc6). And the diodeclamped part is composed of the ying capacitors (C3, C4, C5), the
clamping diodes (Dc1, Dc6), and the main switching devices
(S1, S6). It can be seen clearly that both parts include the ying
capacitors C3, C4, and C5.
The diode-clamped part is a classical four-level diode-clamped
topology with four kinds of working states and four kinds of output
voltage levels. Among the main switching devices S1, S6, only three
switching devices in succession are switched on in each working
state. And (S1, S4), (S2, S5), and (S3, S6) are complementary switching pairs. The switched-capacitor part operates with two kinds of
working states. The clamping switching devices Sc1, Sc6 can be
divided into two groups: Group A and Group B.
Group A includes Sc1, Sc3, and Sc5, and Group B includes Sc2, Sc4,
and Sc6. The control signals for the switching devices of the same
group are identical. When the switching devices of Group A are
switched ON, those of Group B are switched OFF, and vice versa.
The switching devices of the two groups are switched ON or OFF
alternately. If the switching devices of Group A are ON and those
of Group B are OFF C1 is paralleled with C3, and C2 is paralleled with
C4.
Table 1 shows the relationships between the output voltage Vo
and the working states, where Udc is the voltage of one dc link
capacitor. The switched-capacitor part not only contributes to balance the DC link capacitors, but also participates in the synthesis of
the output voltage levels by the common connection of the ying
capacitors with the diode-clamped part. In this case, the
HMI-BSD can output ve kinds of voltage levels with only a
conventional four-level diode-clamped topology.
Voltage balance of capacitors
If only the diode-clamped part of the HMI-BSD works without
the switched-capacitor part [12], the voltages of capacitors would
be unbalanced due to the asymmetric charge current and discharge
current through capacitors. The switched-capacitor part plays a

Fig. 4. Single-leg of ve-level HMI-BSD.

role in balancing the voltages of capacitors by alternative

conduction of the clamping switches Sc1Sc6.
When the switching devices of Group A are ON and those of
Group B are OFF, C1 and C3, C2 and C4 are in parallel, respectively,
so VC1 = VC3 and VC2 = VC4. When the switching devices of Group B
are ON and those of Group A are OFF, C1 and C4, C2 and C5 are in
parallel, respectively, so VC1 = VC4 and VC2 = VC5. If the switching
devices of Group A are turned from ON to OFF, and from OFF to
ON over and over again, then VC1 = VC2 = VC3 = VC4 = VC5. That is
to say, each capacitor can keep voltage balance through the ying
capacitor C4. Actually, the capacitor C4 acts as the second spiker,
which is in parallel with different dc link capacitors in different
switching states. So long as Group A or Group B can switch once
in one period, the voltages of the capacitors can keep balance.
As seen from Table 1, the switching devices of Group B or Group
A are ON for one working state and OFF for the other working state.
Accordingly, there exist two kinds of working states combination,
shown in Tables 2 and 3.
It can be seen from Table 2 that for the rst working states combination, the switching devices of group B are turned ON only
when the highest output level (+2Vdc) appears and turned OFF
when other four levels appear. The pulse width modulation
(PWM) [11,14] carriers arrangement for this working states combination is shown in Fig. 5(a). As seen from Fig. 5(a), every carrier
band from top down corresponds to Group B, S1, S2 and S3 in turn.
When the HMI-BSD operates under the condition of a lower
modulation ratio (M < 0.5), the output voltages will change from

Fig. 3. Three phase ve-level HMI-BSD.

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Table 1
Relationships between the output voltage V0 and the working states.
No. of working states

Output level Vo

S1

S2

S3

S4

S5

S6

Group A

Group B

+2Vdc

2
3

+1Vdc

1
0

1
1

1
1

0
1

0
0

0
0

1
0

0
1

4
5

0Vdc

0
0

1
0

1
1

1
1

0
1

0
0

1
0

0
1

6
7

1Vdc

0
0

0
0

1
0

1
1

1
1

0
1

1
0

0
1

2Vdc

Table 2
First kind of working states combination for HMI-BSD.
No. of working states

Output level Vo

S1

S2

S3

S4

S5

S6

Group A

Group B

1
2
4
6
8

+2Vdc
+1Vdc
0Vdc
1Vdc
2Vdc

1
1
0
0
0

1
1
1
0
0

1
1
1
1
0

0
0
1
1
1

0
0
0
1
1

0
0
0
0
1

0
1
1
1
1

1
0
0
0
0

Table 3
Second kind of working states combination for HMI-BSD.
No. of working states

Output level Vo

S1

S2

S3

S4

S5

S6

Group A

Group B

1
3
5
7
8

+2Vdc
+1Vdc
0Vdc
1Vdc
2Vdc

1
0
0
0
0

1
1
0
0
0

1
1
1
0
0

0
1
1
1
1

0
0
1
1
1

0
0
0
1
1

0
0
0
0
1

1
1
1
1
0

ve levels to three levels, i.e., the highest output level cannot be

realized for the lower modulation index, and then Group B will lose
the chance of being turned ON and being turned OFF all the time. In
the like manner, for the second working states combination listed
in Table 3, the switching devices of Group B are turned OFF only
when the lowest output level ( 2Vdc) appears and turned ON for
the other four output levels appear. The carriers arrangement for
this working states combination is shown in Fig. 5(b). As seen from
Fig. 5(b), every carrier band from top down corresponds to the
switching devices S1, S2, S3, and Group B in turn. When the modulation ratio is less than 0.5, the lowest level cannot be realized,
andthen Group B will have no chance to be turned OFF and be
turned ON all the time.
The capacitor voltage balancing can be realized only when the
switching devices of Group B are turned on and off alternately;
otherwise, the voltage balancing in capacitors will be broken under
the condition of a lower modulation ratio. So these two kinds of
working states combination must be considered together to ensure
the normal operation of the HMI-BSD within the wider range of
modulation degree (even less than 0.5). As a result, the switching

devices of Group B are turned ON over one switching period and

turned off over the next switching period so that, the ying capacitors are, respectively, connected in parallel with the different
capacitors alternately to ensure the realization of self-voltage balancing mechanism of capacitors.
According to the aforesaid analysis, by rearranging the carrier
waveforms, the special carrier waveforms of the switching devices
for the HMI-BSD are shown in Fig. 7. The carrier waves for the three
main switches are shown in Fig. 6(a)(c) and Fig. 6(d)shows the
carrier wave for switching devices of group B. By applying the special carriers in Fig. 6 to the SPWM method, the switching devices of
Group A and Group B will be alternately turned ON or OFF by periods, thus balancing the voltages in capacitors. This balance scheme
does not need complex control strategy, and is adaptive to all kinds
of loads.
Realization of stepping up the output voltage
In view of the symmetry of the positive and negative output
levels of the HMI-BSD, the two input terminals of the DC source
should be on the output terminals symmetry, so for a single-leg

Fig. 5. PWM carriers for rst and second kind of working states.

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367

Fig. 6. Carrier waveforms of the switching devices [2].

Fig. 7. Three modes of connection of the input DC Source [2].

Fig. 8. Output voltage of FIVE level diode-clamped inverter.

ve-level HMI-BSD, there are three modes of connection of the

input DC source, as shown in Fig. 7(a)(c) The positive and negative
terminals of the DC source are, respectively, connected with (1) the
positive terminal of C1 and the negative terminal of C2; (2) the
positive terminal of C3 and the negative terminal of C5; (3) the
positive and the negative terminals of C4.
If the HMI-BSD is in three-phase operation, the input DC source
terminals should be only connected to the DC link capacitors
instead of the ying capacitors because of the symmetry of the

three-phase topology. And for a ve-level topology, only the connection mode 1 can be used. The function of boosting the output
voltage of the HMI-BSD contributes to lessening the transformation ratio of the input transformer, thereby reducing the cost, even
to eliminate the input transformer, which will benet the design of
converters in mediumhigh voltage application. On the other hand,
compared to the conventional switched-capacitor topology, less
switching devices and dc link capacitors are needed in the HMIBSD, which can also reduce the production cost in applications.

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K.S. Gayathri Devi et al. / Electrical Power and Energy Systems 63 (2014) 363372

Fig. 9. Capacitor voltage of ve level diode-clamped inverter.

Fig. 10. FFT analysis of ve level DCI.

Fig. 11. Output voltage of cascaded H-bridge inverter.

Simulations and results

The simulation of diode-clamped ve level inverter had done
with 180 V DC input voltage and sinusoidal pulse width modulation at 0.5 modulation index. The output obtained has ve steps
and each step differ by a voltage of 50 V. That is the ve levels

obtained are 0 V, 45 V, 90 V, 135 V and 180 V. The switching frequency is 5 kHz. Figs. 8 and 9 shows the output voltage and capacitor voltage of ve level diode clamped inverter.
From Fig. 10 it can be observed that the voltage of capacitors 1,
and 4 are increasing to 90 while the voltage across capacitors 2 and
3 are decreasing to 20 V. From Fig. 10 it can be observed that the

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369

Fig. 12. DC link voltage of cascaded H-bridge inverter.

Fig. 13. FFT analysis of ve level H-bridge Inverter.

Fig. 14. Output voltage of ve level DCI with RSCC.

voltage across the capacitors are unbalanced due to the charging

and discharging of the capacitors. Hence the capacitor voltage
should be balanced.
Fig. 10 shows the FFT analysis of ve level DCI. The THD is
25.18%. The harmonics other than fundamental are below 5%.
The rst method of capacitor voltage balancing is using separate
DC sources. If the capacitors in the DCI are replaced with DC

sources the voltage will be balanced but for this each level requires
a separate DC source and is expensive. Another method that uses
separate DC sources are called cascaded H-bridge inverter. This
needs separate DC sources for each bridge. The simulation of cascaded H-bridge inverter is done with 110 V DC input to each bridge.
Phase disposition SPWM is used for generating gate pulses and the
carrier frequency is 5 kHz. The output voltage is shown in Fig. 11.

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Fig. 15. Capacitor voltage with RSCC.

Fig. 16. FFT analysis of ve level DCI with RSCC.

Fig. 17. Output voltage of HMI-BSD at5 kHz.

K.S. Gayathri Devi et al. / Electrical Power and Energy Systems 63 (2014) 363372

Fig. 18. Output voltage of HMI-BSD at 1 kHz Switching Frequency.

Fig. 19. Capacitor voltage of ve level HMI-BSD.

Fig. 20. FFT analysis of ve level HMI-BSD.

371

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Table 4
Comparison of different ve level topologies.

DC Link Capacitors
Flying Capacitors
Resonant capacitors
Inductors
Diodes
No. of main switching devices
No. of clamping switching
devices
No. of DC sources
THD in %

transformer and balance the capacitor voltages. The THD is very

less compared to other methods.

HMIBSD

DCI with
RSCC

CHB

DCI

2
3
0
0
4
6
6

0
4
2
2
6
8
8

0
0
0
0
0
8
0

4
0
0
0
6
8
0

1
17.42

1
18.19

2
18.42

1
25.18

Conclusion

The output voltage of a phase is the sum of output voltages of

individual bridges belong to the corresponding phase. The voltage
across the DC link is shown in Fig. 12.
Fig. 13 shows the FFT analysis of ve level cascaded H-bridge
inverter. The THD is 18.4%. The harmonic components except fundamental are below 5%.
The voltage balancing technique using resonant switched
capacitor [8] had simulated with 180 V dc input and phase shift
control. The output voltage has ve steps each differ by 45 V. The
value of resonant capacitor Cr and inductor Lr are 10 lF and
10 lH respectively. The ying capacitors are of 6600 lF and the
switching frequency of RSCC and carrier frequency of inverter are
30 kHz and 5 kHz respectively.
Figs. 14 and 15 shows the output voltage and ying capacitor
voltage of ve level diode-clamped inverter with RSCC voltage balancing technique. From Fig. 16 it can be observed that the capacitor
voltage is balanced and maintained at 45 V.
The FFT analysis of ve level DCI with RSCC is shown in Fig. 16.
The THD is 18.19%. The harmonic components except fundamental
are less than 5%.
The simulation parameters of HMI-BSD are set as follows: The
dc input voltage is 180 V; the capacitances of all capacitors are
2200 lF; the load resistance is 20 X; the working frequency is
1 kHz; the modulation ratio is 0.95. The input DC source terminals
are connected to the positive terminal of C1 and the negative terminal of C2 The simulation is done for 5 kHz switching frequency
and as well as 1 kHz switching frequency. If 1 kHz switching frequency is considered, the switching losses can be reduced in practical applications. Figs. 17 and 18 shows the output voltage at
5 kHz and 1 kHz frequency respectively.
It can be observed from Figs. 17 and 18 that the output voltage
is stepped up to 360 V with the help of switched capacitor part. The
output has ve levels in which each level differs by 90 V. Also it can
be observed from Fig. 19 that the voltage across all the capacitors
(both DC link capacitors and ying capacitors) are balanced and
maintained at 90 V.
Fig. 20 shows the FFT analysis of ve level HMI-BSD. The THD is
17.42% and the harmonic components other than fundamental are
less than 5%.
The components required per phase is given in Table 4. From
the results and circuit congurations it can be understand that
the voltage balancing using auxiliary circuit need additional circuit
and control complexity because the current and voltage has to be
sensed for control purpose. But HMI-BSD has only simple control
technique as well as it can reduce the transformation ratio of input

The structure and the principle of operation of Hybrid Multilevel Inverter Based on Switched Capacitor and Diode Clamped
units are introduced. The switched-capacitor circuits are applied
to balance the voltage of dc link capacitors and ying capacitors,
as well as participate in synthesizing the output voltage levels.
Both advantages of the switched-capacitor and the diode-clamped
circuits are included in the HMI-BSD by the combination of the two
circuits. Not only this new topology balances dc link capacitors, but
also it can step up the output voltage with kinds of boosting
modes, which will contribute to lessen the turns ratio of the input
transformer, even to eliminate it. In conclusion, the application of
the switched-capacitor circuit in the HMI-BSD can reduce the cost
to a certain extent. The HMI-BSD can operate effectively under the
three-phase condition. Finally, the validity of the HMI-BSD is veried by the simulation of ve level HMI-BSD and compared with
other ve level topologies used for voltage balancing.
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