building blocks for analog circuit design

© All Rights Reserved

12 visualizações

building blocks for analog circuit design

© All Rights Reserved

- For Hobbiest
- Linear Integrated Circuits
- Instrumentation Amplifier
- Simple LM386 Audio Amplifier
- CONTROL_SYSTEMS_AND_SIMULATION_LAB.doc
- Air Conductivity 3
- Electronics - Operational Amplifiers
- Kreatryx GATE 2018 ECE Solutions.pdf
- Logic Probe With Op. Amp. with Dual JFET Input Op Amp - 8 Pin DIP.docx
- Differential Amplifier 8
- Operational Amplifiers
- manual.pdf
- OTA Opamp Testing
- AD744_c
- Base Paper
- LM358
- Multiple Choice Questions and Answers on Op-Amp ( Operational Amplifier ) – Electronics Post
- Opamp design material
- 04541956
- 74HC_HCT244_CNV_2

Você está na página 1de 74

Benemrita Universidad Autnoma de Puebla, Puebla, Mexico

29 November 17 December 2004

Analog Design

Giovanni Anelli

CERN - European Organization for Nuclear Research

Physics Department

Microelectronics Group

CH-1211 Geneva 23 Switzerland

Giovanni.Anelli@cern.ch

This lecture deals with the basis of analog design.

I have decided to prepare the material in a rater formal

way, deriving almost all the necessary formulas.

This was done to try to give you some complete and

precise material for future reference.

We will not need to assimilate all the formulas today.

The important thing is that we recognize in each formula

which are the important parameters and trends.

NOISE

POWER

DISSIPATION

LINEARITY

GAIN

ANALOG

DESIGN

OCTAGON

INPUT/OUTPUT

IMPEDANCE

SUPPLY

VOLTAGE

VOLTAGE

SWINGS

SPEED

Behzad Razavi, CMOS Technology Characterization for Analog and RF Design", IEEE JSSC, vol. 34, no. 3, March 1999, p. 268.

Define specifications

layout

Choose architecture

Layout Versus Schematic

(LVS) check

Simulate schematic

Extracted schematic

simulations

T, VDD, process parameters

BLOCK DONE!

Masks layout

In a complex design,

this will be repeated

for every block of the

design hierarchy.

Outline

Single-stage amplifiers

The differential pair

The current mirror

Differential pair + active current mirror

Operational amplifier (op amp) design

B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill International Edition, 2001.

P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, J. Wiley & Sons, 4th edition, 2001.

R. Gregorian, Introduction to CMOS Op-Amps and Comparators, J. Wiley & Sons, 1999.

R.L. Geiger, P.E. Allen and N.R. Strader, VLSI Design Techniques for Analog and Digital Circuits, McGraw-Hill International Edition, 1990.

D.A. Johns and K. Martin, Analog Integrated Circuit Design, J. Wiley & Sons, 1997.

Outline

Single-stage amplifiers

Common-source Stage

Common-drain Stage (Source Follower)

Common-gate Stage

Cascode Stage

Folded cascode Stage

The current mirror

Differential pair + active current mirror

Operational amplifier (op amp) design

VDD

Vout = VDD R D

DC characteristic

RD

Vout

Vin

Small signal gain

(with channel length

modulation)

( Vin VT )2

2n

Vout

= R D ( Vin VT ) = gmR D

Vin

n

G = gm (r0 // R D ) = gm

r0R D

r0 + R D

G

Vin

gmVGS

S

Vout

RD

ro

could also have been

obtained directly from

the small signal model

CSS Simulation - DC

2.5E-02

3

2.5

1.5E-02

1.5

1.0E-02

1

Vout

Ids

gm

0.5

5.0E-03

0.0E+00

0

0.5

1.5

Vin [ V ]

Puebla, December 2004

2.5

IDS [ A ], g m [ S ]

2.0E-02

Vout [ V ]

W = 100 m

L = 0.5 m

R = 100

The maximum

small signal

gain is only

1.8!!!

CSS Simulation - DC

Increasing the value of the load resistor to 1 k we have

3

1.2E-02

Vout

Ids

gm

1.0E-02

8.0E-03

1.5

6.0E-03

4.0E-03

0.5

2.0E-03

0.0E+00

0

0.5

1.5

Vin [ V ]

Puebla, December 2004

2.5

IDS [ A ], g m [ S ]

Vout [ V ]

2.5

W = 100 m

L = 0.5 m

R = 1000

The maximum

small signal

gain is now

9.6.

0.905

1.774

0.903

1.772

1.77

0.901

1.768

0.899

1.766

0.897

1.764

0.895

1.762

0

R = 1000

Ids [ mA ]

Vin [ V ]

10

0.905

0.738

0.903

0.736

0.734

0.901

0.732

0.899

0.73

0.897

0.728

0.895

0.726

0

sinusoid with frequency 1 kHz,

peak to peak amplitude 1 mV

AND dc offset = 0.9 V.

The DC offset is important to

be in the right bias point.

V out [ V ]

Vin [ V ]

t [ ms ]

gm = 9.6 mS

in a current by the transistor

and then in a voltage again by

the resistor.

10

t [ ms ]

Puebla, December 2004

Diode-connected transistor

A MOS transistor behaves as a small signal resistor when gate and

drain are shorted. A transistor in this configuration is referred to as

diode-connected transistor. The device is always in saturation.

To calculate the impedance of this device we use the small-signal

equivalent circuit and a test voltage generator (in red). The ratio

between the voltage vx applied and the current ix gives the impedance.

ix

G, D

gmVGS

ro

vx

ix = gm v x +

+

R=

vx

r0

vx

1

1

=

1 gm

ix

gm +

r0

The calculation show that the impedance is given by the parallel of two

resistors, 1/gm and r0.

Puebla, December 2004

Diode-connected transistor

Impedance seen looking into the source.

VDD

G, D

ro

gmVGS

ix

vx

ix

vx

v

ix = gm v x + x + gmb v x

r0

R=

gmbVBS

vx

1

1

=

1 gm + gmb

ix

gm + gmb +

r0

In this case we have three resistances in parallel: 1/gm, 1/gmb and r0.

Puebla, December 2004

Diode-connected transistor

Impedance seen looking into the drain with a resistor RS between the

source and ground.

G, D

ix

vx

ix

+

ro

gmVGS

gmbVBS

S

RS

ix = gm (v x ixR S ) +

vx

B

RS

v x i xR S

gmbixR S

r0

1

1 + gm + gmb + R S

r0

v

1 gm + gmb

R= x =

+

RS

1

ix

g

g

m

m

gm +

r0

Without bulk effect (gmb) and the channel length modulation (r0) we

would see the series of 1/gm and RS. If RS = 0 we find again 1/gm.

Puebla, December 2004

VDD

T2

G = gm1

Vout

Vin

T1

1

gm2 + gmb2 +

1

1

+

r02 r01

gm1

gm2

1 g

= m1

gm2 gm2 + gmb 2

n2 gm2

n2

(W / L )1

(W / L )2

Using the results found for single transistors (as we have done)

Starting from the DC equations and doing some mathematics (boring)

Using the small signal equivalent circuit (see next slide)

In an N-well CMOS process, the bulk contacts of all the NMOS are

connected together to ground (substrate). On the other hand, each bulk

contact of the PMOS (each well) can be connected to a desired signal.

Puebla, December 2004

G2, D2

i = gm1vin +

ro2

gm2VGS2

gmb2VBS2

v out

r01

i = gm2 v out

v out

gmb 2 v out

r02

S2, Vout

i

G1

Vin

D1

r01

gm1VGS1

S1

B1

B2

1

1

+

r01 r02

G=

v out

= gm1

vin

g

m2

1

+ gmb 2

1

1

+

+

r02 r01

Substituting the NMOS load with a PMOS load, we get rid of the bulk effect.

VDD

G = gm1

T2

Vout

Vin

T1

gm2

1

g

m1

1

1

gm2

+

+

r02 r01

G=

n (W / L )1

p (W / L )2

It is difficult to have high gain

Vout_max = VDD VGS2.

To have gain, (W/L)2 is made smaller than (W/L)1. This will limit the

maximum output voltage, since VGS2will be quite higher than VT2.

Puebla, December 2004

To increase the gain, we can use the output resistance of a transistor.

T2 provides the DC current bias to T1, and has a high output

impedance. The bias current is determined by Vb.

VDD

Vb

r01 r02

1

Small signal G = g (r // r ) = g

g

=

m1 01

02

m1

m1

1

1

r01 + r02

gain

+

r02

T2

Vout

Vin

T1

r01

other solutions and has a better DC output swing,

since Vout_max = VDD VDS2_sat and Vout_min = VDS1_sat.

The output of the circuit shown is in an undefined state (highimpedance node). This circuit needs therefore an external system to

fix its output DC bias point (we need a feedback network!).

Puebla, December 2004

CSS-CSL = Common Source Stage with Current Source Load

W1 = 100 m

L1 = 0.5 m

Load Transistor

1.2E-04

1.4E-03

2.5

1.0E-04

1.2E-03

8.0E-05

gm [ S ]

6.0E-05

1.5

W2 = 800 m

L2 = 4 m

1.0E-03

IDS [ A ]

V out [ V ]

Input Transistor

8.0E-04

6.0E-04

4.0E-05

4.0E-04

Vout

0.5

2.0E-05

Ids

0

0.0E+00

0

0.5

1.5

2.0E-04

0.0E+00

2.5

Vin [ V ]

Puebla, December 2004

0.5

Vin [ V ]

Giovanni Anelli, CERN

1.5

2.5

Small signal simulations

0.64

101

Vin [ V ]

100.8

0.636

100.7

0.634

100.6

0.632

100.5

0.63

100.4

0

Ids [ A ]

100.9

0.638

0.638

1.5

1.4

0.636

1.3

0.634

1.2

0.632

1.1

0.63

1

0

10

V out [ V ]

Vin [ V ]

1.6

right bias point (especially for the

output!)

With a current of just 100 A and the

same input transistor dimensions as in

the case of the CSS with load resistor,

we have a gain of 373.

10

t [ ms ]

0.64

frequency 1 kHz, peak to peak amplitude

1 mV and DC offset = 0.635 V.

what it should be. The bias point is so

critical that the simulator has some

problems

t [ ms ]

Puebla, December 2004

This circuit is the same as the CSS with Current Source load, but the

gate bias of transistor T2 is low enough to make sure that T2 works in

the linear region and therefore it behaves as a resistor.

VDD

Vb

T2

Vout

Vin

G = gm1

T1

1

PCox

W2

(VDD Vb VTP )

L2

Vb < Vout VTP (where VTP is a positive number). If we

can not take Vb < 0 V, we can take it = 0 V. In this

case we must have Vout > VTP.

depends on many parameters.

Puebla, December 2004

VDD

RD

Vout

Vin

RS

drain current upon the gate overdrive voltage

introduces excessive non linearity. RS smoothes this

effect since it takes a portion of the gate overdrive

voltage. At the limit, for RS >> 1/gm, the small signal

gain does not depend on gm (and therefore on IDS)

anymore.

It is interesting to note that the approximated small

signal gain (which can be easily calculated with the

small signal equivalent circuit) can also be calculated

as if RS and 1/gm were two resistors in series.

Small signal gain

(approximation)

gm

G=

=

RD

1

1 + gmR S

+ RS

gm

RD

The approximated small signal voltage gain can also be seen as the product of

the small signal equivalent transconductance of the degenerated CS Stage

multiplied by the total resistance seen at the output (RD).

To calculate the exact small signal voltage gain we need the exact small signal

equivalent transconductance and the output resistance of the degenerated CS

Stage. Both these quantities can be calculated with the equivalent small signal

circuits.

VDD

RD

(approximation)

G=

gm

R D = gm _ eq R D

1 + gmR S

Vout

Vin

RS

gmr0

equivalent

gm _ eq =

R S + r0 + (gm + gmb ) R S r0

transconductance

(with channel length

DO IT YOURSELF

modulation and bulk effect)

AS AN EXERCISE!

Calculation of the output resistance of the degenerated CS Stage.

G

ix

Vin

vx

D

ix

gmbVBS

RS

B

ix = gm v s +

Puebla, December 2004

ro

gmVGS

vx vs

gmb v s

r0

RS

v s = i xR S

vx

=

= r0 + R S + (gm + gmb ) r0R S

ix

Giovanni Anelli, CERN

vx

Exact small signal gain of the degenerated CS Stage.

VDD

Approximated small

signal gain

Gappr . =

gm

R D = gm _ eq R D

1 + gmR S

RD

Vout

Vin

degenerated CS Stage

RS

Exact small signal gain

gm _ eq =

G = gm _ eq R out

gmr0

R S + r0 + (gm + gmb ) R S r0

Exercise: try to obtain the same equation with the complete small signal circuit

Puebla, December 2004

The analysis of the Common Source Stage (CSS) with current source load

demonstrated that to have a high voltage gain we have to have a high load

impedance. If we want to use a CSS to drive a low impedance load, we

have to put a buffer between the CSS and the load. The simplest buffer

is the Source Follower (also called Common Drain Stage).

VDD

use the small signal equivalent circuit or we can be

clever and reuse what we have seen up to now!

Vin

Vout

RS

G=

G=

Vout

1

= gm R S //

Vin

gm + gmb + 1/ r0

gm

gm + gmb +

1

1

+

r0 R S

gm R S

1 + (gm + gmb ) R S

The gain of our buffer is never one! It is, in the best case, 1/n

Puebla, December 2004

The Source Follower with a resistor is highly non linear, since the drain

current in T1 is a strong function of the input DC level.

We can therefore replace the resistor with a current source.

1

gm1

=

GSF _ NMOS = gm1 r02 //

gm1 + gmb1 + 1/ r01 gm1 + gmb1 + 1/ r01 + 1/ r02

VDD

Vin

T1

Vout

Vb

T2

The circuit is still non linear due to the body effect

(non linear dependence of VT1 upon the source

potential). This can be solved using a PMOS

Source Follower, in which both the transistors

have the body (well) connected to the source. In

this case, we have:

1

gm1

=

GSF _ PMOS = gm1 r02 //

gm1 + 1/ r01 gm1 + 1/ r01 + 1/ r02

Puebla, December 2004

1

gm1

=

G = gm1 R L // r02 //

gm1 + 1/ r01 gm1 + 1/ r01 + 1/ r02 + 1/ R L

VDD

Vb

T2

Vout

Vin

RL

T1

gm1

RL

=

gm1 + 1/ R L R L + 1/ gm

impedance, we risk to have a gain which is

significantly smaller than one. Another

important drawback is that source followers

shift the signal by one VGS. This is a

drawbacks especially in low voltage circuit,

where this causes a limitation in the voltage

headroom. On the other hand, if the power

supply voltage is high enough, source

followers can be used as voltage level shifters.

Giovanni Anelli, CERN

In Common-Source Stages and Source Followers the input signal is applied to

the gate. We can also apply it to the source, obtaining what is called a

Common-Gate Stage (CGS)

VDD

RD

Vout

Vb

R in =

1 + R D / r0

R D + r0

=

gm + gmb + r0 1 + (gm + gmb ) r0

G=

Vin

R out _ CGS = r0

G=

R out

R in _ R D =0

EXERCISE!

r (gm + gmb ) + 1

RD

= RD 0

gm n R D

R in

R D + r0

The input impedance of a CGS is relatively low, but this only if the load

impedance in low. The gain is slightly higher to the one of a CSS, since we

apply the signal to the source. N.B. We have calculated the small signal gain

using 2 different methods (red and blue). The results are identical!

Puebla, December 2004

With the results obtained, it is now very easy to study the most general case,

which includes the impedance RS of the signal source, the channel modulation effect

and the bulk effect. Lets call Rin the resistance seen by the ideal voltage source.

R D + r0

R in = R S +

1 + (gm + gmb ) r0

VDD

RD

Vout

Vb

RS

vin

R D = v out

R in

v out R D

1 + (gm + gmb ) r0

G=

=

= RD

vin

R in

R S [1 + (gm + gmb ) r0 ] + R D + r0

This result is very similar to the one of a Common Source

Stage with source degeneration. The gain here is still

slightly higher due to the body effect. It is now also easy

to calculate the resistance seen into the output.

+

Vin

Giovanni Anelli, CERN

The cascade of a Common-Source Stage (V-I converter) and of a

Common-Gate Stage is called a Cascode.

VDD

v out

RD

r01

= vin gm1

RD

R D + r02

r01 +

1 + (gm2 + gmb 2 ) r02

REMINDER

I

Vout

Vb

Vin

T2

T1

R1

G = gm1

r01

R D gm1R D

R D + r02

r01 +

1 + (gm2 + gmb 2 ) r02

I1 =

case of a Common-Source Stage.

R2

I

R1 + R 2

R2

One nice property of the cascode stage can be discovered looking at the

resistance seen in the drain of T2. This is quickly done if we look at T2 as

a Common-Source Stage with a degeneration resistor = r01.

Rout

Vb

Vin

T2

R out _ CascS = r01 + r02 + (gm2 + gmb2 ) r01r02 (gm2 + gmb2 ) r01r02

T1

boosted by a factor (gm2 + gmb2) r02.

output voltage is now the sum of the saturation voltages of T1 and T2.

It must therefore be used with care in low voltage circuits.

Puebla, December 2004

To fully profit of the high output impedance of the cascode stage, it

seems natural to load it with a high impedance load, like a current source.

VDD

Vb1

T3

Vout

Vb2

Vin

G gm1R out

T2

T1

principle to boost the output impedance of the

current source as well.

N.B. Remember that the DC output level here is not

well defined, and that we will need a feedback loop.

VDD

Vin

VDD

RD

T1

Ib

Vout

T2

Vb

Vin

T1

Vb

T2

Vout

Ib

RD

This solution is has a lower output impedance than the standard CascS

and consumes more current for the same performance.

Puebla, December 2004

Outline

Single-stage amplifiers

The differential pair

Differential signal advantages

The differential pair

Large Signal Analysis

Small Signal Analysis

Common Mode Rejection Ratio (CMMR)

Differential Pair Mismatch

Differential pair + active current mirror

Operational amplifier (op amp) design

Puebla, December 2004

Single-Ended vs Differential

A single-ended signal is defined as a signal measured with respect to a

fixed potential (usually, ground).

A differential signal is defined as a signal measured between two nodes

which have equal and opposite signal excursions. The center level in

differential signals is called the Common-Mode (CM) level.

The most important advantage of differential signals over single-ended

signals is the much higher immunity to environmental noise.

As an example, lets suppose to have a disturbance on the power supply.

VDD

VDD

RD

Vout_SE

RD

Vout +

RD

Vout -

Single-Ended vs Differential

The Common-Mode disturbances disappear in the differential output.

Vdd

Vout_SE = Vout +

Vout Vout_diff

VDD

Vin1

RD

Vin,CM

RD

Vout1

Vin2

Vout2

Vout2

Vin1

Vin2

ISS

Vout,CM

Vout1

since it makes the sum of the currents in the two

ISS

=

v

V

R

branches (I1 + I2= ISS) independent from the input

out ,CM

DD

D

2

common mode voltage.

The output common mode voltage is then given by:

Puebla, December 2004

Differential Pair

VDD

VDD

RD

Vout1

RD

Vout1

Vout2

Vout2

Vin1

VDD - RD ISS

Vin1 - Vin2

Vin2

Vout1 - Vout2

RD ISS

ISS

the slope of this plot

Puebla, December 2004

Vin1 - Vin2

- RD ISS

To better understand what can be the maximum voltage excursion of the

input, we substitute the ideal current source with a real one.

VDD

RD

RD

Vout1

Vin1

vin,CM _ max

Vout2

T1

Vb

T2

T3

Vin2

ISS

= min VDD R D

+ VT 1 , VDD

2

excursion of the output?

v out _ max = VDD

With the basic transistor equations, some patience and some mathematics we can

obtain the equation for the plot shown.

Vout1 - Vout2

vlim =

RD ISS

2ISS

/n

ID1 ID2 = I

Vlim

Vin1 - Vin2

- Vlim

v out = R D I

- RD ISS

I = ISS

For vlim < Vin < vlim

4ISS

2

I =

Vin

Vin

2n

/n

I = ISS

Puebla, December 2004

Deriving the current difference as a function of the input voltage

difference we obtain the transconductance Gm of the differential pair.

I

Gm

ISS

- Vlim

Vlim

Vin

4ISS

2

2Vin

/n

I

=

Gm =

Vin 2n 4ISS

2

Vin

/n

Puebla, December 2004

Vin

Vlim

- Vlim

vin = 0

Gm =

2 ISS

n 2

From the transconductance Gm of the differential pair when the differential

stage is balanced (vin = 0), we obtain the small signal gain G.

Gm =

2 ISS

n 2

v out = R D I = R D Gm vin

v out

2 ISS

= RD

G=

vin

n 2

It is the transconductance in strong inversion of a transistor carrying

a current ISS/2 ! So we can write

G = R D gm

Puebla, December 2004

Now that we know it, is is quite obvious to recognize it looking again at

the circuit schematic.

VDD

RD

RD

Vout1

Vin1

Vout2

T1

Vb

T2

Vin2

common source stages with

degenerated resistor, and

superimpose the effects.

Or, even better, we can realize that

the point P is (ideally) AC grounded.

v out1 = gm R D vin1

v out 2 = gm R D vin2

T3

We have seen that ideally in a differential pair the output voltage does not depend

on the common mode input voltage. But in fact the non infinite output impedance

r03 of the current source has an influence, since the point P do not behave as an

AC ground anymore. The symmetry in this circuit suggests that we can see it as

two identical half circuits in parallel. This makes the analysis much easier.

VDD

VDD

RD

RD

Vout1

Vin1

RD

Vout2

T1

Vb

T2

A CSS with source

degeneration. Easy

Vin2

Vout

Vin,CM

T1

GCM =

2r03

T3

v out

RD

=

vin,CM

1/ gm + 2r0

The variation of the common mode output voltage with the common mode input

voltage is generally small and not so worrying. MUCH MORE concerning is when

we have a differential output as a consequence of a common mode variation at

the input! This can happen if the circuit is not fully symmetric (mismatch!).

Let's call GCM-DM the gain of this common-mode to differential-mode conversion.

A difference in the transconductances of the two transistors, for example, would

give:

gm R D

GCMDM =

(gm1 + gm2 ) r03 + 1

We see that it is essential to have a good current source (very high r03).

To make possible a meaningful comparison between different differential circuit,

we want to compare the undesirable differential output given by a common mode

input variation and the wanted differential output given by a differential input.

We define the Common Mode Rejection Ratio (CMRR) as:

CMRR =

g

transconductance mismatch, we obtain CMRR m (1 + 2gmr03 )

gm

G

GCMDM

To analyze the two circuits we can now make use of the half-circuit

concept and profit from all the results obtained up to now.

1

g

G = gmN

// r0N // r0P mN

gmP

gmP

VDD

T3

VDD

T4

T1

T2

Vin2

Vin1

ISS

T3

T4

T1

T2

ISS

Vb

Vout2

Vout1

Vout2

Vout1

Vin1

Vb

Vin2

And, of course, the gain can be boosted using common-gate stages.

VDD

Vb3

T7

T8

Vb3

Vb2

T5

T6

Vb2

Vout1

Vb1

Vin1

T3

T4

T1

T2

Vout2

lot in the past, when the

supply voltages were

relatively high (few volts).

Vin2

In deep submicron

technologies they are used

with more care.

Vb1

ISS

Puebla, December 2004

The two transistors have the same drain current

VGS =

2

Vth

+

/

gm

22

VGS [mV ] 20

18

16

14

/ = 1 . 4 %

VT = 4.5 mV

12

10

8

2I

VT

6

4

2

0

1.E-02

1.E-01

1.E+00

1.E+01

I.C.

Puebla, December 2004

1.E+02

1.E+03

Outline

Single-stage amplifiers

The differential pair

The current mirror

Standard Current Mirror

Cascode Current Mirror

Low-voltage Cascode Current Mirror

Current Mirror Output Impedance

Current Mirror Mismatch

Operational amplifier (op amp) design

We suppose that all the transistors have the same , Cox and VT.

is the same if the transistors have the same L

VDD

IREF

WR

LR

I1

I2

W1

L1

W2

L2

W1

(1 + 1VDS1 )

L

I1 = IREF 1

WR

(1 + R VDSR )

LR

GND

transistor identical AND they must have the same VDS. When this is not

possible, choosing long devices reduces the effect of .

Precise current ratios can be obtained playing with the ratio between

the transistor widths (not the lengths!).

Puebla, December 2004

0.25 m technology, VDD = 2.5 V, IREF = 100 A, WR = W1 = 100 m, LR = L1

0.12

@ VDS1 = 2.5 V

0.1

I1 [ mA ]

0.08

VDS1 _ min_ SI =

0.06

2I1

Coxn( W1 / L1 )

VDS1 _ min_ WI = 4n t

0.04

L = 10 um

L = 0.5 um

0.02

0

0

0.5

1.5

2.5

VDS1 [ V ]

Puebla, December 2004

T1

L = 0.5

[m]

L = 10

[m]

ID [A]

106

100.3

[mA/V2]

60.54

2.488

gm [mS]

1.77

0.594

VT [mV]

635.7

635.6

VGS [mV]

636.7

943

VDS_sat [mV]

70.76

269.7

Rout [M]

0.866

14.5

VG3 must be fixed so that VD1 = VD2.

I3

VDD

IREF

VD3

W3

L3

VG3

VD1

VD2

W1

L1

W2

L2

GND

obtain that the current I3 practically does not

depend on the voltage VD3. Of course, all the

devices must be in saturation (the circuit is

not suitable for low voltage applications).

I3 = IREF

VD2

(gm3

W2 / L 2

W1 / L1

VP

+ gmb 3 ) r03

Puebla, December 2004

VDD

Transistors 1 & 2 decide the current ratio.

IREF

I3

VD3

W4

L4

W3

L3

VD1

VD2

W1

L1

W2

L2

GND

4 suffer from body effect.

I3 = IREF

W2 / L 2

W1 / L1

W2 / L 2 W3 / L 3

=

W1 / L1 W4 / L 4

The problem of this current mirror is that VD3 > VDS3 + VGS2.

Puebla, December 2004

0.25 m technology, VDD = 2.5 V, IREF = 100 A

0.12

@ VD3 = 2.5 V

T2

T3

ID [A]

100

100

0.08

[mA/V2]

60.54

13.08

0.06

gm [mS]

1.676

1.211

VT [mV]

635.7

852

VGS [mV]

636.7

962.4

VDS_sat [mV]

70.75

128.7

Rout [M]

0.108

1.037

I3 [ mA ]

0.1

0.04

W1 = W2 = 100 m

L1 = L2 = 0.5 m

W3 = W4 = 50 m

L3 = L4 = 1 m

0.02

0

0

0.5

1.5

2.5

VD3 [ V ]

Puebla, December 2004

VDD

IREF

I3

VD3

W4

VB

L4

VD1

W3

L3

VD2

W1

L1

GND

W2

L2

compared to the standard cascode current

mirror is that here we can lower the voltages

VD1 and VD2 to the limit of the saturation of

transistors T1 and T2.

I3 = IREF

W2 / L 2

W1 / L1

W2 / L 2 W3 / L 3

=

W1 / L1 W4 / L 4

The minimum output voltage (VD3) here is just two saturation voltages.

Puebla, December 2004

0.25 m technology, VDD = 2.5 V, IREF = 100 A

@ VD3 = 2.5 V

0.12

T2

T3

ID [A]

100

100

0.08

[mA/V2]

60.5

13.57

0.06

gm [mS]

1.641

1.208

VT [mV]

635.7

692.4

VGS [mV]

642.5

798.3

VDS_sat [mV]

72.87

123.6

Rout [M]

0.021

1.6

I3 [ mA ]

0.1

W1 = W2 = 100 m

L1 = L2 = 0.5 m

W3 = W4 = 50 m

L3 = L4 = 1 m

0.04

0.02

0

0

0.5

1.5

2.5

VD3 [ V ]

Puebla, December 2004

0.12

VDD

0.1

IREF

I3 [ mA ]

0.08

I3

VD3

0.06

can lower the voltage

VB until it reaches the

limit VGS3 + VDS2_sat

0.04

0.02

W4

VB

L4

VD1

VD2

W1

L1

0

0.4

0.6

0.8

1.2

1.4

VB [ V ]

Puebla, December 2004

W3

L3

GND

W2

L2

0.12

IOUT [ mA ]

0.1

Vout_min

Precision

CM

VDS1_sat

CCM

VGS2 + VDS3_sat

Good

LVCCM

VDS2_sat + VDS3_sat

Good

0.08

0.06

0.04

CM - L = 1 um

0.02

LVCCM

CCM

0

0

0.5

1.5

VOUT [ V ]

Puebla, December 2004

2.5

CCM

Standard CM

VDD

VDD

LVCCM

Vout

WR

LR

W1

L1

GND

rout = r01

Puebla, December 2004

Iout

Iout

Vout

Iout

Vout

IREF

IREF

IREF

VDD

W4

L4

W3

L3

W1

L1

W2

L2

GND

W4

L4

Vb

W1

L1

GND

Giovanni Anelli, CERN

W3

L3

W2

L2

The two transistors have the same gate voltage

I/I =

I/I [%]

2

/

gm

+

Vth

I

14

/ = 1 . 4 %

12

VT = 4.5 mV

10

8

6

4

2

0

1.E-02

1.E-01

1.E+00

I.C.

Puebla, December 2004

1.E+01

1.E+02

1.E+03

Outline

Single-stage amplifiers

The differential pair

The current mirror

Differential pair + active current mirror

Common mode, small signal and large signal analysis

Noise

Offset

Current mirrors can also process a signal, and they can therefore be used

as active elements. A differential pair with an active current mirror is also

called a differential pair with active load. The current mirror here has also

the important role to make a differential to single-end conversion!

VDD

T3

T4

Vout

T2

T1

Vin

Maximum output excursion

Vb

T5

Giovanni Anelli, CERN

Lets now calculate the small-signal behavior, neglecting the bulk effect for

simplicity. The circuit is NOT symmetric, and therefore we can not use the halfcircuit principle here. As a first approximation, we can consider the common

sources of the input transistors as a virtual ground. The small-signal gain G can

be seen as the product of the total transconductance of the stage and of the

output resistance.

G = Gm R out

VDD

v

v

iout = gm1 in gm2 in = gm1,2 vin

T3

T4

2

2

iout

iout

V

G

=

= gm1,2

out

+

m

vin

2

T1

T2

vin

2

ISS

vin

In reality, the current source is not ideal, and this has an effect on the gain we

have just calculated. This effect is in general negligible. What is not negligible is

the effect of r05 on the common mode gain. For a common mode input signal the

circuit can be seen symmetric! It can be shown that even for a perfectly

symmetric circuit (no mismatch) a CM signal at the input (vin,CM) generates an

unwanted signal at the output (vout).

VDD

T3

bulk effect and r01,2)

T4

Vout

Vin,CM

T2

T1

Vb

Puebla, December 2004

T5

GCM

Vout

=

Vin,CM

r03 ,4

1

//

2gm3,4

2

=

=

1

+ r05

2gm1,2

gm1,2

1

=

1 + 2gm1,2r05 gm3,4

Giovanni Anelli, CERN

Noise in a DP + Active CM

VDD

VDD

2I

2I

vin2

vin2

v 2tot

i2out

2

vload

2

vload

v 2tot

Puebla, December 2004

2

2

g

m _ load

2

vload

= 2 v in + 2 2

g

m

_

in

i2out

Noise in a DP + Active CM

VDD

2

tot _ 1 / f

1

f

= 2 2

1+

2

Cox WinLin f

K a _ in in Lload

K a _ in

2I

v

2

tot

v 2tot _ th

load

2

L load

= 4kTn

1+

W

Win

2 inCox

I

in

L

in

Lin

W

W

Make >

L in L load

Puebla, December 2004

Offset of a DP + Active CM

RANDOM OFFSET (WORST CASE)

VDD

v off = VT 1,2 +

2I

I

gm1,2

1,2 3 ,4 gm3 ,4

+

+

V

T 3,4

3,4

I

1,2

SYSTEMATIC OFFSET

v off

Vin

T1

T2

Vout

T3

of T1 and T2 gives origin a difference

in the DC currents in the two

branches.

T4

As we have already seen, a common

mode signal at the input gives a non

zero output voltage signal.

List of Acronyms

CSS:

Common-Source Stage

CSS-CSL:

SF:

CGS:

Common-Gate Stage

CascS:

FCascS:

DP:

Differential Pair

CM:

Current Mirror

CCM:

LVCCM:

CMRR:

sorry

Outline

Single-stage amplifiers

The differential pair

The current mirror

Differential pair + active current mirror

Frequency analysis of an amplifier

Operational amplifier (op amp) design

Single-stage op amps

Two-stage op amps

NONINVERTING

CONFIGURATION

INVERTING

CONFIGURATION

R2

Vin

Vout

Vin

Vout

R1

R1

R2

BUFFER

Vin

Vout = Vin

R2

G=

R1

R

G = 1+ 2

R1

G=1

The above equations are valid only if the gain of the op-amp is very high!

Puebla, December 2004

Single-stage Op Amp

VDD

T7

Vb2

T8

T5

T6

Vb2

Vout

Vb1

T3

T4

T1

T2

Vin

Vb1

adopted to make a Single-stage

amplifier. If high gains are needed, we

can use, for example, cascode

structures.

With single-stage amplifiers it is difficult

to obtain at the same time high gain and

voltage excursion, especially when

other characteristics are also required,

such as speed and/or precision.

Two-stage configurations in this sense

are better, since they decouple the gain

and voltage swing requirements.

ISS

Two-stage Op Amp

G = gm1,2 (r01,2 // r03 ,4 ) gm5 ,6 (r05 ,6 // r07 ,8 )

is very often a CSS,

since this allows

the maximum

voltage swing.

VDD

T3

T4

T5

Vb1

T1

T6

swing in this case

is VDD - |2VDS_SAT|

T2

Vin

Vout1

Vout2

ISS

Vb2

T7

T8

Two-stage Op Amp

G = { gm1,2 [(gm3 , 4 + gmb 3 , 4 )r03 , 4r01,2 )] // [(gm5 ,6 + gmb 5 ,6 )r05 ,6r07 ,8 )] } gm9 ,10 (r09 ,10 // r011,12 )

VDD

Vb3

T7

T8

Vb3

Vb2

T5

T6

Vb2

To increase the

gain, we can again

make use, in the

first stage, of

cascode structures.

T9

T10

Vb1

Vout1

T3

T4

T1

T2

Vb1

Vout2

Vin

Vb4

T11

ISS

T12

Vb4

Two-stage Op Amp

G = gm1,2 (r01,2 // r03 , 4 ) gm6 (r06 // r08 )

also have a single-ended

output. In this case, we

kept the differential

behavior of the first

stage, and is the current

mirror T7-T8 which does

the differential-to-single

ended conversion.

VDD

T3

T4

T5

Vb

T1

T6

T2

Vin

Vout

ISS

T7

T8

- For HobbiestEnviado porSingam Sridhar
- Linear Integrated CircuitsEnviado pordhaamini
- Instrumentation AmplifierEnviado porsarpanch
- Simple LM386 Audio AmplifierEnviado poragus alim
- CONTROL_SYSTEMS_AND_SIMULATION_LAB.docEnviado porkiran_y2
- Air Conductivity 3Enviado porsameasbefore
- Electronics - Operational AmplifiersEnviado porengr
- Kreatryx GATE 2018 ECE Solutions.pdfEnviado porjohnarulraj
- Logic Probe With Op. Amp. with Dual JFET Input Op Amp - 8 Pin DIP.docxEnviado porDavid Novelo
- Differential Amplifier 8Enviado pornavinchopra1986
- Operational AmplifiersEnviado porazizah
- manual.pdfEnviado porPalaparthy Venkata Mahesh
- OTA Opamp TestingEnviado porCarlos Muñinovich
- AD744_cEnviado porapi-3701386
- Base PaperEnviado porMukul Sharma
- LM358Enviado porAnonymous sIAUue
- Multiple Choice Questions and Answers on Op-Amp ( Operational Amplifier ) – Electronics PostEnviado porDurga Devi
- Opamp design materialEnviado porNishant Singh
- 04541956Enviado porsukumar78
- 74HC_HCT244_CNV_2Enviado porjd_alvahdz
- IEEE_802.15.4_ZigBeeTM_Compliant_IF_Limi.pdfEnviado porMuhammad Faqih
- Ch2 Elements of EEEnviado porNizzy Izzy
- MODULE 1-NAS.pdfEnviado poradil
- Electrocardiography (1) FinishEnviado porSangeeta Indoi
- AnalogEnviado porsrishaharidas
- ECEF - CopyEnviado porparveshnain19
- Terminal Op Amp-1Enviado porBagus dwi
- analog electronics question bankEnviado porAkshay
- BD6046Enviado porpepejuan
- MIT2_737F14_Lab2Enviado porOSIRIS

- Logic Lab 1 - Digital Abstraction (5 Gates)Enviado porram010
- TA2003Enviado porcalinsat
- 2SB596Enviado pornugroho_budi
- 1W and 5W Power AmplifierEnviado porMikeVive
- CD4069UBCEnviado porJordy Israel Melo Pulecio
- mdt 2005Enviado pornot book
- IC-LAB-ALLEnviado porRaghu Kasula
- Scheme of evaluation.pdfEnviado porlakkepogu
- Prathap-eBot-lightfollowerEnviado porPrathap Naiudu
- AD9852_p_a.pdfEnviado porbtanmay
- VHDL experimentsEnviado porsandeepsingh93
- Avr2011_classEnviado porमेनसन लाखेमरू
- Basic Circuit for 8051Enviado poruatulkar
- VHDL Code for Flipflop – D,JK,SR,TEnviado porSaurabh Bhise
- clock gating circuits.pdfEnviado porTej Pal Singh
- Pmod AD1_rmEnviado por0307ali
- Adv Ckt Technique Using GmIdEnviado pornarashimaraja
- Walt's Blog 2014 References & RegulatorsEnviado porNicolas
- Millimeter-Wave Bist PaperEnviado porChuan Lee
- MOSFET Biasing Using a Current MirrorEnviado porSandeep Pandey
- Santosh FPGAEnviado porSantosh Kumar Modekurty
- Theory_questions-ECE+3337a-Midterm+Final (1)Enviado porgsolisre
- eel100Enviado porJaya Mukesh
- NortonEnviado porHelium Vivek
- LF347Enviado porNarendra Bhole
- 1308_12297 A New Class-D Stereo Audio Amplifier Using Direct Speaker Current ControlEnviado porrodales56
- TLC555Enviado pormarcioalbano
- Usart With HerculesEnviado pormieh
- Atenuator in PiEnviado porLaurentiu Iacob
- FFC solved2Enviado pormuzamil saeed