DATE

:04.03.2015

TITLE

: ENHANCEMENTS FOR LONG TAIL PAIR AND OUTPUT STAGES

OBJECTIVES:
1. To become familiar with the characteristics of long-tail pair
- Effect of frequency on- Common / Differential mode output
-Common/ Differential gain
-CMRR
2. To identify the effects of mismatches in long tail pair
- Input offset voltage
- Input offset current
3. To understand the operation of a current mirror and identify the effects of some
parameters
- Wilson current source
4. Observe the cross-over distortion of output stages and elimination
- Class B push pull amplifiers

PART 1- Frequency Response of Long Tail Pair

PROCEDURE:

First, the schematic diagram was drawn. Then, 1Hz -1GHz was selected as the frequency range. After that
the variation of the two gains were ploted along with frequency. Next, the CMRR Vs frequency was
obtained.
For differential mode

1 5 .0 0 V

Q 1
0V
0 .0 1 V a c
0Vdc

V3

V+

R 1

R 2

1k

1k
1 4 . 2Q8 2V
B CV -5 4 9 C

1 4 . 2 8 VV +

0V
V2

0V

BC 549C

-0 .0 1 V a c
0Vdc
R 4

0V

V1
15Vdc

-6 4 3 .5 m V

V4

V-

15Vdc

0V

10k
-1 5 .0 0 V

Schematic Diagram for Differential Mode

Fig 01:

600mV

400mV

200mV

0V
1.0Hz
10Hz
V(R1:1,R2:1)
V(Q1:b,V4:+)

100Hz

1.0KHz

10KHz

100KHz

1.0MHz

10MHz

100MHz

1.0GHz

Frequency

Fig 02: Output Voltage and Input Voltage Vs Frquency

30

20

10

0
1.0Hz
10Hz
V(R1:1,R2:1) / V(Q1:b,V4:+)

100Hz

1.0KHz

10KHz

100KHz

1.0MHz

10MHz

100MHz

Frequency

Fig 03: Voltage Gain Vs Frequency

For common mode

1 5 .0 0 V
R 11

R 22

1k

1k

1 4 .2 8 V
Q 11

V11
15Vdc

1 4 . 2Q8 2V 2
BC 549C

0V
V22

0V
0 .0 2 V a c
0Vdc

V33

BC 549C

15Vdc

-6 4 3 .5 m V
R 44
0V

10k
-1 5 .0 0 V

Fig 04: Schematic Diagram for Common Mode

1.0GHz

20mV

15mV

10mV

5mV

0V
1.0Hz
V(R11:1)

10Hz
V(Q11:b)

100Hz

1.0KHz

10KHz

100KHz

1.0MHz

10MHz

100MHz

1.0GHz

100MHz

1.0GHz

Frequency

Fig 05: Output Voltage and Input Voltage Vs Frquency

1.0

0.5

0
1.0Hz
10Hz
V(R11:1) / V(Q11:b)

100Hz

1.0KHz

10KHz

100KHz

1.0MHz

10MHz

Frequency

Fig 06: Voltage Gain Vs Frquency

300

200

100

0
1.0Hz
10Hz
100Hz
1.0KHz
(V(Q1:c,Q2:c) / V(V3:+,V4:+)) /(V(Q11:c)/V(V3:+))

10KHz

100KHz

1.0MHz

10MHz

100MHz

1.0GHz

Frequency

Fig 07: Common Mode Rejection Ratio Vs Frequency

COMMENTS
Common Mode Rejection Ratio indicates the ability of the amplifier to accurately cancel voltages that are
common to both inputs. When the frequency is increased CMRR is getting lower. So, only lower
frequency will cancel the voltages that are common to both inputs.

DISCUSSION
What are the reasons to observe the frequency response of the amplifiers?

We can know in which region, the amplifier amplifies the input signal accurately. We can get an
idea of the linear region of the amplifier by observing the frequency response.

PART 02: Device Mismatches Effects on the Differential Pair

A. Input offset Voltage

PROCEDURE:
First, the schematic diagram was drawn. Then, the voltage source was selected as Vac=0.02V,Vdc=0V After
that DC sweeps were carried out and the Vod was observed. Graphs were plotted for following cases.
Next, a temperature sweep was carried out along with DC sweep.

Q 11

R 11

R 22

1k

1k

V11
15Vdc

Q 22
B CV -5 4 9 C

V+

V22
BC 549C
0 .0 2 V a c
0Vdc

15Vdc

V33

R 44
10k

Fig 08: Schematic Diagram for Input Offset Voltage

2.0V

1.0V

0V

-1.0V

-2.0V
-200mV
-160mV
V(R11:1,R22:1)

-120mV

-80mV

-40mV

0mV

40mV

80mV

V_V33

Fig 09: Vod Vs Input Voltage (No mismatch)

120mV

160mV

200mV

R 11

R 22

1k

1k

Q 11

V11
15Vdc

Q 23
B CV -5 4 6 A

V+

V22
BC 549C
0 .0 2 V a c
0Vdc

15Vdc

V33

R 44
10k

Fig 10: Schematic Diagram for Input Offset Voltage (Q2=BC546A)

2.0V

1.0V

0V

-1.0V

-2.0V
-200mV
-160mV
V(R11:1,R22:1)

-120mV

-80mV

-40mV

0mV

40mV

80mV

120mV

V_V33

Fig 11: Vod Vs Input Voltage (Q2=BC546A)

Q 11

R 11

R 22

1k

1k

V11
15Vdc

Q 1
B CV -5 4 9 B

V+

V22
BC 549C
0 .0 2 V a c
0Vdc

15Vdc

R 44
10k

Fig 12: Schematic Diagram for Input Offset Voltage (Q2=BC549C)

160mV

200mV

1.5V

1.0V

0.5V

-0.0V

-0.5V

-1.0V

-1.5V
-200mV
-160mV
V(R11:1,R22:1)

-120mV

-80mV

-40mV

0V

40mV

80mV

120mV

160mV

200mV

V_a

Fig 13: Vod Vs Input Voltage (Q2=BC549C)

TABLE 01: Offset Voltages for Different Cases

Q1
BC549C
BC549C
BC549C

Q2
BC549B
BC546A
BC549C

Vos /mV
-0.8
-1.0
0

COMMENTS
When the two transistors are matched, the input offset voltage is zero. When they are different, the input
offset voltage should have a value in order to have a zero output because the voltages and currents in the
branches are different.

RC1 = 1.2k

R 11

R 22

1 .2 k

Q 11

1k

V11
15Vdc

Q 25
B CV -5 4 9 C

V+

V22
BC 549C
0 .0 2 V a c
0Vdc

15Vdc

V33

R 44
10k

Fig 14: Schematic Diagram for Input Offset Voltage (RC1=1.2K)

2.0V

1.0V

0V

-1.0V

-2.0V
-200mV
-160mV
V(R11:1,R22:1)

-120mV

-80mV

-40mV

0mV

40mV

80mV

120mV

160mV

200mV

V_V33

Fig 15: Vod Vs Input Voltage (RC1=1.2K)

COMMENTS
Vos=0.5mV

When the RC1 is changed, the current going through the two transistors will be different. So the output will
not be 0V when the input given is 0V. In order to have a zero output there should be an input voltage.
Therefore, there should be an offset voltage in the circuit.
Temperature sweep

Q 11

R 11

R 22

1k

1k

V 11
15V dc

Q 25
B CV 5- 4 9 C

V+

V 22
BC 549C
0 .0 2 V a c
0V dc

15V dc

V33

R 44
10k

Fig 16: Schematic Diagram for the Temperature Sweep

2.0V

1.0V

0V

-1.0V

-2.0V
-200mV

-160mV
V(R11:1,R22:1)

-120mV

-80mV

-40mV

0mV

40mV

80mV

V_V33

Fig 17: Variation of Vod with Temperature

120mV

160mV

200mV

Input offset current

R 11

R 22

1k

1k

Q 11

V11
15V dc

Q 25
B CV -5 4 9 C

V+

V22
B C 549C

15V dc

I1

I2

2uAdc

R 44

2uA dc

10k

Fig 18: Schematic Diagram for Input Offset Current (No mismatch)

2.0V

1.0V

0V

-1.0V
-2.0uA
-1.5uA
-1.0uA
V(R11:1,R22:1)

-0.5uA

0A

0.5uA

1.0uA

1.5uA

2.0uA

2.5uA

3.0uA

3.5uA

4.0uA

4.5uA

I_I1

Fig 19: Vod Vs Input Current (No mismatch)

Q 11

R 11

R 22

1k

1k

V11
15Vdc

Q 1
BC 549B

V+

V-

V22
BC 549C

15Vdc

a
2uAdc

I2
R 44

2uAdc

10k

Fig 20: Schematic Diagram for Input Offset Current (Q2=BC549B)

5.0uA

5.5uA

6.0uA

1.0V

0.5V

-0.0V

-0.5V

-1.0V

-1.5V

-2.0V
-2.0uA
-1.5uA
-1.0uA
V(R11:1,R22:1)

-0.5uA

0A

0.5uA

1.0uA

1.5uA

2.0uA

2.5uA

3.0uA

3.5uA

4.0uA

4.5uA

5.0uA

5.5uA

6.0uA

5.0uA

5.5uA

6.0uA

I_a

Fig 21: Vod Vs Input Current (Q2=BC549B)

Q 11

R 11

R 22

1k

1k

V11
15Vdc

Q 2
BC 546A

V+

V-

V22
BC 549C

15Vdc

I2

2uAdc

R 44

2uAdc

10k

Fig 22: Schematic Diagram for Input Offset Current (Q2=BC546A)

0.5V

-0.0V

-0.5V

-1.0V

-1.5V

-2.0V

-2.5V
-2.0uA
-1.5uA
-1.0uA
V(R11:1,R22:1)

-0.5uA

0A

0.5uA

1.0uA

1.5uA

2.0uA

2.5uA

3.0uA

3.5uA

4.0uA

4.5uA

I_a

Fig 23: Vod Vs Input Current (Q2=BC546A)

TABLE 02: Offset Currents for Different Cases

Q1
BC549C
BC549C
BC549C

Q2
BC549B
BC546A
BC549C

Ios /uA
1.10
1.55
0

COMMENTS
When the transistors are different, the current of the each branch will be different. So the output voltage
will not be zero. In order to have a zero output, there should be an input offset current.

What is meant by the input bias current? What is the difference between the input bias current and Ios in an
amplifier?

The current drawn from the input is called as the input bias current. The difference between the
input bias current is called as the input offset current.

DISCUSSION
What are the different kinds of device mismatches, the reasons for them to occur and their effects?
Systematic mismatch

The reasons for them to occur are non-uniform thermal distribution during the fabrication process
and lens aberration during the photolithographic process.
Mismatch affects electrical parameters of the transistor, which in turn differ between two
identically drawn devices. Consequently the operating point and other circuit characteristics differ
from their desired values

Stochastic mismatch

The main reason for the statistical component is the variation of the fabrication process, caused by
random microscopic device architecture fluctuations, such as statistical variations in the number of
dopant atoms, built-in electrical charges, gate-oxide thickness, edge roughness, etc.

Random mismatch

The random mismatch of semiconductor devices caused by local variations of the production
process strongly influences critical performance parameters of analog circuits. It affects for the
threshold voltage, the gain factor and the mobility reduction.

What are the parameters that will affect the values of Ios and Vos ?

Saturation current
Value of the Rc resistor
Current gain
Collector current

PART 3
PROCEDURE:
First, the schematic diagram was drawn. Then, the values of Vdc were changed and values for Vo, Iref, and
Io were obtained. After that a DC sweep was carried out and the variations were plotted.

Q 14

R 45

R 46

15k

1k
BC 549C

V13
15Vdc

Q 12

Q 13

V12
1Vdc

BC 549C

BC 549C

Fig 24: Schematic Diagram for the Wilson Current Source

60V

40V

20V

0V
0V

5V

10V

15V

20V

25V

30V

35V

40V

V(Q14:c)
V_V12

Fig 25: Vod Vs Vo

R 45

Q 14

R 46

15k

1k

BC 549C

V13
15Vdc

Q 12

Q 13

V12
1Vdc

BC 549C

BC 549C

Fig 24: Schematic Diagram for the Wilson Current Source

45V

50V

1.0mA

0.5mA

0A

-0.5mA

-1.0mA
0V
-I(R45)

5V
IC(Q14)

10V

15V

20V

25V

30V

35V

40V

45V

50V

V_V12

Fig 25: Vod Vs Io and Iref

TABLE 03: Variation of Vod Vs Vo, Io and Iref

VDC
0
1
2
3
4
5
6
7
8
9
10
15
20
25
30
35
40
45
50

VO
0
0
1
2
3
4
5
6
7
8
9
14
19
24
29
34
39
44
49

Iref / mA
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9

Io
-0.6
0.3
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9
0.9

COMMENTS

For higher VDC values Iref=Io

DISCUSSION
Check the effect of the resistor inside the network on Iref and Io

When the resistor value is increased, higher value of Vdc is needed to reach the condition
Iref=Io but when the resistor value is decreased, lower value of V dc will reach the condition
Iref=Io

1.0mA

0.8mA

0.6mA

0.4mA

0.2mA

0A

-0.2mA
0V
-I(R45)

5V
IC(Q14)

10V

15V

20V

25V

30V

35V

40V

45V

50V

40V

45V

50V

V_V12

FIG 26: Vdc Vs Iref and Io when R46=5k

1.0mA

0.5mA

0A

-0.5mA

-1.0mA
0V
-I(R45)

5V
IC(Q14)

10V

15V

20V

25V

30V

35V

V_V12

FIG 26: Vdc Vs Iref and Io when R46=0.1k