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DM54LS374/DM74LS374
TRI-STATE Octal D-Type Transparent
Latches and Edge-Triggered Flip-Flops
General Description
Features
Y
Y
Y
Y
Connection Diagrams
Dual-In-Line Packages
LS373
Order Number
DM54LS373J,
DM54LS373W,
DM74LS373N or
DM74LS373WM
See NS Package Number
J20A, M20B, N20A or
W20A
TL/F/6431 1
LS374
Order Number
DM54LS374J,
DM54LS374W,
DM74LS374WM or
DM74LS374N
See NS Package Number
J20A, M20B, N20A or
W20A
TL/F/6431 2
TRI-STATE is a registered trademark of National Semiconductor Corp.
C1995 National Semiconductor Corporation
TL/F/6431
RRD-B30M105/Printed in U. S. A.
DM54LS373/DM74LS373, DM54LS374/DM74LS374
TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
May 1992
The eight latches of the DM54/74LS373 are transparent Dtype latches meaning that while the enable (G) is high the Q
outputs will follow the data (D) inputs. When the enable is
taken low the output will be latched at the level of the data
that was set up.
The eight flip-flops of the DM54/74LS374 are edge-triggered D-type flip flops. On the positive transition of the
clock, the Q outputs will be set to the logic states that were
set up at the D inputs.
Function Tables
DM54/74LS373
DM54/74LS374
Output
Control
Enable
G
Output
Output
Control
L
L
L
H
H
H
L
X
H
L
X
X
H
L
Q0
Z
L
L
L
H
Clock
Output
u
u
H
L
X
X
H
L
Q0
Z
L
X
H e High Level (Steady State), L e Low Level (Steady State), X e Dont Care
e Transition from low-to-high level, Z e High Impedance State
Q0 e The level of the output before steady-state input conditions were established.
Logic Diagrams
DM54/74LS373
Transparent Latches
DM54/74LS374
Positive-Edge-Triggered Flip-Flops
TL/F/64313
TL/F/6431 4
7V
7V
b 65 C to a 150 C
Operating Free Air Temperature Range
b 55 C to a 125 C
DM54LS
DM74LS
0 C to a 70 C
DM54LS373
Parameter
DM74LS373
Units
Min
Nom
Max
Min
Nom
Max
4.5
5.5
4.75
5.25
VCC
Supply Voltage
VIH
VIL
0.7
0.8
IOH
b1
b 2.6
mA
IOL
24
mA
tW
Pulse Width
(Note 2)
12
Enable High
15
15
Enable Low
15
15
tSU
5v
5v
tH
20v
20v
TA
b 55
125
V
V
ns
ns
ns
70
v) indicates the falling edge of the clock pulse is used for reference.
Parameter
Conditions
VI
VOH
VCC e Min
IOH e Max
VIL e Max
VIH e Min
VOL
Min
DM54
Typ
(Note 1)
2.4
3.4
2.4
3.1
Max
Units
b 1.5
V
V
DM74
VCC e Min
IOL e Max
VIL e Max
VIH e Min
DM54
DM74
IOL e 12 mA
VCC e Min
0.25
0.4
0.35
0.5
DM74
0.4
II
VCC e Max, VI e 7V
IIH
20
mA
IIL
b 0.4
mA
IOZH
20
mA
b 20
mA
Short Circuit
Output Current
VCC e Max
(Note 2)
Supply Current
IOZL
IOS
ICC
0.1
DM54
b 20
b 100
DM74
b 50
b 225
24
40
mA
mA
mA
Symbol
From
(Input)
To
(Output)
Parameter
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
RL e 667X
CL e 45 pF
Min
CL e 150 pF
Max
Min
Units
Max
Propagation Delay
Time Low to High
Level Output
Data
to
Q
18
26
ns
Propagation Delay
Time High to Low
Level Output
Data
to
Q
18
27
ns
Propagation Delay
Time Low to High
Level Output
Enable
to
Q
30
38
ns
Propagation Delay
Time High to Low
Level Output
Enable
to
Q
30
36
ns
Output Enable
Time to High
Level Output
Output
Control
to Any Q
28
36
ns
Output Enable
Time to Low
Level Output
Output
Control
to Any Q
36
50
ns
Output Disable
Time from High
Level Output (Note 3)
Output
Control
to Any Q
20
ns
Output Disable
Time from Low
Level Output (Note 3)
Output
Control
to Any Q
25
ns
DM54LS374
Parameter
DM74LS374
Units
Min
Nom
Max
Min
Nom
Max
4.5
5.5
4.75
5.25
VCC
Supply Voltage
VIH
VIL
0.7
0.8
IOH
b1
b 2.6
mA
IOL
24
mA
tW
Pulse Width
(Note 4)
12
Clock High
15
15
Clock Low
15
15
tSU
20u
20u
tH
1u
1u
TA
b 55
Note 1: The symbol ( ) indicates the rising edge of the clock pulse is used for reference.
Note 4: TA e 25 C and VCC e 5V.
125
ns
ns
ns
70
Parameter
Conditions
Min
Typ
(Note 1)
Max
Units
b 1.5
VI
VOH
VCC e Min
IOH e Max
VIL e Max
VIH e Min
DM54
2.4
3.4
DM74
2.4
3.1
VCC e Min
IOL e Max
VIL e Max
VIH e Min
DM54
0.25
0.4
DM74
0.35
0.5
IOL e 12 mA
VCC e Min
DM74
VOL
II
V
0.25
0.4
VCC e Max, VI e 7V
IIH
20
mA
IIL
b 0.4
mA
IOZH
Off-State Output
Current with High
Level Output
Voltage Applied
20
mA
Off-State Output
Current with Low
Level Output
Voltage Applied
b 20
mA
Short Circuit
Output Current
VCC e Max
(Note 2)
Supply Current
IOZL
IOS
ICC
0.1
DM54
b 50
b 225
DM74
b 50
b 225
27
mA
mA
45
mA
Parameter
CL e 45 pF
Min
Max
35
CL e 150 pF
Min
Units
Max
fMAX
tPLH
20
28
32
ns
tPHL
28
38
ns
tPZH
28
44
ns
tPZL
28
44
ns
tPHZ
20
ns
tPLZ
25
ns
MHz
DM54LS373/DM74LS373, DM54LS374/DM74LS374
TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
National Semiconductor
Europe
Fax: (a49) 0-180-530 85 86
Email: cnjwge @ tevm2.nsc.com
Deutsch Tel: (a49) 0-180-530 85 85
English Tel: (a49) 0-180-532 78 32
Fran3ais Tel: (a49) 0-180-532 93 58
Italiano Tel: (a49) 0-180-534 16 80
National Semiconductor
Hong Kong Ltd.
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
National Semiconductor
Japan Ltd.
Tel: 81-043-299-2309
Fax: 81-043-299-2408
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.