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Transactions Briefs
A 0.311 GHz Fast-Corrected Duty-Cycle Corrector
With Successive Approximation Register for
DDR DRAM Applications
Young-Jae Min, Chan-Hui Jeong, Kyu-Young Kim, Won Ho Choi,
Jong-Pil Son, Chulwoo Kim, and Soo-Won Kim

AbstractThis brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The
proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its
controller and an output buffer. In order to achieve fast duty-correction
with a small die area, a SAR-controller is exploited as a duty-correction
controller. The proposed DCC circuit has been implemented and fabricated in a 0.13- m CMOS process and occupies 0.048 mm . The measured
duty-cycle error for the 50% duty-rate is below 1% (or 10 pS) within
320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz
and dissipates 3.2 mW at 1 GHz.
Index TermsDouble data rate (DDR), DRAM, duty-cycle corrector
(DCC), successive approximation register (SAR) controller.

I. INTRODUCTION
For many high-speed systems such as double data rate (DDR)
DRAM, double sampling analog-to-digital converter (ADC) and half
rate clock data recovery (CDR), both positive and negative transition
edges of a clock are utilized to double the data rate. In such applications, the clock duty-cycle should be held close to 50%. Duty-cycle
correctors (DCCs) are widely used to adjust the clock duty-cycle
to 50%. Since improving the speed of computer systems demands
low-power high-speed memory such as DDR3 and emerging DDR4
DRAMs, it has become more important to develop a low-power
high-performance DCC.
A lot of effort [1][9] has been devoted to achieve low-power highperformance DCCs with better duty-cycle accuracy, wider duty-correction range and short duty-correction time. Conventional DCCs can be
classified into non-feedback and feedback DCCs. The non-feedback
digital DCCs [1][3] have the advantage of fast duty-correction and
low-power operation. However, the DCCs utilizing interpolation have
speed limitations on the maximum operation frequency [1], [2] and the
open-loop characteristic cannot track the process, voltage and temperature (PVT) variations. In general, it needs complex calibration and
trimming circuitry for compensating PVT variations, which increases
Manuscript received December 07, 2010; revised April 21, 2011; accepted
May 22, 2011. Date of publication June 27, 2011; date of current version
June 14, 2012. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MEST)
(No.K20902001448-10E0100-03010) and Nano IP/Soc Promotion Group of
Seoul R&BD Program (10920).
Y.-J. Min, C.-H. Jeong, K.-Y. Kim, C. Kim, and S.-W. Kim are with
the School of Electrical Engineering, Korea University, Seoul 136-701,
Korea
(e-mail:
yjmin@asic.korea.ac.kr;
kjch5286@asic.korea.ac.kr;
90-kim@asic.korea.ac.kr; ckim@korea.ac.kr; swkim@korea.ac.kr).
W. H. Choi and J.-P. Son are with the Memory Division, Samsung Electronics
Corporation, Hwasung, Gyeonggi 445-701, Korea (e-mail: wh.choi@samsung.
com; jp.son@samsung.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2011.2158011

Fig. 1. Block diagram of the proposed SAR-DCC.

the area overhead. The analog-feedback DCCs usually adopt the negative feedback scheme. Since charge pumps [4] or integrators [5] are
used to provide the feedback, the analog DCCs can achieve higher dutycycle accuracy. However, the analog-feedback leads to long duty-correction time. Moreover, it requires extremely complex designs to maintain stable operation. In addition, in the DRAM applications with the
power-down mode, in order to keep the correction information during
the power-down mode, the DCC control has to be digitally controllable.
All digital-feedback DCCs [6], [7] can recover the 50% duty-cycle
within the very short duty-correction time. However, DCCs adopt complicated duty-cycle detector structures such as a time-to-digital converter (TDC)-based detector [6], which increases the cost of hardware
implementation and the performance of TDC such as the linearity can
degrade the entire DCC performance. Other mixed-mode digital-feedback DCCs contain the duty-cycle detector with the simple analog circuits of amplifier [8] or integrator and comparator [9]. However, these
DCCs suffer from long duty-correction time.
In this brief, in order to achieve fast duty-correction with small chip
area and low-power consumption, a mixed-mode DCC circuit using a
digital-feedback by the successive approximation register (SAR) controller to support the power-down mode of the state-of-the-art DDR
DRAMs is proposed. This brief is organized as follows. In Section II,
the architecture and operation of the proposed SAR-DCC circuit are
described. Also, the effectiveness of first exploiting the SAR controller
in the DCC circuit is discussed. Section III describes details of the implemented circuit. Section IV shows the experimental results of the proposed circuit. Finally, the brief is concluded in Section V.
II. PROPOSED SAR-DCC
Fig. 1 shows the block diagram of the proposed SAR-DCC circuit,
which consists of a duty-cycle detector, a duty-cycle adjuster, its
controller and an output buffer. The exploited SAR controller, which
adopts the binary search algorithm, controls the duty-cycle adjuster to
correct the clock duty-cycle by 50%. The duty-cycle detector in this
brief just checks whether or not the positive duty-rate OUT is bigger
than 50%. It can be called a duty-rate comparator.
The flowchart of -bit SAR-DCC operation is depicted in Fig. 2.
When the signal Start goes to HIGH, the duty-cycle correction begins
with initializing the control signals of the duty-cycle adjuster. All bits
of the SAR control word Ctrl are set to LOW. The duty-rate comparing
bit Sign of the input clock CLKIN is determined by the signal Comp,
which is the output signal of the duty-cycle detector in the case of no
duty-cycle correction of CLKIN . The determined Sign contains the information about whether the duty-cycle adjuster increases or decreases

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Fig. 3. Timing diagram of the 6-bit SAR-DCC when the positive duty-rate of
is 39%.
the clock input

Fig. 2. Flowchart of the proposed SAR-DCC.

the duty-rate of the output clock CLKOUT . After this determination,

the duty-cycle correction is executed according to the binary search algorithm of the successive approximation. The sequential addition and
subtraction of the binary-weighted duty-rate by Ctrl values, which is
determined via the sequential values of Comp, adjusts the duty-cycle
of CLKOUT to 50%. Finally, the signal End goes to HIGH, which can
provide the end information of the duty-cycle correction to the delay
locked-loop (DLL) in DDR DRAMs. The aim of using bit Sign is to reduce the chip area of the duty-cycle adjuster by reducing the duty-cycle
correction elements of the delay-lines. The details are discussed in
Section III. Fig. 3 shows the timing diagram of our 6-bit SAR-DCC
when the positive duty-rate of IN is 39%. When Start goes to HIGH,
Ctrl is initialized and Sign is determined as LOW. After ck , the 6-bit
binary weighted duty-correction to adjust the duty-cycle to 50% is executed by the successive approximation of the binary search.
The SAR-DCC essentially contains a quantization error of a half
of the minimum duty-correction amount (=0.5 LSB) by digitally
controlled duty-cycle adjuster. The standard of state-of-the-art DDR
DRAMs requires a duty-cycle error of 3% or less [10]. This work
uses the minimum duty-correction amount of a 10 pS to achieve a 1%
duty-cycle error at the clock frequency of 1 GHz. The duty-correction
range depends on the minimum duty-correction amount and total
duty-correction cycles. In the case of the proposed 6-bit SAR-ADC
as shown in Fig. 3, the LSB of duty-correction corresponds to 10 pS
and the MSB of duty-correction corresponds to 320 pS. Therefore,
the correction range of the proposed SAR-DCC with an operation
frequency of 312.5 MHz is 40% to 60%, and one with an operation
frequency of 1 GHz is 18% to 82%. In designing state-of-the-art DDR
DRAM circuits, this correction range is acceptable.
All digital-feedback DCCs [6], [7] can adjust the clock duty-cycle
to 50% within only 1 clock cycle. As shown in Fig. 2, the proposed

Fig. 4. (a) Block diagram and (b) timing diagram of the duty-cycle adjuster.

N -bit SAR-DCC circuit requires N + 1 clock cycles. In spite of the

additional N clock cycles required for 50% duty-correction, the pro-

posed SAR-DCC has the advantages of simpler hardware complexity

and smaller chip area than the conventional all digital-feedback DCCs,
which results in high portability to process and low cost of hardware
implementation. One of the highest hardware implementation costs in
almost all DCCs is that of the duty-cycle adjuster [3]. The hardware
cost of duty-cycle detector in all digital-feedback DCC usually is almost the same as that of the duty-cycle adjuster. However, the proposed
SAR-DCC can utilize a simple duty-cycle detector, which just checks
whether or not the positive duty-rate is bigger than 50%, while the all
digital-feedback one extracts -bit information of duty-rate from the
input clock. Especially, the adaption of analog duty-cycle detector as a
duty-rate comparator can significantly reduce the hardware complexity
and chip area.

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TABLE I
PERFORMANCE SUMMARY AND COMPARISONS OF PUBLISHED DCCS

Fig. 5. (a) Block diagram and (b) operation principle of the duty-cycle detector.

rising edge generator with dummy delay lines, latch, and MUX.
The falling edge generator performs the duty-rate adjustment with
the non-inverted or inverted signal CKin of the input clock CLKIN
by MUX selection and 6-bit control signals Ctrl[5 : 0] of the programmable delay line.
The previous delay-line based duty-cycle adjuster circuits use falling
edge generators [9] or both rising and falling edge generators [3], [7]
for the duty-rate adjustment. Since a lower frequency operation is also
required in DDR DRAM applications, the delay lines of the previous
correction circuits are increased. In the case of the conventional singleedge-used and dual-edge-used circuits, the required minimum amount
of the delay line is the period of the lowest operation frequency for
the full correction range of 650%. In order to reduce delay lines, we
use only a falling edge generator with the input-inversion MUX for
duty-rate adjustment. While the conventional circuits without the signal
inversion require at least 128 delay cells for the required correction
range of this work, the length of the delay cells in our adjuster is 64. At
the first period of the duty-correction, there is no duty-rate change for
the Sign determination of the input clock duty-cycle. The Sign lets the
non-inverted clock input or the inverted one through as a clock input of
duty-cycle adjuster CKin as shown in Fig. 4(b). In this case, it cannot
guarantee the fixed-delay rising-edge (or falling-edge) clock. However,
if the phase detector with the selectable edge comparison of the rising
edge or falling edge is comprised in the DLL as a clock generator, the
Sign information can be provided to DLL, which can be used as the
synchronization information of the DLL. The main drawback of this
adjuster may be that the DLL requires a specially designed phase detector that selectively compares the rising and falling edges according
to the control signal Sign from the DCC, which results in a complicated
DLL design.
B. Duty-Cycle Detector

III. CIRCUIT IMPLEMENTATION

A. Duty-Cycle Adjuster
The DDR DRAMs require wide operation frequency range with
digitally controllable duty-cycle adjuster for the power-down mode.
Adopting the phase mixer as a duty-cycle adjuster can achieve better
duty-correction resolution. However, it is hard to achieve the wide
operation frequency range. In this work, we adopted digitally programmable delay lines [3], [7], [9]. Fig. 4(a) shows a block diagram of
the proposed duty-cycle adjuster. The adjuster consists of a variable
falling edge generator with 6-bit programmable delay lines, fixed

The duty-cycle detector of the duty-rate comparator comprises an

analog amplifier of the logic amplifier, regenerative latch and inverter
buffers as shown in Fig. 5(a) [8], [11]. The first folded preamplifier
converts the differential clock signals into differential current signals
and amplifies the current difference, which is integrated into the capacitors C1 and C2. The second differential latch amplifies the integrated
voltage difference to a full swing digital signal. Since the duty-rate
comparator operates at high speed, the first stage of the preamplifier
requires wide bandwidth. In this work, the first stage is designed with
consideration of the tradeoff between gain and bandwidth. Also, the
bias voltages are externally calibrated in order to reduce the mismatch

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Fig. 6. 6-bit SAR-controller circuit: (a) the 6-bit SAR-controller and (b) the modified start circuit of the SAR with the Sign bit determination.

Fig. 7. Die photo of the proposed SAR-DCC.

Fig. 9. Measured duty-cycle accuracy at 330 MHz and 1 GHz.

Fig. 8. Measured transient results of the duty-cycle correction with

error input at 330 MHz.

010% duty

of the integrated current and offset of the latch over the process variation. Fig. 5(b) shows the operation principle of the duty-rate comparator. The comparator in this work evaluates and determines the dutyrate at the falling edge of the divided-by-2 clock CLK_2X for the reset
phase of the equalization function, which doubles the duty-cycle correction from 7 to 14 cycles.
C. SAR-Controller
Fig. 6(a) shows a 6-bit SAR block diagram with an additional Sign
register, which uses one of the most compact SARs with small chip area
[12]. The SAR determines the value of each bit of the control word Sign
and Ctrl according to the sequential binary search based on the output
of the duty-rate comparator Comp. The modified start circuit with the
divided-by-2 clock CLK_2X, start signal Start and Sign bit is shown in
Fig. 6(b). After the duty-cycle correction of the LSB determination in

Fig. 10. Measured jitter histogram of the corrected output at 1 GHz.

the SAR registers, this SAR circuit gives the information End of the
correction finish, which goes to HIGH after determining Ctrl[0]. The
digitally stored data in SAR can support the power-down mode for the
DDR DRAMs.
IV. EXPERIMENTAL RESULTS
The prototype of the proposed SAR-DCC has been fabricated in a
standard 0.13-m single-poly six-metal CMOS technology with a 1.2
V supply voltage and occupies 280-m 2 270 m with two input and
output buffer drivers for testing and power rings, excluding I/O pads
and coupling capacitors. The active area is 0.048 mm2 . The die photo of
the proposed ADC core is shown in Fig. 7. The chip has been mounted
on a standard PCB and directly wire-bonded for testing.
Fig. 8 shows the measured output clock waveform of the SAR-DCC
during the duty-cycle correction process with -10% input duty-cycle
error at 330 MHz. Within 14 cycles, the output of the DCC is corrected
to 50%. The measured correction error of the DCC at 330 MHz and

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1 GHz is less than 61% as shown in Fig. 9. The measured input frequency range is 312.5 MHz to 1 GHz. Fig. 10 shows the measured
the peak-to-peak and rms jitter for 1 GHz output clock is 15.5 ps and
2.05 ps, respectively after 21 270 hits. Power consumption is measured as 3.2 mW at 1 GHz. The performance summary of the proposed
SAR-DCC is given in Table I, and the performance comparisons with
published DCCs are also listed. Among the conventional feedback type
DCCs, the all digital-feedback DCC with the large delay lines has the
smallest duty-correction time [6]. Comparing with the DCC in [6], the
proposed SAR-DCC has the faster duty-correction time as well as occupying a smaller die area by adopting a simple duty-rate comparator.
V. CONCLUSION
In this brief, a SAR-DCC for DDR DRAM applications is presented.
In order to achieve fast duty-correction with small die area and to support the power-down mode, a SAR-controller is proposed as a duty-correction controller. Within 14 cycles, the proposed DCC corrects the
duty-cycle to 50% within the frequency range of 312.5 MHz to 1 GHz
and the DCCs correction range is 40% to 60%, respectively. The proposed SAR-DCC achieves the fastest duty-correction time among feedback type DCCs.
Since the duty-cycle adjuster uses delay lines and the duty-cycle
detector comprises the differential amplifier, the proposed SAR-DCC
may suffer from PVT variations including noises. During the
duty-cycle correction, the PVT variations in the duty-cycle adjuster
may introduce errors in the correction range and minimum correctible
amount, which can be minimized by enhancing the LSB resolution and
increasing the delay line length. The correction accuracy error mainly
arises from the duty-cycle detector, which is externally calibrated in
this work. However, while the all digital-feedback DCCs suffer from
TDC imperfection over the variations, this SAR-DCC with a duty-rate
comparator can relax the requirement of process-tolerant duty-cycle
detector. After the duty-cycle correction, the supply voltage/temperature variations may break the duty-rate of 50%. By applying
the periodic signal Start for duty-cycle correction from the DRAM
controller, the proposed SAR-DCC can keep the 50% duty-rate.

[6] Y.-J. Wang, S.-K. Kao, and S.-I. Liu, All-digital delay-locked loop/
pulsewidth-control loop with adjustable duty cycles, IEEE J. SolidState Circuits, vol. 41, no. 6, pp. 12621274, Jun. 2006.
[7] J. C. Ha, J. H. Lim, Y. J. Kim, W. Y. Jung, and J. K. Wee, Unified alldigital duty-cycle and phase correction circuit for QDR I/O interface,
IET Electron. Lett., vol. 44, no. 22, pp. 13001301, Oct. 2008.
[8] K.-S. Song, C.-H. Koo, N.-K. Park, K.-W. Kim, Y.-J. Choi, J.-H. Ahn,
and B.-T. Chung, A single-loop DLL using an OR-AND duty-cycle
correction technique, in Proc. IEEE Asian Solid-State Circuit Conf.
(ASSCC), 2008, pp. 245248.
[9] Y. C. Jang, S. J. Bae, and H. J. Park, CMOS digital duty cycle correction circuit for multi-phase clock, IET Electron. Lett., vol. 39, no. 19,
pp. 13831384, Sep. 2003.
[10] Double Data-Rate III (DDRIII) SDRAM Specification, JEDEC Standard JESD79-3B, Apr. 2008. [Online]. Available: http://www.jedec.
org/download/search/JESD79-3B.pdf
[11] K.-L. J. Wong, H. Hatamkhani, M. Mansuri, and C.-K. K. Yang, A
27-mW 3.6-Gb/s I/O transceiver, IEEE J. Solid-State Circuits, vol. 39,
no. 4, pp. 602612, Apr. 2004.
[12] G.-K. Dehng, J.-M. Hsu, C.-Y. Yang, and S.-I. Liu, Clock-deskew
buffer using a SAR-controlled delay-locked loop, IEEE J. Solid-State
Circuits, vol. 35, no. 8, pp. 11281136, Aug. 2000.

ZeROA: Zero Clock Skew Rotary Oscillatory Array

Vinayak Honkote and Baris Taskin

AbstractResonant rotary clocking is a clocking technology for high frequency clock generation and distribution at a low power dissipation rate.
It is commonly conceived that the multiple phases on the rings of the rotary oscillatory array (ROA) necessitate a non-zero clock skew operation.
In this paper, the feasibility of zero clock skew synchronization with the
rotary clocking technology implemented on the ROA is shown. Design automation experiments are performed to demonstrate that the zero clock
skew operation can be achieved with minimal change in the performance
of rotary clock operation. In particular, a marginal 1.5% change in the
tapping wirelength and a negligible 0.38% average skew mismatch are reported in experiments on R1R5 and ISPD 2010 benchmark circuits.
Index TermsDesign automation, design methodology, oscillators, sequential circuits.

ACKNOWLEDGMENT
The authors would like to thank IC Design Education Center (IDEC)
and the Korea Ministry of Knowledge Economy (MKE) for the fabrication of the chip.

REFERENCES
[1] S.-K. Kao and S.-I. Liu, All-digital fast-locked synchronous dutycycle corrector, IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 53,
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[2] D. U. Lee , H. W. Lee, K. C. Kwean, Y. K. Choi, H. U. Moon, S. W.
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H. Ahn, and J. S. Kih, A 2.5 Gb/s/pin 256 Mb GDDR3 SDRAM with
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I. INTRODUCTION
In deep sub-micrometer integrated circuit (IC) design, synchronization, and timing remain as serious closure problems. These problems
stem partially from the high level of variability in the silicon components (and their timing), and partially from the limitation of the technology that is currently in use to provide the synchronization infrastructure. The latter challengeparticularly the PLL-based clock sources
with long, buffered distribution tree or mesh networks [1]necessitates a tight control over the placement and sizing of the clock buffers
and interconnects. Towards this end, the majority of the research on
clocking remains in improved clock distribution network design. Resonant clocking technologies [2][10] present attractive features (such
Manuscript received July 26, 2010; revised November 08, 2010 and February
21, 2011; accepted May 05, 2011. Date of publication June 30, 2011; date of
current version June 14, 2012. This work was supported in part by the National
Science Foundation CAREER Grant CCF-0845270.
The authors are with the Department of Electrical and Computer Engineering,
Drexel University, Philadelphia, PA 19104 USA (e-mail: vh32@drexel.edu;
taskin@coe.drexel.edu).
Digital Object Identifier 10.1109/TVLSI.2011.2158458

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