Introduction to Embedded Systems

Vaibhav Bedia
Texas Instruments

Designing the next big thing

Location Free TV/Web

Tablet
Portable
Digital TV,
eDictionary,
Low Cost PC
Portable
Navigation,
Portable Games

Portable Data
Terminals/
Point of Sale

???

SDR, Medical,
IP Communications

Smart Home
Media Controllers

Audio + Video +
JPEG + WiFi

The world of microcontrollers

Typical Interfaces Expected

Camera:
CMOS Sensor, PTZ (Pan, Tilt, Zoom)
Display:
16-bit Color LCD, LEDs
Audio:
Hands-free Speakerphone, Handset, Headset; Wideband Codec
Support
External Storage:
USB 2.0 Memory Stick, SD/MMC Card, SATA, PATA

Memory:
Nand, NOR, DDR2, DDR3, mDDR etc
Connectivity
USB, Ethernet, WLAN, PCI/PCIe

MSP 430 Microcontroller Block Diagram

MSP 430 Microcontroller Block Diagram 2

TBD

Essential concepts of SOC

ARM High end programming (Neon, VFB, Thum2, etc )
External Pin connectivity (PIN MUX)

Power Management
Clock Management
Memory configuration
Peripheral Controller
Multi Core Acceleration

Flash / Storage solutions

Debugging
System Validation

System on a chip
TIs Sitara DaVinci & OMAP family of processors
truly integrate an entire embedded system into a
single device.
ARM, Accelerators (DSP, 3D graphics, Neon) and Peripheral
controllers (USB, Video ports, Camera ISP, .)

This integration offers huge benefits:

System Cost
Low Power
Form Factor
Performance

Highly integrated
SOCs enable
leading edge
products

Embedded processing portfolio

TI Embedded Processors
ARM-Based Processors

Microcontrollers (MCUs)

Digital Signal Processors (DSPs)

Software & Development Tools

16-bit ultralow power
MCUs

32-bit
real-time
MCUs

MSP430

C2000
Delfino
Piccolo

32-bit ARM
MCUs

Stellaris

ARM Cortex-M3

Up to
25 MHz

40 MHz to
300 MHz

Up to
80 MHz

Flash
1 KB to 256 KB

Flash, RAM
16 KB to 512 KB

Analog I/O, ADC

LCD, USB

PWM, ADC,
CAN, SPI, I2C

Flash
64 KB to 256 KB
USB, ENET
MAC+PHY, CAN,
ADC, PWM, SPI

Measurement,
sensing, general
purpose

Motor control,
digital power,
lighting, ren. energy

$0.25 to $9.00

$1.85 to $20.00

32-bit ARM
MPUs

DSP
DSP+ARM

Multicore
DSPs

Ultralow power
DSPs

Sitara

C6000
Integra
DaVinci

C6000

C5000

Up to 10GHz
Multicore,
Fixed/Floating
+Accelerators

Up to 300 MHz
16-bit Fixed Point +
FFT Accelerator

ARM Cortex-A8
& ARM9

Value Line to
600 MHz
Perf. Line to 1.5 GHz
Up to 32KB I/D cache
256 KB L2, LPDDR,
DDR2/3 support

Digital Media Processors

300 MHz to >1.5 GHz

Floating DSP +
Video Accelerators

L2 Cache
Up to 4 MBL2,
mDDR, DDR2/DDR3 32 KB L1, 1 MB SL2

Up to 320 KB RAM
Up to 256 KB ROM

Motion control,
HMI, industrial
automation

GEMAC, PCIe+PHY,
SATA+PHY, CAN,
USB+PHY, PRU
Industrial automation,
portable data terminals,
Single-board computing

USB 2.0 OTG, GEMAC,

SATA, SPI, UPP, PRU,
PCIe2.0, McBSP, McASP
Video, audio, voice,
security, conferencing,
test & measurement

RapidIO, PCIe,
10/100MAC,
Hyperlink, DDR2/3
Telecom, medical,
mission critical,
base stations

USB 2.0, ADC, SPI

McBSP, I2C, LCD,
On-chip regulators
Portable audio/voice,
fingerprint biometrics,
portable medical

$1.00 to $8.00

$5.00 to $50.00

$5.00 to $200.00

$40 to $200.00

$2.99 to $10.00

MPUs Microprocessors

TI SOCs

Location Free TV/Web

Tablet
Portable
Digital TV,
eDictionary,
Low Cost PC
Portable
Navigation,
Portable Games

Portable Data
Terminals/
Point of Sale

SDR, Medical,
IP Communications

SOC
Smart Home
Media Controllers

Audio + Video +
JPEG + WiFi

Using the right SOC

OMAP
OMAP

Smart Phones, MIDs, etc

Davinci - DM
Davinci

Video Centric Devices

Sitara - AM
Sitara

Stellaris

ARM Only Applications

Industrial, Instrumentation, medical

Low Power MCU Applications

TI ARM investment and innovation

1st single-chip
digital baseband DSP/ARM
multi-core

Two ARM
Cortex-R4
cores
for
automotive

Introduced DaVinci
processors for
digital video
ARM9-based SoCs

TI
licenses
first
ARM
core

1993

TMS570
MCU

DaVinci

Stellaris
Fury
Class

TI
licenses
Cortex-A9

*TI first licensee for

ARM Cortex- A8

1995

2002
1st multi-core
applications
processor,
ARM9-based
OMAP
OMAP1510

2005

2006

2007

DaVinci
Stellaris
Sandstorm Class

1st ARM
Cortex-A8
based silicon
OMAP
OMAP3

Fixed/
FloatingPoint
Stellaris ARM9
DustDevil SoC
Class
OMAP

Newest DaVinci
solution for
flexible,
HD video

Stellaris
MCU

TI
Acquires
Luminary
Micro

OMAP-L138

2009

2008
Stellaris
Tempest
Class

TI announces
31 new
1st R4F-based
ARM-based
floating-point,
products
dual-core auto
and
introduces
MCU
Sitara family
TMS570F
MCU

TI has shipped over 5 billion ARM-based products and continues to invest

in a large portfolio of scalable platforms from $1 to >1GHz
* TI licensed in July 2003, but publicly announced Oct 2005.

OMAP Cortex-A8 based processors

Benefits
2000DMIPS for OSs like Linux, Win CE, RTOS
Up to 30% reduction in power
20M polygons per second for robust GUIs

OMAP
Processors

ARM

Cortex-A8
800MHz/1 GHz

Sample Applications
Smart connected devices
Patient monitoring
Single board computers
Low power PC
Power
Dynamic Voltage and Frequency Scaling (DVFS)
AVS
Extremely low standby power

Peripheral limitations may apply among different packages

Some features may require third party support
All speeds shown are for commercial temperature range only

32K/32K L1
256K L2

Display Subsystem
3D
Graphics
Accelerator*

LCD Controller

Video
Processing
Front End

Video Encoder

64K SRAM

Video
Input
(12-bit)

10 bit DAC
10 bit DAC

L3/L4 Interconnect
Connectivity

Serial Interface

Memory Interface

USB OTG

McBSP x5

LPDDR1

USB HS Host x3

MCSPI x4

NAND

I2C x3

MMC/SD/SDIO x3

HDQ/ 1-wire

Timers

UART x3

GP x12

UART w/ IrDA

WDT x2

Cortex-A8

TI Base SW/Components

software summary

TI HW/Libraries

ARM Cortex-A8+graphics
User Interface

3rd party/Customer

Application Level Software

Browser/
Media Players

Applications

Application Frameworks Java, Qt, GStreamer, Flash, Android, DShow, Direct Draw

Board Support Package

Linux Open Source TI Developed
Android Open Source TI Funded
Windows Embedded CE TI Owned,
Developed by Microsoft Gold Partner
Commercial Linux and Android Many
Partners
RTOS QNX, VxWorks, Nucleus, Integrity etc.

Video,
Imaging,
Speech,
Audio
Codecs
and
Frameworks
on NEON

OpenGL ES
and OpenVG
Library
On
SGX

2D
Graphics
Library
On
NEON

OS Kernel
ARM Cortex-A8 with on chip USB, High End CAN controller* (HECC) and Ethernet MAC

Accelerators SGX 530 and Neon

OMAP35x, AM35x, AM37x

14

Typical TI Linux SDK Stack

Matrix Application Launcher
ARM
Benchmarks

SGX
Demos

2D Blitrix
Demos

Power/Clock

Web Browser

System Information

WLAN

Qt Embedded

GStreamer
QGLWidget

QWidget
Wifi Stack

BlueZ

FFMPEG
(MPG4, H.264, AAC)

TI BitBLT
(Neon 2DA)

OpenGL ES

FBDEV

V4L2
DSS2

ALSA

VISA

McSPI

Touch
screen

Ethernet

I2C

USB

McBSP

MMC/SD

UART

System on Chip
Target Board

Android Stack

Delivering on the importance of software

Integrated development
environments

Robust operating
system support

Comprehensive software & tools

Libraries & Stacks

DSP

Middleware & Frameworks

LINUX

Multimedia Codecs
Example software and
demos

Software development kits

MPU
TI Code Composer
Studio IDE

Application-specific
algorithms

SYSBIOS

Micrim

Reference designs

Free development
software: Sitaraware,
Stellarisware

MCU
Allowing you to

Reduce learning curve

Accelerate development and time-to-market
Maximize your investment

17

INTRODUCING LINUX

How Linux is built (short video)

Linux - Definition

TI Interest

Linux is loose term for GNU/Linux

Most influential figures

Richard Stallman
Linus Torvalds

The Philosophies of Unix

Everything is a file
Programs should do one thing well
Programs should work together
Text Streams are a universal interface

Versioning
v3.4 released a week back
A release every 2-3 months
Stable series
3.0.Stable - back ported patches (eg 2.6.32.17)

Image courtesy Jonathan Corbet (corbet@lwn.net)

Rapid Development..

Rapid Development..
Over 15 million lines of code!

Rapid Development..

Whos sponsoring the development?

Linux System in Three Parts

Bootloader

Flash

1st, 2nd and 3rd boot loader

Provides rudimentary h/w init
Calls Linux kernel and passes
boot arguments

Kernel
Initializes the system (and device)
Manages system resources
Provides services for user
programs

Filesystem

Single filesystem (/ root)

Stores all system files
After init, kernel looks to
filesystem for whats next
bootarg tells
linux where
to find root
filesystem

Embedded Distributions

OMAP AND THE BEAGLEBOARD

Whats in a name

B ring your own peripherals

E ntry-level cost ($149)
A rm Cortex-A8 (600MHz, superscaler)

G raphics and DSP / Video accelerated

L inux and open source community
E nvironment for software innovators

Targeting community development

$149
> 900 participants
and growing
Active &
technical
community

Open access to
hardware
documentation
Opportunity to
tinker and
learn

Personally
affordable

Wikis, blogs,
promotion of
community
activity
Freedom to
innovate

Instant access to
>10 million lines of
code
Free
software

Fast, low power, flexible expansion

OMAP3530 Processor
600MHz Cortex-A8
NEON+VFPv3
16KB/16KB L1$
256KB L2$
430MHz C64x+ DSP
32K/32K L1$
48K L1D
32K L2
PowerVR SGX GPU
64K on-chip RAM
POP Memory
128MB LPDDR RAM
256MB NAND flash

Peripheral I/O
DVI-D video out
SD/MMC+
S-Video out
USB 2.0 HS OTG
I2C, I2S, SPI,
MMC/SD
JTAG
Stereo in/out
Alternate power
RS-232 serial
USB Powered
2W maximum consumption
OMAP is small % of that
Many adapter options
Car, wall, battery, solar,

And more
Other Features
4 LEDs
USR0
USR1
PMU_STAT
PWR
2 buttons
USER
RESET
4 boot sources
SD/MMC
NAND flash
USB
Serial

On-going collaboration at BeagleBoard.org

Live chat via IRC for 24/7 community support
Links to software projects to download

Peripheral I/O
DVI-D video out
SD/MMC+
S-Video out
USB HS OTG
I2C, I2S, SPI,
MMC/SD
JTAG
Stereo in/out
Alternate power
RS-232 serial

Desktop development
DVI-D

Power

Stereo out

SD

Stereo in
USB

Note: Beagle Board can be powered

from
the alternate jack (as shown) or via
USB

Development on-the-go
Power + IP
over USB
Serial Port

OMAP35x / AM-DM 37x Block Diagram

AM/DM 35xx

Interface to the physical world

The Real
World
Temperature
Pressure
Position
Speed
Flow
Humidity
Sound
Light

Signal
Conditioning

Analog
Signal
Conversion
to Digital

Power
Management

Signal
Conditioning

Digital Signal
Processor

Digital
Signal
Conversion
to Analog

Interface

Clocks & Timers

and present within the virtual

OMAP35x Processor Block Diagram

Cores

Cortex A-8 with NEON Coprocessor

C64x+ DSP-based and video accelerators
600 MHz / 430 MHz @ 1.35V
550 MHz / 400 MHz @ 1.27V
500 MHz / 360 MHz @ 1.2V
2D/3D Graphics Engine (PowerVR SGX)
Up to 10M polygons per second

OMAP35x Processor

C64x+ DSP and

video accelerators
(3525/3530 only)

ARM:
16 kB I-Cache; 16 kB D-Cache; 256kB L2
TMS320C64x+ DSP and video accelerators
L1 32kB Program Cache/32kB Data Cache + 48kB
SRAM
L2 64kB Program / Data Cache + 32 kB SRAM; 16 kB
ROM
On Chip: 64kB SRAM; 112kB ROM

Package

Highlights

12x12 mm, 0.4mm pitch, Package On Package

Samples now; production 4Q08
16x16 mm 0.65 mm pitch. Via Channel Array Tech.
Samples 2Q08; production 4Q08
Industrial temperature range supported

LCD
Controller

ARM
Cortex-A8
CPU

2D/3D
Graphics
(3515/3530 only)

Memory

Display Subsystem

Video 10 bit DAC

Enc 10 bit DAC

Camera I/F
Image
Pipe

Parallel I/F

L3/L4 Interconnect
Peripherals

USB 2.0 HS USB

OTG
Host
Controller Controller x2

Serial Interfaces
McBSP
x5

McSPI
x4

I 2C
x3

UART
x2
UART
w/IRDA

System

Connectivity

HDQ /
1-wire

Timers
GP x12
WDT x2

Program/Data Storage
SDRC
GPMC

MMC/
SD/
SDIO
x3

ARM Cortex-A8
ARMv7 Architecture
Thumb-2
MMU Enhancements
In-Order, Dual-Issue, Superscalar Microprocessor Core

NEON Multimedia Architecture

Over 2x Performance of ARMv6 SIMD
Supports Both Integer and Floating Point SIMD
Jazelle RCT Execution Environment Architecture
Dynamic Branch Prediction

95% Accurate Branch Target Address Cache

across industry benchmarks

Global History Buffer

8-Entry Return Stack

Embedded Trace Macrocell (ETM) Support

Non-Invasive Debug

ARM Cortex-A8 Memory Architecture:

16K-Byte Instruction Cache
4-WaySet-Associative

16K-Byte Data Cache

4-Way Set-Associative

256K-Byte L2 Cache

C64x+ DSP and Accelerators

IVA Subsystem
64x+
DSP

Up to 430 MHz (c64x+ DSP)

Dedicated Enhanced Data Memory Access engine (EDMA) to move data to/from memories and
peripherals external to the sub-system

Video HWA

Video hardware accelerators

EDMA

MMU to access external address space (such as memory/peripheral)

Advanced Very-Long-Instruction-Word TMS320C64x+ DSP Core

Eight Highly Independent Functional Units
Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic
per Clock Cycle
Two Multipliers Support Four 16 x 16-B Multiplies (32-Bit Results) per Clock Cycle or
Eight 8 x 8-Bit Multiplies (16-B Results) per Clock Cycle
64 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size

C64x+ L1/L2 Memory Architecture

32K-Byte L1P Program RAM/Cache (Direct Mapped)
80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
64K-Byte L2 Unified Mapped RAM/Cache (4-Way Set-Associative)
32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM

C64x+ Instruction Set Features

Byte-Addressable (8-/16-/32-/64-Bit Data)
8-Bit Overflow Protection

32KB L1P Cache/RAM

32KB L1D Cache/RAM
48KB L1D RAM
64KB L2 Cache/RAM
32KB L2 RAM
MMU

PowerVR SGX Graphics Engine

Up to ~111 MHz
Tile Based Architecture with up to 10 MPoly/sec

Universal Scalable Shader Engine: Multi-threaded Engine

Incorporating Pixel and Vertex Shader Functionality
Industry Standard API Support:
OpenGLES 1.1 and 2.0
OpenVG1.0
Direct3D Mobile (TBD)

Fine Grained Task Switching, Load Balancing, and Power

Management
Programmable High Quality Image Anti-Aliasing

Graphics Capability Examples

Wave Physics

Environment Mapping & PerPixel lighting

Reflection &
Refraction

Display Subsystem (DSS)

Display Subsystem
LCD
Controller

Video
Enc

10 bit DAC
10 bit DAC

Parallel Digital Output

Up to 24-Bit RGB
HD Maximum Resolution
Supports Up to 2 LCD Panels
Support for Remote Frame Buffer
Interface (RFBI) LCD Panels

2 10-Bit Digital-to-Analog Converters(DACs) Supporting:

Composite NTSC/PAL Video
Luma/Chroma Separate Video (S-Video)
Rotation 90-, 180-, and 270-degrees
Resize Images From 1/4x to 8x
Color Space Converter
8-bit Alpha Blending

Display Subsystem Examples

Scaling
PiP

HW cursor
Overlay

Camera Interface Subsystem (ISP)

CCD and CMOS Imager Interface
Memory Data Input

RAW Data Interface

BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface

A-Law Compression and Decompression

Preview Engine for Real-Time Image Processing

Glueless Interface to Common Video Decoders

Generic parallel interface example

Histogram Module/Auto-Exposure, Auto-White Balance, and

Auto-Focus Engine
Resize Engine
Resize Images From 1/4x to 4x
Separate Horizontal/Vertical Control

Timers
12 32-bit General Purpose Timers
2 32-bit Watchdog Timers
1 32-bit 32-kHz Sync Timer

SD / MMC, SDRC, and GPMC Interface

SD / MMC / SDIO

Three instantiations
Compliant with CE-ATA and ATA for MMCA
1-bit or 4-bit transfer mode specifications for SD and SDIO cards
1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards

General Purpose Memory Controller (GPMC)

SDRC
GPMC

MMC/
SD/
SDIO
x3

Controls all accesses to SRAM and Flash-type memory

8 Chip Selects - 128MB per CS -1GB Total space (8 * 128 MB)
16 bit wide bus
Multiplexed Addr/Data
2KB non-multiplexed
Support for:NAND/NOR Flash, One NAND Flash, SRAM, OneNAND, & Pseudo-SRAM devices

SDRAM Controller (SDRCM) Subsystem

support for low-power or Mobile single-data-rate (LPSDR or M-SDR) and low-power doubledata-rate SDRAM (LPDDR)
16 Mbits, 32 Mbits, 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits , 1 Gbit, and 2 Gbits device
support

USB
USB 2.0 HS OTG Controller

USB 2.0 low-speed (1.5M bit/s), full-speed (12M bit/s), and high-speed (480M bit/s) host
USB 2.0 full-speed (12M bit/s), and high-speed (480M bit/s) peripheral
OTG Support
PHY interface ULPI (HS/FS)

USB Host Controller

USB 2.0 HS
OTG
Controller

USB
Host Controller
x2

Host only
All 3 ports operate in either HS or FS mode (determined by selected PHY connection)
HS Mode
480M bit/s
Available Port 1 & 2
PHY interface ULPI
FS Mode
12M bit/s
Available Port 1, 2, and 3
PHY interface Serial Asynchronous

Serial Interfaces and HDQ/1-Wire

3 Master/Slave High-Speed Inter-Integrated Circuit Controllers (I2C)

5 Multi Channel Buffered Serial Ports (McBSP)

McBSP
x5
McSPI
x4

I 2C
x3

UART
x2
UART
w/IRDA

HDQ /
1-wire

512 Byte Transmit/Receive Buffer (McBSP1/3/4/5)

5K-Byte Transmit/Receive Buffer (McBSP2)
SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix
Operations
Direct Interface to I2S and PCM Device and TDM Buses
128 Channel Transmit/Receive Mode

4 Master/Slave Multi Channel Serial Port Interface (McSPI)

3 UARTs (One with Infrared Data Association [IrDA] and Consumer
Infrared [CIR] Modes)
1 HDQ / 1-Wire

Some cool projects on the BeagleBoard

TBD

References
TBD