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SLAS272F JULY 2000 REVISED JUNE 2004
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description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s.
The MSP430x13x and the MSP430x14x(1) series are microcontroller configurations with two built-in 16-bit
timers, a fast 12-bit A/D converter (not implemented on the MSP430F14x1 devices), one or two universal serial
synchronous/asynchronous communication interfaces (USART), and 48 I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and
process and transmit the data to a host system. The timers make the configurations ideal for industrial control
applications such as ripple counters, digital motor control, EE-meters, hand-held meters, etc. The hardware
multiplier enhances the performance and offers a broad code and hardware-compatible family solution.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000 2004, Texas Instruments Incorporated
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AVAILABLE OPTIONS
PACKAGED DEVICES
TA
40C to 85C
MSP430F133IPM
MSP430F135IPM
MSP430F147IPM
MSP430F1471IPM
MSP430F148IPM
MSP430F1481IPM
MSP430F149IPM
MSP430F1491IPM
MSP430F133IPAG
MSP430F135IPAG
MSP430F147IPAG
MSP430F148IPAG
MSP430F149IPAG
MSP430F133IRTD
MSP430F135IRTD
MSP430F147IRTD
MSP430F1471IRTD
MSP430F148IRTD
MSP430F1481IRTD
MSP430F149IRTD
MSP430F1491IRTD
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
P2.6/ADC12CLK
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
DVCC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
VREF+
XIN
XOUT
VeREF+
VREF/VeREF
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P5.6/ACLK
P5.5/SMCLK
AVCC
DVSS
AV SS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH
P5.4/MCLK
P5.3
P5.2
P5.1
P5.0
P4.7/TBCLK
P4.6
P4.5
P4.4
P4.3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7
P3.6
P3.5/URXD0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
P2.6/ADC12CLK
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
DVCC
P6.3/A3
P6.4/A4
P6.5/A5
P6.6/A6
P6.7/A7
VREF+
XIN
XOUT
VeREF+
VREF/VeREF
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P5.6/ACLK
P5.5/SMCLK
AVCC
DVSS
AVSS
P6.2/A2
P6.1/A1
P6.0/A0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P1.5/TA0
P1.6/TA1
P1.7/TA2
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/Rosc
P2.6
P2.7/TA0
P3.0/STE0
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
DVCC
P6.3
P6.4
P6.5
P6.6
P6.7
Reserved
XIN
XOUT
DVSS
DVSS
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P5.6/ACLK
P5.5/SMCLK
AVCC
DVSS
AVSS
P6.2
P6.1
P6.0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P5.7/TBOUTH
P5.4/MCLK
P5.3/UCLK1
P5.2/SOMI1
P5.1/SIMO1
P5.0/STE1
P4.7/TBCLK
P4.6/TB6
P4.5/TB5
P4.4/TB4
P4.3/TB3
P4.2/TB2
P4.1/TB1
P4.0/TB0
P3.7/URXD1
P3.6/UTXD1
P3.5/URXD0
XOUT
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
P2
8
ROSC
Oscillator
XT2IN
System
Clock
XT2OUT
ACLK
16KB Flash
512B RAM
ADC12
SMCLK
8KB Flash
256B RAM
12-Bit
8 Channels
<10s Conv.
P3
P4
P5
P6
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
Watchdog
Timer
TCK
TDI/TCLK
15/16-Bit
TDO/TDI
Timer_B3
Timer_A3
3 CC Reg
Shadow
Reg
3 CC Reg
POR
Comparator
A
USART0
UART Mode
SPI Mode
MSP430x14x
XIN
XOUT
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
8
ROSC
Oscillator
XT2IN
System
Clock
XT2OUT
ACLK
60KB Flash
2KB RAM
ADC12
2KB RAM
32KB Flash
1KB RAM
12-Bit
8 Channels
<10s Conv.
P2
P3
P4
P5
P6
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
TCK
TDI/TCLK
TDO/TDI
Hardware
Multiplier
MPY, MPYS
MAC,MACS
Watchdog
Timer
15/16-Bit
Timer_B7
Timer_A3
7 CC Reg
Shadow
Reg
3 CC Reg
POR
Comparator
A
USART0
USART1
UART Mode
SPI Mode
UART Mode
SPI Mode
XOUT
DVCC
DVSS
AVCC
P1
AVSS RST/NMI
8
ROSC
Oscillator
XT2IN
System
Clock
XT2OUT
ACLK
60KB Flash
2KB RAM
2KB RAM
32KB Flash
1KB RAM
P2
P3
P4
P5
P6
MCLK
Test
MAB,
4 Bit
MAB,MAB,
16 Bit16-Bit
JTAG
CPU
MCB
Emulation
Module
Incl. 16 Reg.
Bus
Conv
MDB,
16-Bit
MDB,
16 Bit
MDB, 8 Bit
4
TMS
TCK
TDI/TCLK
TDO/TDI
Hardware
Multiplier
MPY, MPYS
MAC,MACS
Watchdog
Timer
15/16-Bit
Timer_B7
Timer_A3
7 CC Reg
Shadow
Reg
3 CC Reg
POR
Comparator
A
USART0
USART1
UART Mode
SPI Mode
UART Mode
SPI Mode
Terminal Functions
MSP430x13x, MSP430x14x
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVCC
AVSS
64
Analog supply voltage, positive terminal. Supplies the analog portion of the analog-to-digital converter.
62
Analog supply voltage, negative terminal. Supplies the analog portion of the analog-to-digital converter.
DVCC
DVSS
63
P1.0/TACLK
12
I/O
P1.1/TA0
13
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK
16
I/O
P1.5/TA0
17
I/O
P1.6/TA1
18
I/O
P1.7/TA2
19
I/O
P2.0/ACLK
20
I/O
P2.1/TAINCLK
21
I/O
P2.2/CAOUT/TA0
22
I/O
P2.3/CA0/TA1
23
I/O
P2.4/CA1/TA2
24
I/O
P2.5/ROSC
P2.6/ADC12CLK
25
I/O
General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency
26
I/O
P2.7/TA0
27
I/O
P3.0/STE0
28
I/O
P3.1/SIMO0
29
I/O
P3.2/SOMI0
30
I/O
P3.3/UCLK0
31
I/O
General-purpose digital I/O/USART0 clock: external input UART or SPI mode, output SPI mode
P3.4/UTXD0
32
I/O
P3.5/URXD0
P3.6/UTXD1
33
I/O
34
I/O
P3.7/URXD1
35
I/O
P4.0/TB0
36
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output
P4.1/TB1
37
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output
P4.2/TB2
P4.3/TB3
38
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output
39
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output
P4.4/TB4
P4.5/TB5
40
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output
41
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output
P4.6/TB6
42
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output
P4.7/TBCLK
P5.0/STE1
43
I/O
44
I/O
P5.1/SIMO1
P5.2/SOMI1
45
I/O
46
I/O
P5.3/UCLK1
47
I/O
General-purpose digital I/O pin/USART1 clock: external input UART or SPI mode, output SPI mode
P5.4/MCLK
48
I/O
49
I/O
P5.5/SMCLK
14x devices only
NO.
I/O
DESCRIPTION
P5.6/ACLK
50
I/O
P5.7/TBOUTH
51
I/O
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance Timer_B7: TB0 to
TB6
P6.0/A0
59
I/O
P6.1/A1
60
I/O
P6.2/A2
61
I/O
P6.3/A3
I/O
P6.4/A4
I/O
P6.5/A5
I/O
P6.6/A6
I/O
P6.7/A7
I/O
RST/NMI
58
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices).
TCK
57
Test clock. TCK is the clock input port for device programming test and bootstrap loader start (in Flash
devices).
TDI/TCLK
55
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI
54
I/O
TMS
56
Test mode select. TMS is used as an input port for device programming and test.
VeREF+
VREF+
10
VREF/VeREF
11
Negative terminal for the ADCs reference voltage for both sources, the internal reference voltage, or an
external applied reference voltage
XIN
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
XT2IN
53
Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT
52
QFN Pad
NA
NA
Test data output port. TDO/TDI data output or programming data input terminal
Terminal Functions
MSP430x14x1
TERMINAL
NAME
NO.
I/O
DESCRIPTION
AVCC
AVSS
64
62
DVCC
DVSS
63
P1.0/TACLK
12
I/O
P1.1/TA0
13
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1
14
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
15
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK
16
I/O
P1.5/TA0
17
I/O
P1.6/TA1
18
I/O
P1.7/TA2
19
I/O
P2.0/ACLK
20
I/O
P2.1/TAINCLK
21
I/O
P2.2/CAOUT/TA0
22
I/O
P2.3/CA0/TA1
23
I/O
P2.4/CA1/TA2
24
I/O
P2.5/ROSC
P2.6
25
I/O
General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency
26
I/O
P2.7/TA0
27
I/O
P3.0/STE0
28
I/O
P3.1/SIMO0
29
I/O
P3.2/SOMI0
30
I/O
P3.3/UCLK0
31
I/O
General-purpose digital I/O/USART0 clock: external input UART or SPI mode, output SPI mode
P3.4/UTXD0
32
I/O
P3.5/URXD0
33
I/O
P3.6/UTXD1
34
I/O
P3.7/URXD1
35
I/O
P4.0/TB0
36
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A or CCI0B input, compare: Out0 output
P4.1/TB1
37
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A or CCI1B input, compare: Out1 output
P4.2/TB2
38
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A or CCI2B input, compare: Out2 output
P4.3/TB3
39
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI3A or CCI3B input, compare: Out3 output
P4.4/TB4
40
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI4A or CCI4B input, compare: Out4 output
P4.5/TB5
41
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI5A or CCI5B input, compare: Out5 output
P4.6/TB6
42
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI6A or CCI6B input, compare: Out6 output
P4.7/TBCLK
43
I/O
P5.0/STE1
44
I/O
P5.1/SIMO1
45
I/O
P5.2/SOMI1
46
I/O
P5.3/UCLK1
47
I/O
General-purpose digital I/O pin/USART1 clock: external input UART or SPI mode, output SPI mode
P5.4/MCLK
48
I/O
P5.5/SMCLK
49
I/O
NO.
I/O
DESCRIPTION
P5.6/ACLK
50
I/O
P5.7/TBOUTH
51
I/O
General-purpose digital I/O pin/switch all PWM digital output ports to high impedance Timer_B7: TB0 to
TB6
P6.0
59
I/O
P6.1
60
I/O
P6.2
61
I/O
P6.3
I/O
P6.4
I/O
P6.5
I/O
P6.6
I/O
P6.7
I/O
RST/NMI
58
Reset input, nonmaskable interrupt input port, or bootstrap loader start (in Flash devices).
TCK
57
Test clock. TCK is the clock input port for device programming test and bootstrap loader start (in Flash
devices).
TDI/TCLK
55
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TDO/TDI
54
I/O
TMS
56
Test mode select. TMS is used as an input port for device programming and test.
DVSS
10
Connect to DVSS
Reserved
DVSS
11
XIN
XOUT
Test data output port. TDO/TDI data output or programming data input terminal
Connect to DVSS
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XT2IN
53
Input port for crystal oscillator XT2. Only standard crystals can be connected.
XT2OUT
52
QFN Pad
NA
NA
10
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in conjunction with seven addressing modes for source
operand and four addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
R4 + R5 > R5
e.g. CALL
PC >(TOS), R8> PC
e.g. JNE
R8
Jump-on-equal bit = 0
S D
SYNTAX
EXAMPLE
OPERATION
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
F F
MOV EDE,TONI
Absolute
F F
MOV &MEM,&TCDAT
R10
> R11
M(2+R5)> M(6+R6)
Indirect
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
Indirect
autoincrement
MOV @Rn+,Rm
MOV @R10+,R11
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
#45
> M(TONI)
D = destination
11
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCOs dc-generator is disabled if DCO not used in active mode
CPU is disabled
MCLK and SMCLK are disabled
DCOs dc-generator remains enabled
ACLK remains active
CPU is disabled
MCLK and SMCLK are disabled
DCOs dc-generator is disabled
ACLK remains active
12
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCOs dc-generator is disabled
Crystal oscillator is stopped
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
Flash memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash memory access violation
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
14
Maskable
0FFFAh
13
TBCCR1 to 6 CCIFGs,
TBIFG (see Notes 1 & 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog timer
WDTIFG
Maskable
0FFF4h
10
USART0 receive
URXIFG0
Maskable
0FFF2h
USART0 transmit
UTXIFG0
Maskable
0FFF0h
Maskable
0FFEEh
Timer_A3
Maskable
0FFECh
Timer_A3
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG (see Notes 1 & 2)
Maskable
0FFEAh
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
Maskable
0FFE8h
Maskable
0FFE6h
0FFE4h
0FFE2h
0FFE0h
0, lowest
USART1 receive
URXIFG1
USART1 transmit
UTXIFG1
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
Maskable
NOTES: 1.
2.
3.
4.
13
Address
0h
UTXIE0
rw-0
URXIE0
rw-0
ACCVIE
NMIIE
rw-0
1
OFIE
rw-0
rw-0
0
WDTIE
rw-0
WDTIE:
OFIE:
Oscillator-fault-interrupt enable
NMIIE:
Nonmaskable-interrupt enable
ACCVIE:
URXIE0:
UTXIE0:
Address
01h
UTXIE1
URXIE1
rw-0
rw-0
URXIE1:
UTXIE1:
Address
02h
UTXIFG0
rw-1
URXIFG0
NMIIFG
rw-0
OFIFG
rw-0
rw-1
WDTIFG
rw-(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC
power up or a reset condition at the RST/NMI pin in reset mode.
OFIFG:
NMIIFG:
URXIFG0:
UTXIFG0:
Address
03h
UTXIFG1
URXIFG1
rw-1
14
rw-0
URXIFG1:
UTXIFG1:
Address
04h
rw-0
6
URXE0
USPIE0
rw-0
URXE0:
UTXE0:
USPIE0:
Address
05h
5
UTXE1
rw-0
4
URXE1
USPIE1
rw-0
URXE1:
UTXE1:
USPIE1:
Legend: rw:
rw-0:
memory organization
MSP430F133
MSP430F135
MSP430F147
MSP430F1471
MSP430F148
MSP430F1481
MSP430F149
MSP430F1491
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
8KB
0FFFFh 0FFE0h
0FFFFh 0E000h
16KB
0FFFFh 0FFE0h
0FFFFh 0C000h
32KB
0FFFFh 0FFE0h
0FFFFh 08000h
48KB
0FFFFh 0FFE0h
0FFFFh 04000h
60KB
0FFFFh 0FFE0h
0FFFFh 01100h
Information memory
Size
Flash
256 Byte
010FFh 01000h
256 Byte
010FFh 01000h
256 Byte
010FFh 01000h
256 Byte
010FFh 01000h
256 Byte
010FFh 01000h
Boot memory
Size
ROM
1KB
0FFFh 0C00h
1KB
0FFFh 0C00h
1KB
0FFFh 0C00h
1KB
0FFFh 0C00h
1KB
0FFFh 0C00h
Size
256 Byte
02FFh 0200h
512 Byte
03FFh 0200h
1KB
05FFh 0200h
2KB
09FFh 0200h
2KB
09FFh 0200h
16-bit
8-bit
8-bit SFR
01FFh 0100h
0FFh 010h
0Fh 00h
01FFh 0100h
0FFh 010h
0Fh 00h
01FFh 0100h
0FFh 010h
0Fh 00h
01FFh 0100h
0FFh 010h
0Fh 00h
01FFh 0100h
0FFh 010h
0Fh 00h
RAM
Peripherals
Data Transmit
13 - P1.1
Data Receive
22 - P2.2
15
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
8 KB
16 KB
32 KB
48 KB
60 KB
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
Segment 1
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
Segment 2
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0E400h
0E3FFh
0C400h
0C3FFh
08400h
083FFh
04400h
043FFh
01400h
013FFh
0E200h
0E1FFh
0C200h
0C1FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
0E000h
010FFh
0C000h
010FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
01000h
01000h
Segment 0
w/ Interrupt Vectors
Main
Memory
Segment n-1
Segment n
Segment A
Information
Memory
Segment B
16
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x1xx Family Users Guide, literature number
SLAU049.
digital I/O
There are six 8-bit I/O ports implementedports P1 through P6:
D
D
D
D
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
USART0
The MSP430x13x and the MSP430x14x(1) have one hardware universal synchronous/asynchronous receive
transmit (USART0) peripheral module that is used for serial data communication. The USART supports
synchronous SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered
transmit and receive channels.
17
comparator_A
The primary function of the comparator_A module is to support precision slope analogtodigital conversions,
batteryvoltage supervision, and monitoring of external analog signals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
12 - P1.0
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
21 - P2.1
TAINCLK
INCLK
13 - P1.1
TA0
CCI0A
22 - P2.2
TA0
CCI0B
DVSS
DVCC
GND
14 - P1.2
15 - P1.3
TA1
VCC
CCI1A
CAOUT (internal)
CCI1B
DVSS
DVCC
GND
TA2
VCC
CCI2A
ACLK (internal)
CCI2B
DVSS
DVCC
GND
Module Block
Timer
NA
13 - P1.1
17 - P1.5
CCR0
TA0
27 - P2.7
14 - P1.2
18 - P1.6
CCR1
TA1
23 - P2.3
ADC12 (internal)
15 - P1.3
19 - P1.7
CCR2
TA2
24 - P2.4
VCC
18
43 - P4.7
TBCLK
TBCLK
Module Block
Timer
NA
ACLK
ACLK
SMCLK
SMCLK
43 - P4.7
TBCLK
INCLK
36 - P4.0
TB0
CCI0A
36 - P4.0
36 - P4.0
TB0
CCI0B
ADC12 (internal)
DVSS
DVCC
GND
37 - P4.1
37 - P4.1
TB1
VCC
CCI1A
TB1
CCI1B
DVSS
DVCC
GND
38 - P4.2
TB2
VCC
CCI2A
38 - P4.2
TB2
CCI2B
DVSS
DVCC
GND
39 - P4.3
39 - P4.3
TB3
VCC
CCI3A
TB3
CCI3B
DVSS
DVCC
GND
40 - P4.4
TB4
VCC
CCI4A
40 - P4.4
TB4
CCI4B
DVSS
DVCC
GND
41 - P4.5
TB5
VCC
CCI5A
41 - P4.5
TB5
CCI5B
DVSS
DVCC
GND
42 - P4.6
TB6
VCC
CCI6A
ACLK (internal)
CCI6B
DVSS
DVCC
GND
CCR0
TB0
37 - P4.1
ADC12 (internal)
CCR1
TB1
38 - P4.2
CCR2
TB2
39 - P4.3
CCR3
TB3
40 - P4.4
CCR4
TB4
41 - P4.5
CCR5
TB5
42 - P4.6
CCR6
TB6
VCC
Timer_B3 implements three capture/compare blocks (CCR0, CCR1 and CCR2 only).
19
WDTCTL
0120h
Timer_B7/
Timer_B3
(see Note 1)
TBIV
011Eh
Timer_B control
TBCTL
0180h
Capture/compare control 0
TBCCTL0
0182h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 3
TBCCTL3
0188h
Capture/compare control 4
TBCCTL4
018Ah
Capture/compare control 5
TBCCTL5
018Ch
Capture/compare control 6
TBCCTL6
018Eh
Timer_B register
TBR
0190h
Capture/compare register 0
TBCCR0
0192h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 2
TBCCR2
0196h
Capture/compare register 3
TBCCR3
0198h
Capture/compare register 4
TBCCR4
019Ah
Capture/compare register 5
TBCCR5
019Ch
Capture/compare register 6
TBCCR6
019Eh
TAIV
012Eh
Timer_A control
TACTL
0160h
Capture/compare control 0
TACCTL0
0162h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 2
TACCTL2
0166h
Timer_A3
Reserved
0168h
Reserved
016Ah
Reserved
016Ch
Reserved
016Eh
Timer_A register
TAR
0170h
Capture/compare register 0
TACCR0
0172h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 2
TACCR2
0176h
Reserved
0178h
Reserved
017Ah
Reserved
017Ch
Reserved
Hardware
Multiplier
(MSP430x14x and
MSP430x14x1
only)
017Eh
Sum extend
SUMEXT
013Eh
RESHI
013Ch
RESLO
013Ah
Second operand
OP2
0138h
MACS
0136h
Multiply+accumulate/operand1
MAC
0134h
Multiply signed/operand1
MPYS
0132h
Multiply unsigned/operand1
MPY
0130h
NOTE 1: Timer_B7 in MSP430x14x(1) family has 7 CCRs, Timer_B3 in MSP430x13x family has 3 CCRs.
20
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
ADC12
Conversion memory 15
(Not implemented in Conversion memory 14
the MSP430x14x1)
Conversion memory 13
ADC12MEM15
015Eh
ADC12MEM14
015Ch
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
Interrupt-vector-word register
ADC12IV
01A8h
Inerrupt-enable register
ADC12IE
01A6h
Inerrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
ADC12MCTL15
08Fh
ADC12MCTL14
08Eh
ADC12MCTL13
08Dh
ADC12MCTL12
08Ch
ADC12MCTL11
08Bh
ADC12MCTL10
08Ah
ADC12MCTL9
089h
ADC12MCTL8
088h
ADC12MCTL7
087h
ADC12MCTL6
086h
ADC12MCTL5
085h
ADC12MCTL4
084h
ADC12MCTL3
083h
ADC12MCTL2
082h
ADC12MCTL1
081h
ADC12MCTL0
080h
21
USART0
Comparator_A
Basic Clock
Port P6
Port P5
Port P4
Port P3
Port P2
22
Transmit buffer
U1TXBUF
07Fh
Receive buffer
U1RXBUF
07Eh
Baud rate
U1BR1
07Dh
Baud rate
U1BR0
07Ch
Modulation control
U1MCTL
07Bh
Receive control
U1RCTL
07Ah
Transmit control
U1TCTL
079h
USART control
U1CTL
078h
Transmit buffer
U0TXBUF
077h
Receive buffer
U0RXBUF
076h
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
CAPD
05Bh
Comparator_A control2
CACTL2
05Ah
Comparator_A control1
CACTL1
059h
BCSCTL2
058h
BCSCTL1
057h
DCOCTL
056h
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
P2IE
02Dh
P2IES
02Ch
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Special Functions
Port P1 selection
P1SEL
026h
P1IE
025h
P1IES
024h
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
ME2
005h
ME1
004h
IFG2
003h
IFG1
002h
IE2
001h
IE1
000h
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to + 4.1 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 150C
Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 85C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
23
MIN
NOM
MAX
UNITS
MSP430F13x,
MSP430F14x(1)
1.8
3.6
MSP430F13x,
MSP430F14x(1)
2.7
3.6
0.0
0.0
40
85
450
8000
kHz
1000
8000
kHz
450
8000
1000
8000
DC
4.15
DC
LF selected, XTS=0
Watch crystal
Ceramic resonator
Crystal
Ceramic resonator
Crystal
VCC = 1.8 V
VCC = 3.6 V
32768
Hz
kHz
MHz
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1M resistor from XOUT to VSS is recommended when VCC <
2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15MHz at VCC 2.2 V. In XT1 mode,
the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8MHz at VCC 2.8 V.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
f (MHz)
8.0 MHz
4.15 MHz
1.8 V
2.7 V 3 V
Supply Voltage V
3.6 V
24
TEST CONDITIONS
NOM
MAX
VCC = 2.2 V
280
350
VCC = 3 V
420
560
VCC = 2.2 V
2.5
20
VCC = 2.2 V
VCC = 3 V
32
45
55
70
VCC = 2.2 V
11
14
VCC = 3 V
17
22
0.8
1.5
0.9
1.5
TA = 85C
TA = 40C
1.6
2.8
1.8
2.2
TA = 25C
TA = 85C
1.6
1.9
2.3
3.9
0.1
0.5
0.1
0.5
0.8
2.5
0.1
0.5
0.1
0.5
0.8
2.5
TA = 40C to 85C
TA = 40C to 85C
I(LPM0)
TA = 40C to 85C
I(LPM2)
TA = 40C to 85C
I(AM)
I(AM)
I(LPM3)
TA = 40C
TA = 25C
I(LPM4)
A
A
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
TA = 85C
TA = 40C
TA = 25C
TA = 85C
UNIT
A
A
VCC = 3 V
TA = 40C
TA = 25C
MIN
VCC = 3 V
A
A
A
A
NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
2. Timer_B is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The current
consumption in LPM2 and LPM3 are measured with ACLK selected.
25
TEST CONDITIONS
VIT+
VIT
Vhys
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
1.1
1.5
1.5
1.9
0.4
0.9
VCC = 3 V
VCC = 2.2 V
0.90
1.3
0.3
1.1
0.5
VCC = 3 V
UNIT
V
V
V
TEST CONDITIONS
VCC = 2.2 V / 3 V
MIN
TYP
VSS
0.8VCC
MAX
VSS+0.6
VCC
UNIT
V
V
t(int)
TEST CONDITIONS
t(cap)
f(TAext)
f(TBext)
VCC
2.2 V/3 V
MIN
TYP
MAX
1.5
2.2 V
62
3V
50
2.2 V
62
3V
50
UNIT
cycle
ns
ns
2.2 V
3V
10
MHz
f(TAint)
2.2 V
8
Timer_A, Timer_B clock
SMCLK or ACLK signal selected
MHz
frequency
f(TBint)
3V
10
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. Seven capture/compare registers in x14x(1) and three capture/compare registers in x13x.
Leakage
current (see
Note 1)
TEST CONDITIONS
Port P1
MIN
TYP
MAX
26
UNIT
50
nA
VOH
VOL
TEST CONDITIONS
MIN
IOH(max) = 1 mA,
IOH(max) = 6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOH(max) = 1 mA,
IOH(max) = 6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
VCC = 3 V,
VCC = 3 V,
See Note 1
See Note 2
See Note 2
TYP
MAX
VCC0.25
VCC0.6
VCC
VCC
VCC0.25
VCC0.6
VCC
VCC
VSS
VSS
VSS+0.25
VSS+0.6
VSS
VSS
VSS+0.25
VSS+0.6
See Note 2
See Note 2
UNIT
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 6 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed 24 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
fTAx
fACLK,
fMCLK,
fSMCLK
TEST CONDITIONS
TA0..2, TB0TB6,
Internal clock source, SMCLK signal
applied (see Note 1)
CL = 20 pF
TYP
DC
MAX
UNIT
fSystem
MHz
CL = 20 pF
fSystem
P2.0/ACLK
CL = 20 pF,
VCC = 2.2 V / 3 V
tXdc
MIN
40%
60%
30%
70%
50%
40%
60%
35%
65%
fSMCLK = fLFXT1/n
50%
15 ns
50%
50%
15 ns
fSMCLK = fDCOCLK
50%
15 ns
50%
50%
15 ns
NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK
frequencies can be different.
27
TA = 25C
VCC = 2.2 V
P2.7
14
12
16
TA = 85C
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.7
20
TA = 85C
15
10
0
0.0
2.5
TA = 25C
0.5
1.0
Figure 2
2.5
3.0
3.5
VCC = 2.2 V
P2.7
I OH High-Level Output Current mA
2.0
Figure 3
1.5
4
6
8
10
TA = 85C
12
VCC = 3 V
P2.7
5
10
15
20
TA = 85C
25
TA = 25C
TA = 25C
14
0.0
0.5
1.0
1.5
2.0
2.5
30
0.0
1.0
1.5
Figure 5
2.0
2.5
3.0
Figure 4
28
0.5
3.5
TEST CONDITIONS
MIN
TYP
f = 1 MHz
t(LPM3)
f = 2 MHz
Delay time
MAX
UNIT
6
6
f = 3 MHz
RAM
PARAMETER
TEST CONDITIONS
VRAMh
MIN
TYP
MAX
1.6
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
TEST CONDITIONS
TYP
MAX
VCC = 2.2 V
VCC = 3 V
MIN
25
40
45
60
I(DD)
VCC = 2.2 V
30
50
I(Refladder/Refdiode)
VCC = 3 V
45
71
CAON =1
0.23
0.24
0.25
0.47
0.48
0.5
VCC = 2.2 V
390
480
540
VCC = 3 V
400
490
550
V(IC)
V(Ref025)
V(Ref050)
Common-mode input
voltage
Voltage @ 0.25 V
V
node
CC
Voltage @ 0.5V
V
CC
CC
CC
node
VCC1
UNIT
A
A
V
V(RefVT)
(see Figure 6)
V(offset)
Vhys
Offset voltage
See Note 2
30
mV
CAON=1
30
Input hysteresis
0.7
1.4
mV
TA = 25
25C,
C, Overdrive 10 mV,
Without filter: CAF=0
VCC = 2.2 V
VCC = 3 V
130
210
300
80
150
240
TA = 25
25C,
C, Overdrive 10 mV,
With filter: CAF=1
VCC = 2.2 V
VCC = 3 V
1.4
1.9
3.4
0.9
1.5
2.6
25C,
TA = 25
C, Overdrive 10 mV,
Without filter: CAF=0
VCC = 2.2 V
VCC = 3 V
130
210
300
80
150
240
TA = 25
25C,
C, Overdrive 10 mV,
With filter: CAF=1
VCC = 2.2 V
VCC = 3 V
1.4
1.9
3.4
0.9
1.5
2.6
t(response LH)
t(response HL)
mV
ns
s
ns
s
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
29
650
VCC = 2.2 V
V(REFVT) Reference Volts mV
VCC = 3 V
600
Typical
550
500
450
400
45
25
15
35
55
75
600
Typical
550
500
450
400
45
95
25
15
35
55
TA Free-Air Temperature C
0 V VCC
1
CAF
CAON
V+
V
+
_
To Internal
Modules
CAOUT
Set CAIFG
Flag
2.0 s
VCAOUT
Overdrive
V
400 mV
V+
t(response)
30
95
75
TA Free-Air Temperature C
TEST CONDITIONS
t(POR_Delay)
VPOR
TA = 40C
TA = 25C
V(min)
MIN
TA = 85C
TYP
MAX
UNIT
150
250
1.4
1.8
1.1
1.5
0.8
1.2
0.2
t(reset)
RST/NMI low time for PUC/POR
Reset is accepted internally
2
s
NOTES: 1. VCC rise time dV/dt 1V/ms.
2. When driving VCC low in order to generate a POR condition, VCC should be driven to 200mV or lower with a dV/dt equal to or less
than 1V/ms. The corresponding rising VCC must also meet the dV/dt requirement equal to or greater than +1V/ms.
V
VCC
POR
No POR
POR
V
(min)
POR
1.8
1.5
V POR V
1.6
1.4
1.2
1.4
1.2
1
1.2
0.8
0.8
0.6
0.4
25C
0.2
0
40
20
20
40
60
80
TA Temperature C
31
TEST CONDITIONS
MIN
MAX
UNIT
VCC = 2.2 V
VCC = 3 V
0.08
0.12
0.15
0.08
0.13
0.16
VCC = 2.2 V
VCC = 3 V
0.14
0.19
0.23
0.14
0.18
0.22
VCC = 2.2 V
VCC = 3 V
0.22
0.30
0.36
0.22
0.28
0.34
VCC = 2.2 V
VCC = 3 V
0.37
0.49
0.59
0.37
0.47
0.56
VCC = 2.2 V
VCC = 3 V
0.61
0.77
0.93
0.61
0.75
0.90
VCC = 2.2 V
VCC = 3 V
1.2
1.5
1.3
1.5
VCC = 2.2 V
VCC = 3 V
NOM
1.6
1.9
2.2
1.69
2.0
2.29
2.4
2.9
3.4
2.7
3.2
3.65
fDCO40
1.7
fDCO40
2.1
fDCO40
2.5
VCC = 2.2 V
VCC = 3 V
f(DCO47)
f(DCO77)
VCC = 2.2 V
VCC = 3 V
S(Rsel)
S(DCO)
SR = fRsel+1 / fRsel
SDCO = fDCO+1 / fDCO
Dt
VCC = 2.2 V
VCC = 3 V
DV
4.5
4.9
4.4
4.9
5.4
1.35
1.65
1.07
1.12
1.16
0.31
0.36
0.40
0.33
0.38
0.43
10
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%/C
%/V
Frequency Variance
NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f(System).
2. This parameter is not production tested.
Max
f DCO_7
Min
Max
f DCO_0
Min
1
f DCOCLK
2.2
VCC V
32
DCO
TEST CONDITIONS
VCC
2.2 V
MIN
NOM
MAX
1.815%
3V
UNIT
MHz
1.9515%
MHz
0.1
%/C
10
%/V
2.2 V/3 V
CXIN
CXOUT
VIL
VIH
TEST CONDITIONS
MIN
NOM
UNIT
12
pF
2
12
pF
MAX
2
VSS
0.8 VCC
0.2 VCC
VCC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
Input capacitance
CXT2OUT
Output capacitance
VIL
VIH
TEST CONDITIONS
MIN
NOM
MAX
pF
VSS
0.8 VCC
UNIT
pF
0.2 VCC
VCC
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
TEST CONDITIONS
VCC = 2.2 V
VCC = 3 V
MIN
NOM
MAX
200
430
800
150
280
500
UNIT
ns
NOTE 1: The signal applied to the USART0/1 receive signal/terminal (URXD0/1) should meet the timing requirements of t() to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0/1 line.
33
TEST CONDITIONS
MIN
AVCC
V(P6.x/Ax)
IADC12
IREF+
CI
Input capacitance
NOM
MAX
UNIT
2.2
3.6
VAVCC
2.2 V
0.65
1.3
3V
0.8
1.6
3V
0.5
0.8
2.2 V
0.5
0.8
3V
0.5
0.8
mA
mA
mA
2.2 V
40
pF
RI
Input MUX ON resistance 0V VAx VAVCC
3V
2000
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VeREF+
Positive external
reference voltage input
1.4
VAVCC
VREF /VeREF
Negative external
reference voltage input
1.2
(VeREF+
VREF/VeREF)
Differential external
reference voltage input
1.4
VAVCC
IVeREF+
IVREF/VeREF
0V VeREF+ VAVCC
2.2 V/3 V
34
VREF+
AVCC(min)
IVREF+
Load-current regulation
VREF+ terminal
IL(VREF)+
TEST CONDITIONS
REF2_5V = 1 for 2.5 V
IVREF+ IVREF+max
3V
2.2 V/3 V
MIN
NOM
MAX
2.4
2.5
2.6
1.44
1.5
1.56
UNIT
2.2
VREF+ + 0.15
VREF+ + 0.15
2.2 V
0.01
0.5
mA
3V
2.2 V
3V
3V
LSB
20
ns
IDL(VREF) +
3V
CVREF+
REFON =1,
0 mA IVREF+ IVREF+max
2.2 V/3 V
TREF+
Temperature coefficient of
built-in reference
2.2 V/3 V
tREFON
LSB
10
100
ppm/C
17
ms
10 F
1 F
0
1 ms
10 ms
100 ms
tREFON
Figure 13. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
35
DVCC
From
Power
Supply
10 F
DVSS
100 nF
AVCC
10 F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
AVSS
10 F
VREF+ or VeREF+
100 nF
VREF/VeREF
10 F
MSP430F14x
100 nF
Apply
External
Reference
MSP430F13x
100 nF
Figure 14. Supply Voltage and Reference Voltage Design VREF/VeREF External Supply
From
Power
Supply
DVCC
+
10 F
DVSS
100 nF
AVCC
10 F
AVSS
MSP430F14x
100 nF
VREF+ or VeREF+
10 F
MSP430F13x
100 nF
Reference Is Internally
Switched to AVSS
VREF/VeREF
Figure 15. Supply Voltage and Reference Voltage Design VREF/VeREF = AVSS, Internally Connected
36
TEST CONDITIONS
fADC12CLK
fADC12OSC
Internal ADC12
oscillator
MIN
NOM
5
MAX
UNIT
6.3
MHz
2.2V/
3V
0.45
ADC12DIV=0,
fADC12CLK=fADC12OSC
2.2 V/
3V
3.7
6.3
MHz
2.2 V/
3V
2.06
3.51
tCONVERT
Conversion time
tADC12ON
(see Note 1)
tSample
Sampling time
RS = 400 , RI = 1000 ,
CI = 30 pF
= [RS + RI] x CI;(see Note 2)
13ADC12DIV
1/fADC12CLK
s
100
3V
1220
2.2 V
1400
ns
ns
ED
Differential linearity
error
EO
Offset error
EG
Gain error
ET
Total unadjusted
error
TEST CONDITIONS
1.4 V (VeREF+ VREF/VeREF) min 1.6 V
1.6 V < (VeREF+ VREF/VeREF) min [V(AVCC)]
(VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF),
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
(VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF),
Internal impedance of source RS < 100 ,
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
(VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF),
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
(VeREF+ VREF/VeREF)min (VeREF+ VREF/VeREF),
CVREF+ = 10 F (tantalum) and 100 nF (ceramic)
MIN
NOM
MAX
2
UNIT
2.2 V/3 V
1.7
LSB
2.2 V/3 V
LSB
2.2 V/3 V
LSB
2.2 V/3 V
1.1
LSB
2.2 V/3 V
LSB
37
TEST CONDITIONS
MIN
NOM
MAX
2.2 V
40
120
3V
60
160
VSENSOR
2.2 V
986
9865%
3V
986
9865%
TCSENSOR
2.2 V
3.55
3.553%
3V
3.55
3.553%
ISENSOR
2.2 V
30
3V
30
tSENSOR(sample)
IVMID
1.1
1.10.04
2.2 V
VMID
3V
1.5
1.500.04
tVMID(sample)
2.2 V
1400
3V
1220
UNIT
A
A
mV
mV/C
ss
2.2 V
NA
3V
NA
A
A
V
ns
38
PARAMETER
VCC(PGM/
ERASE)
VCC
MIN
NOM
MAX
UNIT
2.7
3.6
fFTG
IPGM
257
476
kHz
2.7 V/ 3.6 V
mA
IERASE
tCPT
2.7 V/ 3.6 V
mA
see Note 1
2.7 V/ 3.6 V
ms
tCMErase
see Note 2
2.7 V/ 3.6 V
Program/Erase endurance
TJ = 25C
200
104
ms
105
tRetention
tWord
tBlock, 0
tBlock, 1-63
tBlock, End
tMass Erase
tSeg Erase
5297
4819
cycles
100
years
35
30
21
see Note 3
tFTG
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/fFTG,max = 5297x1/476kHz). To
achieve the required cumulative mass erase time the Flash Controllers mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controllers state machine (tFTG = 1/fFTG).
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
see Note 1
RInternal
see Note 2
VCC
MIN
2.2 V
NOM
MAX
UNIT
MHz
3V
10
MHz
2.2 V/ 3 V
25
60
90
MIN
NOM
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
PARAMETER
VCC(FB)
VFB
IFB
tFB
TA = 25C
VCC
2.5
6
UNIT
V
100
mA
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
39
APPLICATION INFORMATION
input/output schematic
port P1, P1.0 to P1.7, input/output with Schmitt-trigger
P1SEL.x
0
P1DIR.x
Direction Control
From Module
1
Pad Logic
P1.0/TACLK ..
P1OUT.x
Module X OUT
1
P1.7/TA2
P1IN.x
EN
Module X IN
P1IRQ.x
P1IE.x
Q
P1IFG.x
EN
Set
Interrupt
Flag
Interrupt
Edge
Select
P1IES.x
P1SEL.x
PnSel.x
PnDIR.x
Dir. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.0
P1DIR.0
P1DIR.0
P1OUT.0
DVSS
P1IN.0
P1IE.0
P1IFG.0
P1IES.0
P1IN.1
TACLK
CCI0A
P1IE.1
P1IFG.1
P1IES.1
P1IE.2
P1IFG.2
P1IES.2
P1Sel.1
P1DIR.1
P1DIR.1
P1OUT.1
P1Sel.2
P1DIR.2
P1DIR.2
P1OUT.2
Out0 signal
Out1 signal
P1Sel.3
P1DIR.3
P1DIR.3
P1OUT.3
Out2 signal
P1IN.3
CCI1A
CCI2A
P1IE.3
P1IFG.3
P1IES.3
P1Sel.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
P1IN.4
unused
P1IE.4
P1IFG.4
P1IES.4
P1Sel.5
P1DIR.5
P1DIR.5
P1OUT.5
P1IN.5
unused
P1IE.5
P1IFG.5
P1IES.5
P1Sel.6
P1DIR.6
P1DIR.6
P1OUT.6
Out0 signal
Out1 signal
P1IN.6
unused
P1IE.6
P1IFG.6
P1IES.6
P1Sel.7
P1DIR.7
P1DIR.7
P1OUT.7
Out2 signal
P1IN.7
unused
P1IE.7
P1IFG.7
P1IES.7
P1IN.2
40
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger
P2SEL.x
0
P2DIR.x
Direction Control
From Module
0: Input
1: Output
1
0
P2OUT.x
Module X OUT
P2.0/ACLK
P2.1/TAINCLK
P2.2/CAOUT/TA0
Pad Logic
P2.6/ADC12CLK
P2.7/TA0
P2IN.x
EN
Module X IN
P2IRQ.x
Bus Keeper
D
P2IE.x
P2IFG.x
Set
Interrupt
Flag
CAPD.X
Interrupt
Edge
Select
EN
Q
P2IES.x
P2SEL.x
PnSel.x
PnDIR.x
Dir. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
ACLK
P2IN.0
P2IE.0
P2IFG.0
P2IES.0
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
P2IN.1
P2IE.1
P2IFG.1
P2IES.1
P2Sel.2
P2DIR.2
P2DIR.2
P2OUT.2
DVSS
CAOUT
unused
INCLK
P2IN.2
CCI0B
P2IE.2
P2IFG.2
P2IES.2
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
ADC12CLK
Out0 signal
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
P2Sel.7
P2DIR.7
P2DIR.7
P2OUT.7
Signal from Comparator_A
Signal to Timer_A
Signal from Timer_A
ADC12CLK signal is output of the 12-bit ADC module
41
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3
0: Input
1: Output
P2DIR.3
Direction Control
From Module
Pad Logic
P2.3/CA0/TA1
P2OUT.3
Module X OUT
P2IN.3
EN
Module X IN
Bus Keeper
P2IRQ.3
P2IE.3
P2IFG.3
EN
Set
Interrupt
Flag
Interrupt
Edge
Select
CAPD.3
Comparator_A
CAEX
P2CA
P2IES.3
P2SEL.3
CAREF
CAF
+
CCI1B
To Timer_A3
P2SEL.4
P2IES.4
Interrupt
Flag
P2IFG.4
P2IRQ.4
Set
EN
P2IE.4
CAREF
Reference Block
Edge
Select
Interrupt
CAPD.4
Module X IN
Bus Keeper
EN
P2IN.4
Module X OUT
P2OUT.4
From Module
Direction Control
P2DIR.4
1
0
1
P2.4/CA1/TA2
Pad Logic
1: Output
0: Input
P2SEL.4
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.3
P2DIR.3
P2DIR.3
P2OUT.3
P2IN.3
unused
P2IE.3
P2IFG.3
P2IES.3
P2Sel.4
P2DIR.4
Signal from Timer_A
P2DIR.4
P2OUT.4
Out1 signal
Out2 signal
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
42
APPLICATION INFORMATION
input/output schematic (continued)
port P2, P2.5, input/output with Schmitt-trigger and Rosc function for the basic clock module
0: Input
1: Output
P2SEL.5
0
P2DIR.5
Direction Control
From Module
Pad Logic
1
P2.5/Rosc
P2OUT.5
Module X OUT
Bus Keeper
P2IN.5
EN
Module X IN
P2IRQ.5
D
P2IE.5
Q
P2IFG.5
EN
Set
Interrupt
Flag
VCC
Edge
Select
Interrupt
Internal to
Basic Clock
Module
0
to
P2IES.5
P2SEL.5
DCOR
DC Generator
CAPD.5
DCOR: Control Bit From Basic Clock Module
If it Is Set, P2.5 Is Disconnected From P2.5 Pad
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.5
P2DIR.5
P2DIR.5
P2OUT.5
DVSS
P2IN.5
unused
P2IE.5
P2IFG.5
P2IES.5
43
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger
P3SEL.x
0: Input
1: Output
P3DIR.x
Direction Control
From Module
1
Pad Logic
P3OUT.x
Module X OUT
P3.0/STE0
P3.4/UTXD0
P3.5/URXD0
P3.6/UTXD1
P3.7/URXD1
P3IN.x
EN
D
Module X IN
PnSel.x
PnDIR.x
P3Sel.0
P3DIR.0
P3Sel.4
P3DIR.4
P3Sel.5
P3DIR.5
P3Sel.6
P3DIR.6
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
DVSS
DVCC
P3OUT.0
DVSS
UTXD0
P3IN.0
STE0
P3IN.4
DVSS
DVCC
P3OUT.5
DVSS
UTXD1
P3IN.5
Unused
URXD0
DVSS
P3IN.7
P3OUT.4
P3OUT.6
P3Sel.7
P3DIR.7
DVSS
P3OUT.7
Output from USART0 module
Output from USART1 module in x14x(1) configuration, DVSS in x13x configuration
Input to USART0 module
Input to USART1 module in x14x(1) configuration, unused in x13x configuration
44
P3IN.6
Unused
URXD1
APPLICATION INFORMATION
input/output schematic (continued)
port P3, P3.1, input/output with Schmitt-trigger
P3SEL.1
SYNC
MM
STC
STE
P3DIR.1
0: Input
1: Output
DCM_SIMO
Pad Logic
P3.1/SIMO0
P3OUT1
(SI)MO0
From USART0
P3IN.1
EN
SI(MO)0
To USART0
P3DIR.2
0: Input
1: Output
DCM_SOMI
Pad Logic
P3.2/SOMI0
P3OUT.2
SO(MI)0
From USART0
P3IN.2
EN
(SO)MI0
To USART0
45
APPLICATION INFORMATION
input/output schematic (continued)
P3DIR.3
0: Input
1: Output
DCM_UCLK
Pad Logic
P3.3/UCLK0
P3OUT.3
UCLK.0
From USART0
P3IN.3
EN
UCLK0
D
To USART0
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always
an input.
SPI, slave mode:
The clock applied to UCLK0 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).
46
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.0 to P4.6, input/output with Schmitt-trigger
P4SEL.x
0
P4DIR.x
Direction Control
From Module
Module X IN
0: Input
1: Output
1
w
Pad Logic
P5SEL.7
P4OUT.x
Module X OUT
P4.0/TB0 ..
P4.6/TB6
TBOUTHiZ
Bus Keeper
P4IN.x
EN
Module X IN
PnSel.x
PnDIR.x
DIRECTION
CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P4Sel.0
P4DIR.0
P4DIR.0
P4OUT.0
P4DIR.1
P4DIR.1
P4OUT.1
Out0 signal
Out1 signal
P4IN.0
P4Sel.1
P4IN.1
CCI0A / CCI0B
CCI1A / CCI1B
P4Sel.2
P4DIR.2
P4DIR.2
P4OUT.2
Out2 signal
P4IN.2
CCI2A / CCI2B
P4Sel.3
P4DIR.3
P4DIR.3
P4OUT.3
P4DIR.4
P4DIR.4
P4OUT.4
Out3 signal
Out4 signal
P4IN.3
P4Sel.4
CCI3A / CCI3B
CCI4A / CCI4B
P4Sel.5
P4DIR.5
P4DIR.5
P4OUT.5
P4IN.5
P4DIR.6
P4DIR.6
P4OUT.6
Out5 signal
Out6 signal
P4Sel.6
Signal from Timer_B
Signal to Timer_B
From P5.7
P4IN.4
P4IN.6
CCI5A / CCI5B
CCI6A
47
APPLICATION INFORMATION
input/output schematic (continued)
port P4, P4.7, input/output with Schmitt-trigger
P4SEL.7
0: Input
1: Output
P4DIR.7
1
Pad Logic
P4.7/TBCLK
P4OUT.7
DVSS
P4IN.7
EN
Timer_B,
TBCLK
0: Input
1: Output
P5DIR.x
Direction Control
From Module
1
Pad Logic
P5OUT.x
Module X OUT
P5.0/STE1
P5.4/MCLK
P5.5/SMCLK
P5.6/ACLK
P5.7/TBOUTH
P5IN.x
EN
Module X IN
PnDIR.x
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P5Sel.0
P5DIR.0
STE.1
P5OUT.4
DVSS
MCLK
P5IN.0
P5DIR.4
P5IN.4
unused
P5Sel.5
P5DIR.5
DVSS
DVCC
DVCC
P5OUT.0
P5Sel.4
P5OUT.5
SMCLK
P5IN.5
unused
P5Sel.6
P5DIR.6
P5OUT.6
ACLK
P5IN.6
unused
P5Sel.7
P5DIR.7
DVCC
DVSS
P5OUT.7
DVSS
P5IN.7
TBOUTHiZ
NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B7.
48
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger
P5SEL.1
SYNC
MM
P5DIR.1
DCM_SIMO
STC
STE
0: Input
1: Output
Pad Logic
P5.1/SIMO1
P5OUT.1
(SI)MO1
From USART1
P5IN.1
EN
SI(MO)1
To USART1
P5DIR.2
0: Input
1: Output
DCM_SOMI
Pad Logic
P5.2/SOMI1
P5OUT.2
SO(MI)1
From USART1
P5IN.2
EN
(SO)MI1
To USART1
49
APPLICATION INFORMATION
input/output schematic (continued)
port P5, P5.3, input/output with Schmitt-trigger
P5SEL.3
SYNC
MM
STC
STE
P5DIR.3
0: Input
1: Output
DCM_SIMO
Pad Logic
P5.3/UCLK1
P5OUT.3
UCLK1
From USART1
P5IN.3
EN
D
UCLK1
To USART1
NOTE: UART mode:
The UART clock can only be an input. If UART mode and UART function are selected, the P5.3/UCLK1 direction
is always input.
SPI, slave mode:
The clock applied to UCLK1 is used to shift data in and out.
SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P5.3/UCLK1 (in slave mode).
50
APPLICATION INFORMATION
input/output schematic (continued)
port P6, P6.0 to P6.7, input/output with Schmitt-trigger
P6SEL.x
0
P6DIR.x
Direction Control
From Module
0: Input
1: Output
Pad Logic
P6.0 .. P6.7
P6OUT.x
Module X OUT
Bus Keeper
P6IN.x
EN
Module X IN
PnDIR.x
DIR. CONTROL
FROM MODULE
PnOUT.x
MODULE X OUT
PnIN.x
MODULE X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
P6Sel.7
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
NOTE: The signal at pins P6.x/Ax is used by the 12-bit ADC module.
51
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC DVCC
TDI
Fuse
Burn & Test
Fuse
Test
TDI/TCLK
&
Emulation
Module
DVCC
TMS
TMS
DVCC
TCK
TCK
52
APPLICATION INFORMATION
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse is not burned.
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 16). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITDI/TCLK
ITF
53
www.ti.com
10-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
MSP430F133IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F133
MSP430F133IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F133
MSP430F133IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F133
MSP430F133IRTDR
ACTIVE
VQFN
RTD
64
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F133
MSP430F133IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F133
MSP430F135IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F135
REV #
MSP430F135IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F135
REV #
MSP430F135IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F135
REV #
MSP430F135IRTDR
ACTIVE
VQFN
RTD
64
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F135
MSP430F135IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F135
MSP430F1471IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1471
REV #
MSP430F1471IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1471
REV #
MSP430F1471IPMRG
ACTIVE
LQFP
PM
64
TBD
Call TI
Call TI
-40 to 85
MSP430F1471IRTDR
ACTIVE
VQFN
RTD
64
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F1471
MSP430F1471IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F1471
MSP430F147IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F147
REV #
MSP430F147IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F147
REV #
Addendum-Page 1
Samples
www.ti.com
Orderable Device
10-Apr-2015
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
MSP430F147IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F147
REV #
MSP430F147IPMRG4
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F147
REV #
MSP430F147IRTDR
ACTIVE
VQFN
RTD
64
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F147
MSP430F147IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F147
MSP430F1481IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1481
MSP430F1481IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1481
MSP430F1481IRTDR
ACTIVE
VQFN
RTD
64
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F1481
MSP430F1481IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F1481
MSP430F148IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F148
MSP430F148IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F148
REV #
MSP430F148IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F148
REV #
MSP430F148IRTDR
ACTIVE
VQFN
RTD
64
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F148
MSP430F148IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F148
MSP430F1491IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1491
MSP430F1491IPMG4
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1491
MSP430F1491IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1491
MSP430F1491IPMRG4
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F1491
MSP430F1491IRTDR
ACTIVE
VQFN
RTD
64
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F1491
Addendum-Page 2
Samples
www.ti.com
Orderable Device
10-Apr-2015
Status
(1)
Eco Plan
Lead/Ball Finish
(2)
(6)
(3)
Op Temp (C)
Device Marking
(4/5)
MSP430F1491IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F1491
MSP430F149IPAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F149
REV #
MSP430F149IPAGR
ACTIVE
TQFP
PAG
64
1500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
-40 to 85
M430F149
REV #
MSP430F149IPM
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F149
REV #
MSP430F149IPMG4
ACTIVE
LQFP
PM
64
160
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F149
REV #
MSP430F149IPMR
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F149
REV #
MSP430F149IPMRG4
ACTIVE
LQFP
PM
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430F149
REV #
MSP430F149IRTDR
ACTIVE
VQFN
RTD
64
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F149
MSP430F149IRTDT
ACTIVE
VQFN
RTD
64
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
M430F149
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 3
Samples
www.ti.com
(4)
10-Apr-2015
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
19-Mar-2015
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430F133IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F133IRTDR
VQFN
RTD
64
2500
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F133IRTDT
VQFN
RTD
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F135IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F135IRTDR
VQFN
RTD
64
2500
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F135IRTDT
VQFN
RTD
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F1471IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F1471IRTDR
VQFN
RTD
64
2500
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F1471IRTDT
VQFN
RTD
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F147IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F147IRTDR
VQFN
RTD
64
2500
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F147IRTDT
VQFN
RTD
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F1481IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F1481IRTDR
VQFN
RTD
64
2500
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F1481IRTDT
VQFN
RTD
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F148IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F148IRTDR
VQFN
RTD
64
2500
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F148IRTDT
VQFN
RTD
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
19-Mar-2015
Device
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430F1491IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F1491IRTDR
VQFN
RTD
64
2500
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F1491IRTDT
VQFN
RTD
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F149IPAGR
TQFP
PAG
64
1500
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
MSP430F149IPMR
LQFP
PM
64
1000
330.0
24.4
13.0
13.0
2.1
16.0
24.0
Q2
MSP430F149IRTDR
VQFN
RTD
64
2500
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
MSP430F149IRTDT
VQFN
RTD
64
250
180.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F133IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430F133IRTDR
VQFN
RTD
64
2500
367.0
367.0
38.0
MSP430F133IRTDT
VQFN
RTD
64
250
210.0
185.0
35.0
MSP430F135IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430F135IRTDR
VQFN
RTD
64
2500
367.0
367.0
38.0
MSP430F135IRTDT
VQFN
RTD
64
250
210.0
185.0
35.0
MSP430F1471IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430F1471IRTDR
VQFN
RTD
64
2500
367.0
367.0
38.0
MSP430F1471IRTDT
VQFN
RTD
64
250
210.0
185.0
35.0
MSP430F147IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
Pack Materials-Page 2
19-Mar-2015
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430F147IRTDR
VQFN
RTD
64
2500
367.0
367.0
38.0
MSP430F147IRTDT
VQFN
RTD
64
250
210.0
185.0
35.0
MSP430F1481IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430F1481IRTDR
VQFN
RTD
64
2500
367.0
367.0
38.0
MSP430F1481IRTDT
VQFN
RTD
64
250
210.0
185.0
35.0
MSP430F148IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430F148IRTDR
VQFN
RTD
64
2500
367.0
367.0
38.0
MSP430F148IRTDT
VQFN
RTD
64
250
210.0
185.0
35.0
MSP430F1491IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430F1491IRTDR
VQFN
RTD
64
2500
367.0
367.0
38.0
MSP430F1491IRTDT
VQFN
RTD
64
250
210.0
185.0
35.0
MSP430F149IPAGR
TQFP
PAG
64
1500
367.0
367.0
45.0
MSP430F149IPMR
LQFP
PM
64
1000
336.6
336.6
41.3
MSP430F149IRTDR
VQFN
RTD
64
2500
367.0
367.0
38.0
MSP430F149IRTDT
VQFN
RTD
64
250
210.0
185.0
35.0
Pack Materials-Page 3
MECHANICAL DATA
MTQF006A JANUARY 1995 REVISED DECEMBER 1996
PAG (S-PQFP-G64)
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0 7
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
MECHANICAL DATA
MTQF008A JANUARY 1995 REVISED DECEMBER 1996
PM (S-PQFP-G64)
0,50
0,08 M
33
48
49
32
64
17
0,13 NOM
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
0 7
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040152 / C 11/96
NOTES: A.
B.
C.
D.
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