A Multicore Reconfigurable Processor Platform for Energy and

Throughput Aware Applications

Project Proposal for ICT-Related Development and Research Grant

Principal Investigator: Dr.JameelAhmed( Jameel@hitecuni.edu.pk)

Co-Principal Investigator:Dr. Muhammad YasirQadri ( yasirqadri@acm.org)

Introduction:
The saturation of design complexity and clock frequencies for single core processors have
resulted in the emergence of multicore architectures as an alternative design paradigm. In the
recent trends, multicore/multithreaded computing systems are not only a de facto standard for
high-end applications but are gaining popularity in the field of embedded computing. The
advanced level research on multicore architectures requires the development of a high-end test
bed for the exploration of hardware and software. Therefore, we propose an FPGA based
multicore reconfigurable architecture that will support MS and PhD level research and
development in the areas of multicore-processing including core design, memory management,
thread scheduling, application support, inter-processor communication, debugging, power
management, run-time reconfiguration, real-time applications and many more.
The scope of this research project will include the development of an FPGA based reconfigurable
multicore architecture that will support runtime reconfiguration of cache size and associativity,
number of cores and operating frequency. Using the performance counters we will be able to
have a feedback of energy consumption, application throughput and cache miss rate. The project
will also include the development of Fuzzy logic, Neural Nets, Game Programming or similar
Artificial Intelligence (AI) based algorithm to strike a balance between throughput and energy
consumption of work-load (applications).

Figure 1. Automated hardware exploration

Project Summary:
Contemporary processor architectures do not leverage much flexibility for reconfiguration and
have been designed for an overall average performance in terms of throughput and energy
consumption for general applications. Recently, leading academic/research institutions are
focusing on processors with micro-architecture and reconfigurable units such as cache, pipelines
etc. to make them more adaptive and energy efficient as per users workload requirements.
Field Programmable Gate Arrays (FPGAs) have been employed in most of the proposed
reconfigurable architectures as they can allow reconfiguration at runtime. The foremost
advantage of runtime reconfiguration is that it is possible to apply a set of configurations that
would have a combined size larger than the available area on the reconfigurable hardware.
However, reconfigurable platforms such as FPGAs still face a few problems such as seamless
adaptation of Operating Systems that are executing running multiple threads on the hardware
changes, and large reconfiguration latencies which make them inefficient to meet deadlines in a
real-time environment. Partially reconfigurable FPGAs offer an effective resource for fast
reconfiguration making them suitable for real-time tasks.

Figure 2 Multicore Reconfigurable Processor on FPGA

On the other hand, only a few partially reconfigurable devices are available to date and
specialized software is required to support these features. A full reconfiguration model could be
adapted to any FPGAs with large on chip SRAMs but such approach suffers from large
configuration latencies. Therefore, we have proposed a novel run-time hardware adaptation
technique that avoids the greater reconfiguration latency costs and leverages the use of Artificial
Intelligence (AI) based techniques such as Fuzzy Logic, Neural Networks for hardware
adaptation as per application requirements.
In order to build upon the concept of hardware realization of our previously proposed run-time
reconfiguration scheme, we propose a hardware platform based on FPGAs on which a multicore

processor architecture is to be mapped. The proposed platform would have a novel

reconfiguration engine to optimize the adjoining architecture as per energy and throughput needs
of an application. The platform will serve as a base for conducting research on several areas of
multicore architectures such as the development of novel cache coherency protocols, memory
management systems, cache replacement policies, hardware transactional memories, OS support
for fine grained parallelism, Instruction Set Extension, Network on Chip, energy and throughput
analysis, and hardware reconfiguration.
The proposed project comprises the development of an Advanced Computer Architecture
Laboratory at the HITEC University that will include latest Computer Architecture Simulation
Software, high-end FPGA boards, and PCs.