ECEN 454 – Lab 10: Logic Synthesis and Static Timing Analysis

PART A : LOGIC SYNTHESIS

Purpose:

Design Vision is the graphical interface to the Synopsys family of logic synthesis tools. Internally it
runs design compiler. This lab is to familiarize you with the basics of synthesis using Design Vision
through a simple example "alarm clock design". We then use the same method to synthesize the cruise
control logic from the previous lab. After synthesis, you will do pre-layout static timing analysis of
your synthesized design. You will define constraints for your design and check the timing of all the
paths in the design. If you are comfortable, you can jump directly to the cruise control synthesis.

Preparation:

1. Copy the tutorial to your home directory (not your cadence directory created in first lab, just
home directory). "cp –r /jumbo/synopsys/2000.5/doc/syn/tutorial/ .” The db (Synopsys database
format), verilog (Verilog format) and VHDL (VHDL format) directories contain the designs for
the alarm clock in different formats. The work directory is empty at the beginning and will be
used to store intermediate files. The db format is the proprietary format of Synopsys for front
end design. Apart from containing the description of design, it may also contain the information
about constraints.

2. Brief introduction to the “alarm clock design”: This is a simple hierarchical design for a
digital display alarm clock. Below is the structure of the design (TOP).

Fig 1. Hierarchical design of Alarm Clock

3. Starting design analyzer: Open “.cshrc” file (it is hidden by default) in your home directory.
You can use any TXT editor such as vi, emacs, pico and etc.

Add “source /usr/local/bin/setup.synopsys” to “.cshrc” and save it.

Execute “source .cshrc”.
Change to your tutorial directory.

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To start design analyzer, using the command: design_vision &. (If you do not run design vision
from your tutorial directory, remember to copy .synopsys_dc.setup file to the directory where
you start.) For your convenience, please always start design_vision from your tutorial
directory.

You will find that in the xterm window, there is a design_vision prompt. Type the
following command in that prompt.

source .synopsys_dctcl.setup

The command should work if you invoked design_vision from the tutorial directory. To see if
the script sourced properly, type

echo $target_library

It should yield the result “class.db”

Synthesis Procedure:

1. Load a design: Analyze, elaborate and read are commands provided by Design Compiler. They
are available through the File menu in Design Vision.

The analyze command reads a VHDL or Verilog file, checks for proper syntax and
synthesizable logic, and stores the design in an intermediate format. The elaborate command
creates a design from the intermediate format produced by analyze. It replaces the HDL
operators with synthetic operators. Mainly it translates the verilog code to synopsys’ internal
generic library called gtech.

The read command is used to load files in formats other than HDL formats, such as db, pla and
other formats supported by Design Compiler.

As to the alarm clock example, the CONVERTOR sub design is given in pla format and must be
loaded by read. For others, Verilog version designs are given in verilog directory and analyze
and elaborate are used to load the files.

To avoid unresolved references or unnecessary warnings, load the designs following the
“bottom up” style. That’s, started with the lowest level sub designs and work your way up to the
top-level design.

Detailed procedure:

1. Analyze the block level sub designs in Fig 1.

 Select “File > Analyze”. The Analyze File window appears. Change to the verilog
directory.

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 Select the designs ALARM_STATE_MACHINE.v, HOURS_FILTER.v,

TIME_COUNTER.v, TIME_STATE_MACHINE.v ALARM_COUNTER.v using the
left mouse button and ctrl key.

 Click Ok.

2. Elaborate each sub block separately.

 Select “File > Elaborate”. The Elaborate Design window appears. Choose the library work
in the Library list. Ignore the warnings about the symbol library.

 Verify that ReAnalyze OutOfDate Libraries is set to on.

 Select the ALARM_COUNTER in the Design list.

 Click Ok.

 Elaborate the other 4 sub designs individually by repeating the above steps.

3. Read in the CONVERTOR block.

 Select “File > Read”. Change to the verilog directory.

 Select CONVERTOR.pla file.

4. Load the sub designs in next hierarchy level.

ALARM_BLOCK.v, ALARM_SM_2.v, COMPARATOR.v, CONVERTOR_CKT.v,

TIME_BLOCK.v, MUX.v
(There is a small error in MUX.v . line 7 should be reg [10:0] OUTBUS; change it before
analyze)

The six sub designs are all in verilog format. Use Analyze and elaborate.

5. Load the Top level design.

Use Analyze and elaborate to load TOP.v.

6. Save the design and your attribute settings

 Select TOP design in the logical hierarchy window.

 Select “File > Save As”.

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 Change to your tutorial/db/ directory.

 Enter TOP_attributes.ddc in the File Name field to save the file to db directory.

 Check the Save All Designs in Hierarchy option. This is to make sure your netlist (the
term used to describe a structural verilog code) contains the description of all modules
and not just the top module.

Till now, the entire design hierarchy is loaded. Remember to always save your design work
in case the machine crashes.

7. Set attributes for the design

Attributes are values set on a design that control or affect the optimization process. For
example, attributes can specify the operating environment of the design, the constraints for
optimization, as well as many other design parameters.

8. Select TOP design.

 Click the symbol view button (you should find an icon below the menus which should
read “create symbol view” when you move the cursor over it ). The created symbol
should appear on the screen showing inputs and outputs.

9. Set the Drive Strength on Input Ports

The drive strength is used to set a finite transition time for the input signals. Otherwise, the
input signals to the design will be ideal which is unfortunately not realistic.

Use left mouse button to select the each input port in the symbol view. Use the ctrl key to select
all inputs at the same time. Select “Attributes > Operating Environment > Drive Strength”. The
Drive Strength window displays.

 Set the Drive Strength to be that of pin Z of the driver cell B4I in the target library.

 Select “Attributes > Operating Environment > Drive Strength”.

 Choose “Use library cell options”

 Clock on the button across the Library cell name option.

 Choose class on the left side of the new window and B41 from the right side. Click to
choose objects. Press ok. Press ok to close the drive strength window.

By this, we are modeling the input ports to be driven by a buffer B41 which has a finite
drive strength

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10. Set the Load on Output Ports

Load values are used to model the capacitive load on the output ports. SPEAK_OUT drives a
load of five inverters. The load of each inverter is 1.5(load of cell IVA, pin A in the target
library). So the load value for SPEAKER_OUT is calculated as (1.5 * 5=7.5). Loads for DISP1
and DISP2 are 3.

 Select the SPEAKER_OUT port.

 Select “Attributes > Operating Environment > Load”.

 Replace the contents of the capacitive load field with 7.5.

 Click Apply.
 Click Cancel to dismiss the Load window.

Repeat the above steps to set capacitance load value on DISP1 and DISP2 to be 3.
The alternate way is to paste the below two commands

set_load 3 [all_outputs]
set_load [expr [load_of class/IVA/A] * 5] SPEAKER_OUT

11. Set the Wire Load

The wire load model is used to model the post layout effects in pre-layout design. Before
actual placement and routing, there is no information on interconnects. Wire-load models
are a statistical way of modeling wire resistance. The input capacitance and resistance of the
wire load models vary with the size of design based on the assumption that a larger design
will have longer wires. Refer to the design compiler manual for more information.

 Select TOP.

 Select “Attributes > Operating Environment > Wire Load”.

 Select 10x10(class). As defined in the library file, 10x10 corresponds to a die size of
1mm x 1mm.

 Click Ok.

12. Set the Operating Conditions

Operating conditions are the temperature, process and voltage in which the design operates.
The target library defines operating conditions. Library vendors define default operating
conditions, which can differ from one vendor to another.

 Select “Attributes > Operating Environment > Operating Conditions”. The operating

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conditions window appears and lists operating conditions from the target library.

 Select WCCOM (class) in the Operating conditions window. This is the worst-case
commercial operating condition defined in the target library.

 Click Ok.

The operating condition sets the process, voltage and temperature (PVT) corners for analysis
and design. Worst case usually represents the slow corner or worst timing for setup. So, when
you set your operating condition to worst case, you will have the worst delays for all the
standard cells in the design.

13. Save the design and your attribute settings

 Select “File > Save As”.

 Change to your tutorial/db/ directory.

 Enter TOP_attributes.ddc in the File Name field to save the file to db directory.

 Check the Save All Designs in Hierarchy option.

 Click Ok.

14. Set the Optimization Goals

The Optimization goals or constraints include timing, area and power that you set for a design.
Design Compiler checks your optimization goals during optimization and tries to meet them
while synthesizing the design using the technology library.

Set Clock Constraints:

 Select CLK in the symbol view. Click

 “Attributes > Clocks > Specify”. Type 25 in the Period field.

 Type 12.5 next to the rising field and 25 next to the falling field

 Click Apply. You should be able to see the clock waveform

 Click ok to dismiss the Specify Clock window.

The clock object is created on CLK. Note the small waveform symbol attached to the CLK
port.

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Set Delay Constraints. Input/output delays model the external delays arriving/leaving at
the input/output ports of the constrained module. In this Alarm clock design, the input delay
is zero. We need to set the output delay.

 Select the four output ports of TOP.

 Select “Attributes > Operating Environment > Output Delay”.

 Select the clock signal you just created. It should be named CLK_0 or whatever name you
gave for the clock in the previous step.

 Enter 5 in the Max Rise. The Max Fall should copy the same value

 Click Apply.

 Click Cancel to dismiss the Output delay window.

The input and output delays are usually set for each clock domain. Usually, there is a need
for many IOs in large designs and designers sometimes use the same IO for multiple
applications. Hence when you set the IO constraints it is also necessary to specify the clock
domain.

15. Run check_design

Check_design is one of the most important commands for sanity check before synthesis.
Though it doesn’t do anything on the design, it is very important to verify its result before
progressing further.

 Select “Design > Check Design”.

 Click Ok.

Examine the messages.

 The first message shold be : Pin `T0' is connected to logic 0. Pin T0 is selected in the
schematic. Design Analyzer updates the schematic in the Design Analyzer window.

 The next warning should be: In design `CONVERTOR_CKT', the same net is connected to
more than one pin on submodule `U7'. (LINT33). This message and the previous three
warning messages are issued because unconnected input ports are automatically connected
to logic 0 by Design Compiler. Because these warnings do not reflect problems in the
design, you can ignore them. If you're using Verilog, the net name Logic 0 is connected to
T0 and T1.

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 There should also be a Warning: Design `CONVERTOR' is instantiated 2 times. (LINT45).

This message is issued because CONVERTOR is referenced more than once in design
CONVERTOR_CKT. Resolve the multiple instances of CONVERTOR before optimization
using uniquify as explained soon.

 Click Cancel to dismiss the Design Errors window.

Resolve Multiple Design Instances

Hierarchical designs can reference a subdesign more than once. When the same subdesign is
referenced more than once in another design, multiple instances are created. Resolve
multiple design instances before you compile.

 Select TOP design.

 In the design_vision prompt, type uniquify

When you have instantiated a module multiple times, uniquify creates separate or unique
module names for each instance. In this way, the instances are referenced by different
modules though they are functionally equivalent.

 Save the Design and run check_design again, you can see multiple design instances error
disappear.

 Select design TOP.

 Select “File > Save As”.

If you are not in the db directory, change to it. Type TOP_before_compile.db in the File Name
Field.

Verify that Save All Designs in Hierarchy option is set to on. Click OK.

4. Optimize the Design

After setting constraints & attributes on the alarm clock design and running check_design, the
design is ready to be optimized with the compile command. Optimizing is the step in the synthesis
process that attempts to implement a combination of library cells that meets the functional, area and
speed requirements of the design.

Detailed procedure:

 Open the Design Optimization window

 Return to the top level and select design Top.

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 Select “Design->compile design”.

 Check and set options

 Note the default settings. Map Design (mapping) is set to on. Map Effort is set to Medium.
This is the CPU effort used to map a design. For this design, the defaults are sufficient to
meet defined constraints.

 Set Allow Boundary Conditions to on. This enables boundary optimization

Evaluate and Interpret the Design:

Generate reports to determine whether the design goals are met. Using Design vision you can select
and generate any number of attribute and analysis reports, which send output to a report window or
a file you designate.

 Open the report window

 Display the Symbol View of TOP.

1. Generate Analysis Reports

 Choose design-> report constraints

 Select “show all violators” and verbose .
 Choose “To file” and enter a file name to direct the output to.
 The report_constraints command reports all violations of any constraints you have for
your design (timing, transition etc).

To get the area report

 Choose design-> report area.
This gives the cell count and percentage of combinational and sequential area.

2. Save the optimized verilog netlist.

After completion of optimization save the design in the form a verilog netlist. Use “File > Save As”
and choose the Verilog option and save a copy of the “Top” design in the verilog folder as
“Alarm_Clock.v”.

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3. Synthesis of the Cruise Control Logic

Now repeat the same procedure explained above to synthesize the behavioral verilog code that was
written for the Cruise Control Logic of a vehicle in the previous lab session. But in this case we
need to synthesize the logic with a certain specific library for 180nm technology. The synopsys
database format (db) file for a typical 180nm technology is put up on the website. We need to
ensure that the synthesis is performed according to this library file (see below for procedure). What
this means is that the optimization (power, timing, area etc) will be performed according to the
characteristics of the standard cells given in this file.

Note: In the following lab we will use the synthesized verilog netlist that you will generate for the
cruise control logic to “Place and Route” the circuit on a die.

Procedure to link the given library with the synthesis process:

 Download the "iit018_stdcells.db" file from the lab website and save a copy in the ~/tutorial
folder.
 After you begin Design_Analyzer, choose "File->Setup > Defaults". A window pops up.
 Fill in iit018_stdcells.db in "Link Library".
 Fill in iit018_stdcells.db in "Target Library".
 Fill in generic.sdb in the "Symbol Library"
 Click Ok.

The target library is the actual library which the synthesis will use to optimize. The link library
includes the target library and any other libraries for macros you may have in the design.
Now place the verilog behavioral code of the Cruise Control Logic in the ~/tutorial/verilog
folder and repeat the same procedure as above to optimize the logic and generate the
synthesized netlist.

Note:
 While assigning the drive strength for the clock, the above given procedure of using drive_of
(class/B4I/Z) will not work since the target library does not remain the same. Hence use an
absolute value of 0.0335
 Use a load of 3 on the output ports.
 Also you need not set the Wire Load in this case.
 And for operating conditions use the "typical" option provided by the library.
 Use a clock period of 25 and set the output delay to 5 in both the Max Rise and Max Fall fields.
 Make sure you save the synthesized netlist (after performing optimization) of the design in
verilog format. This file will be required for the next section.

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Report Requirements:

1. Print the area and constraints report of the cruise control logic.
2. Print out the final synthesized verilog netlist of the cruise control logic.
3. Report the register count.
4. Why should you uniquify the design? The lab manual explains what the command does. Can
you figure out why you may have to uniquify the design ?
5. What is boundary optimization? Explain with an example.

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PART B : STATIC TIMING ANALYSIS

1. Introduction

Timing analysis is to check the timing requirement of the circuit. You can do timing analysis at
different design stages – pre-layout with wire-load models or post-layout with actual wires.

PrimeTime® (PT) is the static timing analysis (STA) tool from Synopsys. It is the most widely
used STA engine. Though Design compiler has its own timing engine, it cannot come close to
PrimeTime’s accuracy. Moreover, primetime can also consider signal integrity effects like
coupling noise due to cross talk and analysis of complex interconnect structures.

But PT requires a gate level description (netlist) as input. When you do post-layout STA, you
also need to feed parasitic information (which is for the next lab)

2. Using PrimeTime

Environment Setup:

 Make sure you have the iit018_stdcells.db and iit018_stdcells.lib files in the same
folder. If not, download the same from the lab website. The iit018_stdcells.db is the
timing library file in Synopsys format and iit018_stdcells.lib is the same timing library
file in ASCII format. Browse through the iit018_stdcells.lib file and you will find the
timing information of each standard cell in table format. If not specified, PrimeTime
uses these tables to compute gate delays in the circuit. You may modify these tables
according to your own simulation (SPICE), and use "lc_shell" (Library Compiler shell)
to compile the text file to db file.

Circuit:

 Make sure you have the synthesized verilog netlist in the same folder

Read Libraries:

 Type "primetime &" in your terminal, then the primetime console window appears. If
you can't find this command, try to add "source /usr/local/bin/setup.synopsys" into file
".cshrc" at your home directory, then open a new terminal.
 In the console window, click "File - > Search and Link Path". In the pop-up window,
type "." in column "Search Path" and type "* iit018_stdcells.db" (there is a space
between the * and the library name) in column "Link Path", then click "OK". This is to
indicate PrimeTime that the libraries with the specified names are to be found in the
current directory. Please note in primetime console window you will see the
corresponding messages about what you did. Note that if there are message in red color,
it means there are errors in the operation.

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Setup Design:

 Click "File > Open" to read in your circuit design. Please select files of type as "verilog"
then you will see the verilog file, highlight your file and click "OK". Dismiss the pop-up
window. Then click "Design > Current" and choose top module in your design. Click
"OK" then. Next step is to link the design to the running library. You can do this by
clicking "Design > Link" and choose your top module to link.

Set Capacitance for output ports:

 The output ports of your design are to be connected to other blocks. Therefore you need
to set the load capacitance for the outputs. Click "Attributes > Capacitance > Set
Port/Net Capacitance" then the set capacitance window pops up. You can click button
"Browse..." to select output ports and set the max value to be 3.

Set driving strength for input ports:

 You need to provide driving strength to the input ports of your design. You may do it by
clicking "Attributes > Port Drive > Set Driving Cell...” Then use the "Browse" button to
choose the input ports and choose cell "BUFX2" as the driving cell. Then click "Ok".

Set Clock Details:

 To set the time period for the clock choose "Attributes > Clock > Create”. Use Browse
to choose the clock source pin in your design. and set the period of the clock to 10.

 After setting the clock details you intend to perform a check_timing command before
you begin the timing analysis. The check_timing command shows possible timing
constraints related problems for the design. For example, if you have not defined a
clock, some flip flops will not have any clock information. There may then be
unconstrained paths in the design which will not get reported as violating paths. The
chip may fail!

To type in the command use the space at the bottom of the console. You may type in the
command next to the space after "primetime > “. After the command is executed you
will see there are a few warnings that may appear on the console window. The warnings
may say There are * ports with no clock-relative input delay specified and There are *
endpoints which are not constrained for maximum delay. This is because you have not
specified the required arrival time for the signals at the input and output pins relative to
the clock signal.

 To specify the arrival time for the input signals relative to the clock choose "Attributes >
Port Delay > Input". Use Browse again to choose all the input pins and the Maximum
Rise as 4 and Minimum Rise delay as 0 and ensure that the Reference Clock refers to the

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name of the clock symbol in your design.

 To specify the arrival time for the output signals relative to the clock choose "Attributes
> Port Delay > Output". Use Browse to select all the output pins type in 5 for the
Maximum Rise and Minimum Rise times and also ensure that the Reference Clock refers
to the name of the clock symbol in your design.

 Now execute the check_timing command again and you must be able to get a clean
output on the console window.

 Next you check if there is are any setup time violations on any of the cells in the circuit.
You do this by typing in the following command
report_constraint -all_violators -verbose -max_delay

You can redirect it to a file by typing

report_constraint -all_violators -verbose -max_delay > output_file_name

 If you have any violations then you will be able to see the details on the console
window. To report the hold time violations on any of the cells use the following
command
report_constraint -all_violators -verbose -min_delay

 Next, you will learn how to generate path-based timing reports. The report_timing
command with no options reports the longest path in the design. Make a note of the
slack that is displayed on the window after the command is executed. This is the least
possible slack on your design considering only max (setup) paths. Now let us generate
the top three critical paths with respect to the setup time. To do this use the following
command
report_timing -max_paths 3 > max_paths.txt

The results will not appear on the console window but get stored in the file
max_paths.txt

 Similarly, obtain the top three critical min (hold time) paths by using the following
command.
report_timing -max_paths 3 -delay min > min_paths.txt

This will store the three most critical minpaths in the min_paths.txt file.

Report Requirements:

1. Print out the files "max_paths.txt" and "min_paths.txt"

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