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Prepared by: Garth Nash
Applications Engineering
ABSTRACT
The fundamental design concepts for phase-locked loops
implemented with integrated circuits are outlined. The
necessary equations required to evaluate the basic loop
performance are given in conjunction with a brief design
example.
e(s)
INTRODUCTION
H(s)
i(s)
e(s)
o(s)
G(s)
H(s)
Phase Input
Phase Error
Output Phase
Product of the Individual Feed
Forward Transfer Functions
Product of the Individual Feedback
Transfer Functions
PARAMETER DEFINITION
The Laplace Transform permits the representation of the
time response f(t) of a system in the complex domain F(s).
This response is twofold in nature in that it contains both
transient and steady state solutions. Thus, all operating
conditions are considered and evaluated. The Laplace
transform is valid only for positive real time linear parameters;
thus, its use must be justified for the PLL which includes both
linear and nonlinear functions. This justification is presented
in Chapter Three of Phase Lock Techniques by Gardner.1
i(s)
fi
1
(s)
e(s)
1 G(s) H(s) i
(1)
G(s)
o(s)
(s)
1 G(s) H(s) i
(2)
e(s)
Phase Detector
fo
N
o(s)
Filter
o(s)/N
VCO/VCM
Programmable
Counter (N)
REV 0
o(s)
G(s)
fo
(3)
10
s(s 10)
(4)
This is a type one system since there is only one pole at the
origin.
The order of a system refers to the highest degree of the
polynomial expression
1 + G(s) H(s) = 0
( 10 )
Where
TYPE ORDER
let
ERROR CONSTANTS
C.E.
(5)
10
s(s 10)
(6)
10
0
s(s 10)
(7)
therefore
C.E. = s(s +10) +10
C.E. = s2 + 10s + 10
(8)
(9)
( 11 )
( 12 )
C
Or, in Laplace notation: i(s) sp
( 13 )
where Cp is the magnitude of the phase step in radians. This
corresponds to shifting the phase of the incoming reference
signal by Cp radians:
Step velocity: i(t) = Cvt t 0
( 14 )
then
1 G(s) H(s) 1
1
e(s)
(s)
1 G(s) H(s) i
2 Ca
s3
( 16 )
( 17 )
G(s) H(s)
K
s(s a)
( 18 )
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G(s) H(s)
K(s a)
s2
( 19 )
Type 3
G(s) H(s)
K(s a)(s b)
s3
( 20 )
The final value of the phase error for a type 1 system with a
step phase input is found by using Equations 11 and 13.
e(s)
1
K
1 s(sa)
Cp
s
(s a)Cp
(s2 as K)
( 21 )
sa
e(t ) Lim s
Cp 0
2 as K
s
so
( 22 )
(2n 1)
; n 0, 1, 2, ...
#P #Z
( 23 )
Type 2
Type 3
Step Position
Zero
Zero
Zero
Step Velocity
Constant
Zero
Zero
Step
Acceleration
Continually
Increasing
Constant
Zero
( 25 )
K
s(s 4)
( 26 )
STABILITY
The root locus technique of determining the position of
system poles and zeroes in the s-plane is often used to
graphically visualize the system stability. The graph or plot
( 24 )
2n 1
2
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for n 0
2
3 for n 1
2
( 27 )
( 4 0) (0)
20
( 28 )
s 2
The breakaway point, as defined by Rule 6, can be found by
first writing the characteristic equation.
( 29 )
K = s2 4s
( 30 )
9 =!"% ,"('#('%&#"!&
1
dK d ( s2 4s)
ds
ds
( 31 )
dK 2s 4 0
ds
( 32 )
or
s = 2
( 33 )
s2 + 2ns + 2n
8=
&+ #'"'
8
!'% " %)'+
( 34 )
Assume
%*+ #"!'
= 0.5
error < 10%
for t > 1ms
From = 0.5 curve error is less than 10% of final value for all
time greater than nt = 4.5. The required n can then be found
by:
nt = 4.5
&+ #'"'
( 35 )
or
( 36 )
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Example:
(s a)k
s2
( 37 )
-
<B:6-80
-
4
38.
9 =!"% ,"('#('%$(!+
G(s) H(s)
8=
BANDWIDTH
Output Frequency
2.0MHz to 3.0MHz
Frequency Steps
100KHz
1ms
Overshoot
<20%
( 39 )
MC4044/4344
MC4024/4324
Programmable Counter
MC4016/4316
G(s) = Kp Kf Ko
where
Kn = 1/N
H(s) = Kn
( 40 )
( 41 )
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Phase Detector
Kp
fi
Filter
Kf
VCM
Ko
fo
Programmable
Counter Kn
f min
f min
N min o
o
2MHz 20
100KHz
fi
fstep
( 42 )
f max
3MHz 30
N max o
100KHz
fstep
( 43 )
Kn 1 to 1
20
30
( 44 )
)
)/.
A
A
A
Ko 11.2sx10
radsV
( 47 )
Kp Kv K n Kf
s
K(s a)
s2
( 49 )
a
Kf s
s
( 50 )
in order to provide all of the necessary poles and zeroes for the
required G(s) H(s). The circuit shown in Figure 9 yields the
desired results.
K
Ko sv
%
B
( 46 )
Thus
G(s)H(s)
A
) 38 !#(')"')"'&
( 45 )
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0.5 Kp Kv
R Cs 1
for largeA
Kf 2
R1Cs
R1CN
( 51 )
and
R1, R2, and C are then the variables used to establish the
overall loop characteristics.
R2RCs1Cs 1
n2
0.5 Kp Kv R2
R1N
( 57 )
2n
( 58 )
With the use of an active filter whose open loop gain (A) is
large (Kc = 1), Equations 57 and 58 become
Kp Kv
R1CN
n2
Kp Kv R 2
R1N
( 59 )
2n
( 60 )
( 52 )
n 4.5 4.5 4.5krads
t
0.001
( 61 )
Rewriting Equation 57
R1C
( 53 )
R2RCs1Cs 1
Ksv
N1
0.5 Kp Kv
n2N
( 62 )
( 54 )
0.5 Kp Kv R2
R1N
s
0.5 Kp Kv
R1CN
R1C = 0.00102
( 55 )
0.5 Kp Kv R2
R1N
s
C = 0.5F
Then
R1 0.00102 2.04k
0.5 x 10-6
Use
R1 = 2k
0.5 Kp Kv
R1CN
= s2 + 2ns + n2
( 56 )
i(s)
+
Kp = 0.111V/rad
R Cs 1
Kf 2
2R1Cs
6
Ko 11.2
s * 10 radsV
o(s)
Kn 1 to 1
30
20
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)
)
5
13
%
%
5
:
%
5
#&
19
089=0< :-;=< 0?=0;8-6 =9 =20
( 63 )
N = 20
n = 5.64krad/s
= 0.961
N = 30
n = 4.61krad/s
= 0.785
2(0.8)
(0.5 x 10-6)(4.5k)
5
= 711
Use R2 = 680
All circuit parameters have now been determined and the
PLL can be properly configured.
Since the loop gain is a function of the divide ratio Kn, the
closed loop poles will vary its position as Kn varies. The root
locus shown in Figure 12 illustrates the closed loop pole
variation.
The loop was designed for the programmable counter
N = 30. The system response for N = 20 exhibits a wider
bandwidth and larger damping factor, thus reducing both
lock-up time and percent overshoot (see Figure 14).
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EXPERIMENTAL RESULTS
)
!&'##%" '"
)
)
!&'##%" '"
)
)
) .7
7< .7
!
"('#('%$(!+ @
SUMMARY
! &'## %" '"
&=0: 8:>=
! &'## %" '"
!
' 7<
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P2 = 0.111
V2 = 1.12 E+7
R3 = 3900 (R1C = 2k)
R4 = 680
C2 = 0.5
N3-N4 = 21 20
F2 (F6) = 100000 (100000)
PLOT OF FUNCTIONS
(NOTE: Y(T) IS +, Z(T) IS *, AND IS COMMON)
FOR T:
FOR FCTS:
TOP = 0
LEFT = 0
BOTTOM = 0.0015
RIGHT = 0.12
INCREMENT = 0.0005
INCREMENT = 0.002
10
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Bibliography
1. Topic: Type Two System Analysis
Gardner, F. M., Phase Lock Techniques, Wiley, New York, Second Edition, 1967
2. Topic: Root Locus Techniques
Kuo, B. C., Automatic Control Systems, Prentice-Hall, Inc., New Jersey, 1962
3. Topic: Laplace Techniques
McCollum, P. and Brown, B., Laplace Transform Tables and Theorems, Holt, New York, 1965
4. Topic: Type One System Analysis
Truxal, J. G., Automatic Feedback Control System Synthesis, McGraw-Hill, New York, 1955
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AN535/D
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