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Z80A-CPU
Product Specification
MARCH 1978
The Zilog Z80 product line is a complete set of microcomputer components, development systems and support
software. The Z80 microcomputer component set includes
all of the circuits necessary to build high-performance
microcomputer systems ,with virtually no other logic and a
minimum number of low cost standard memory elements.
The two 16-bit index registers allow tabular data manipulation and easy implementation of relocatable code. The
Refresh register provides for automatic, totally transpare'nt
refresh of external dynamic memories. The I register is used
in a powerful interrupt response mode to form the upper 8
bits of a pointer to a interrupt service address table, while
the interrupting device supplies the lower 8 bits of the
pointer. An indirect call is then made to this service address.
The Z80 and Z80A CPU's are third generation single chip
microprocessors with unrivaled computational power. This
increased computational power results in higher system
through-put and more efficient memory utilization when
compared to second generation microprocessors. In
addition, the Z80 and Z80A CPU's are very easy to implement into a system because of their single voltage requirement plus all output signals are fully decoded and timed to
control standard memory or peripheral circuits_ The circuit
is implemented using an N-channel, ion implanted, silicon
gate MaS process.
FEATURES
Single chip, N-channel Silicon Gate CPU.
158 instructions-includes all 78' of the 8080A instructions with total software compatibility. New instructions include 4-, 8- and 16-bit operations with more
useful addressing modes such as indexed, bit and relative.
17 internal registers.
Three modes of fast interrupt response plus a nonmaskable interrupt.
Directly interfaces standard speed static or dynamic
memories with virtually no external logic.
1.0 /ls instruction execution speed.
Single 5 VDC supply and single-phase 5 volt Clock.
Out-performs any other single chip microcomputer in
4-, 8-, or 16-bit applications.
All pins TTL Compatible
Built-in dynamic RAM refresh circuitry.
a-BIT
DATA BUS
13
CPU AND
SYSTEM
~:;'~}:L~L \:"~Hi%:1
ACCUMULATOR
A
fLAGS
F
ACCUMULATOR
A'
FLAGS
F'
B'
C'
D'
E'
H'
L'
INTERRUPT
MEMORY
REFRESH
!i!:;!!'!'{i;;g;'T;;;HTH;;';;H;
VECTOR
I
:L!!ii;ijI'
R
INDEX REGISTER
IX
INDEX REGISTER
IV
STACK POINTER
SP
SPECIAL
PURPOSE
rrr
PROGRAM COUNTER
REGISTERS
PC
iHi1f.iiiiU3i,;;;;V
16-81T
ADDRESS BUS
"
]
GENERAL
PURPOSE
REGISTERS
Ml
MREQ
SYSTEM
CONTROL
19
20
!.::RQ
RD
ViR
RFSH
RFSH
(Refresh)
HALT
(Halt state)
WAIT
(Wait)
INT
(Interrupt
Request)
NMI
(Non
Maskable
Interrupt)
RESET
BUSRQ
(Bus
Request)
BUSAK
(Bus
Acknowledge)
AS
A,
"
A7
ADDRESS
AS
BUS
A,
HALT
AIO
WAIT
{
CPU
CONTROL
NM'
RESET
ZBO-CPU
Z80ACPU
A"
A"
A"
A14
A"
CPU
{BUSAa
BUS
CONTROL
BUSAK
'SV
GND
AO-A15
(Address Bus)
DO-D7
(Data Bus)
Ml
(Machine
Cycle one)
MREQ
(Memory
Request)
10RQ
(Input/
Output
Request)
RD
(Memory
Read)
WR
(Memory
Write)
Timing Waveforms
INSTRUCTION OP CODE FETCH
-,AD"" A15
4JL-':":'---+---l-A-~==r-:="---!A---+-
L ______
co- 01
IN
DATA OUT
IN
00-07
WAIT
-=-____- :IL-_-
-~~~ ~
-,.
PORT ADDRESS
AD .... A7
-1---- ---
------
00"" 07
...d
Cvcle
...!!:!..,
00-0,'
AO"" A15
~===t:==:t:x==::t:::::JPC~:::t===~==~E
'.E~F.~EESH
lORD
,....,-1}..--
00- 07
WAIT
-.....;;
-_ --------r----r----~----,,--r------- - - - _____1-_ _ _ _
1-____
L_
- - __
()
b
cc
combinations of
Indexed
Register
Implied
Register Indirect
Bit
Mnemonic
Symbolic Operation
Comments
Mnemonic
Symbolic Operation
LD r, s
r +- s
s == r, n, (HL),
(IX+e) , (IY+e)
LDI
LD d, r
d+-r
d==(HL),r
(IX+e) , (IY+e)
LDIR
LDd,n
d+-n
d == (HL),
(IX +e), (IY+e)
LDA,s
A+- s
LDd,A
d+-A
LD dd, nn
dd +- nn
LD dd, (nn)
dd +- (nn)
LD (nn), ss
(nn) +- ss
LD SP, ss
PUSH ss
SP +- ss
(SP-l) +- sSH; (SP-2) +- sSL
POPdd
dd L +- (SP); dd H +- (SP+l)
EX DE,HL
EX AF,AF'
EXX
DE
AF
EX (SP), ss
LDD
s == (BC), (DE),
(nn), I, R
d == (BC), (DE),
(nn), I, R
LDDR
dd == BC, DE,
HL, SP, IX, IY
dd == BC, DE,
HL, SP, IX, IY
ss== BC, DE,
HL, SP, IX, IY
SS = HL, IX, IY
ss = BC, DE,
HL, AF, IX, IY
dd = BC, DE,
HL, AF, IX, IY
HL
<+ AF'
<+
(BC) (BC)
DE <+ DE'
HL
HL'
(SP) H ssu (SP+ I)
sSH
ss == HL, IX, IY
CPI
A-(HL), HL +- HL+l
BC +- BC-l
CPIR
A-(HL), HL +- HL+l
BC +- BC-l, Repeat
until BC = 0 or A = (HL)
CPD
A-(HL), HL +- HL-l
BC +- BC-l
CPDR
A-(HL), HL +- HL-l
BC +- BC-1, Repeat
until BC= 0 or A = (HL)
ADDs
ADC s
SUB s
SBC s
ANDs
ORs
XORs
A+-A+s
A +- A + S + CY
A+-A-s
A +- A - s - CY
A+-Al\s
A+-AVs
A+-AEllS
Comments
A-(HL) sets
the flags only.
A is not affected
CY is the
carry flag
s == r, n, (HL)
(IX +e), (IY+e)
Mnemonic
Symbolic Operation
Comments
Mnemonic
Symbolic Operation
Comments
CP s
A- s
s = r, n (HL)
(IX+e), (IY+e)
BIT b, s
SET b, s
Z~Sb
d = r, (HL)
(IX+e), (IY+e)
RES b, s
Z is ze ro flag
s = r, (HL)
(IX+e), (IY+e)
INC d
DECd
~d+
d ~ d-I
HL~HL+ss
ADDHL, ss
ADC HL,ss
SBC HL, ss
ADD IX, ss
HL ~ HL + ss + CY
HL ~ HL - ss - CY
IX ~ IX + ss
ADD IY, ss
IY
IY + ss
INC dd
dd
dd + 1
DEC dd
dd
~dd
DAA
ss=BC, DE,
IX, SP
ss=BC, DE,
IY, SP
INI
(HL) ~(C),HL ~ HL + 1
B~B -1
INIR
(HL) ~(C),HL ~ HL + 1
B~B -1
Repeat until B = 0
IND
OUTen), A
OUT(C), r
(HL) ~(C),HL ~ HL - 1
B~B -1
(HL) ~(C), HL ~ HL - 1
B~ B-1
Repeat until B = 0
(n) ~A
(C)~ r
Operands must
be in packed
BCD format
OUTI
(C)~
OTIR
CPL
NEG
CCF
SCF
A~A
A~OO-A
OUTD
CY~CY
CY~
NOP
HALT
DI
EI
1M 0
1M 1
1M 2
RLCs
OTDR
No operation
Halt CPU
Disable Interrupts
Enable Interrupts
Set interrupt mode 0
Set interrupt mode 1
Set interrupt mode 2
8080Amode
Call to 0038H
Indirect Call
L&=l7_0~
RL s
~7_0~
s
RRs
[g--/7 _ ol--u
s
SRAs
SRLs
RLD
RRD
s = r, (HL)
(IX+e), (IY+e)
cS7~
o~
s
1\ 413
~ ~ 71(HL)
17 A413
~ ~ ~ ol(HL)
NC
C
JP (ss)
DJNZ e
PC ~ss
B ~ B-1, if B = 0
continue, else PC ~ PC + e
ss = HL, IX, IY
CALL nn
(SP-I) ~ PC H
(SP-2) ~ PCL> PC ~ nn
If condition cc is false
continue, else same as
CALLnn
If condition cc is true
PC ~ nn, else continue
cc
PC~PC+e
RSTL
(SP-I) ~PCH
(SP-2) ~ PCL' PC H ~ 0
PCL ~L
RET
PCL ~(SP),
PC H ~(SP+l)
If condition cc is false
continue, else same as RET
RETcc
PC~nn
kk{~Z
SLAs
(HL), HL+ HL + 1
B ~B-l
(C)~ (HL), HL ~ HL + 1
B ~ B-1
Repeat until B = 0
(C)~ (HL), HL ~ HL - 1
B~B -1
(C)~ (HL), HL ~ HL - 1
B ~B-l
Repeat until B = 0
If condition kk is true
PC ~ PC + e, else continue
CALL cc, nn
~7_0~
Set flags
rz~C
JRe
JRkk, e
~7~OiJ
r ~(C)
PO
PE
P
M
JP nn
JP cc, nn
RRC
A~(n)
INDR
dd =BC, DE,
HL, SP, IX, IY
dd =BC, DE,
HL, SP, IX, IY
- 1
IN A, Cn)
IN r, (C)
},,: BC, DE
HL,SP
sb ~ 1
sb ~O
RETI
RETN
cc
rz~C
PO
PE
P
M
cc
rz~c
PO
PE
P
M
Z80-CPU
A.C. Characteristics
TA =
Signal
4>
Ao-15
DO_7
Symbol
Parameter
Min
Max
Unit
Ic
Iw (4)H)
Iw I>Ll
Ir.f
Clock
("lock
Clock
("lock
.4
180
180
1121
[E)
2000
30
.usee
ID(AD)
IF(AD)
tea
teal'
ID(D)
IF(D)
IS<I>(D)
ISi"(D)
tdem
Idci
Icdf
taclll
taei
Period
Pulse Widlh. ("lock High
Pulse Widlh. Clock Low
Rise ond Fall Time
145
110
13
Wb
nsec
osec
nsec
osec
osec
nsec
osec
III
Test Condition
CL = 50pF
[I)
osec
[2)
laci = tc -80
osec
osec
[3)
lea = 1w(<I>L) + Ir - 40
[4)
leaf= 1w(<I>L) + Ir - 60
[5)
tdcm = tc - 210
[6)
tdci = tw(4)L)
[7)
[8)
Iw (MRL) = Ic - 40
[9)
Iw(MRH) = 1w(<I>H) + If - 30
osec
141
230
~u
osec
nsec
~u
60
15
16
171
C L = 50pF
osec
osec
IH
IDLi" (MR)
IDH<I> (MR)
IDHi"(MR)
Iw(MRL)
Iw(MRH)
10RO
IDL<I> (IR)
IDLij;(lR)
IDH<I> (IR)
IDHi"(1R)
10RO Delay
10RO Delay
10RO Delay
10RO Delay
RD
IDL<I> (RD)
IDLij;(RD)
IDH<I> (RD)
IDHi" (RD)
RD
RD
RD
RD
100
130
100
osec
osec
lIu
"sec
IDL<I> (WR)
IDLi"(WR)
tDHi"(WR)
Iw(WRL)
80
90
100
osec
osec
osec
osec
MI
IDL(MI)
tDH(MI)
130
130
osec
osec
C L = 50pF
RFSH
tDL(RF)
tDH(RF)
180
150
osec
osec
C L =50pF
WAIT
Is(WT)
HALT
ID(HT)
INT
MREO
WR
Delay
Delay
Delay
Delay
From
From
From
From
From
From
From
From
osec
0
100
100
100
18
191
[101
osec
osec
osec
osec
C L = 50pF
osec
osec
osec
osec
osec
C L = 50pF
C L = 50pF
CL = 50pF
nsec
70
300
osec
IS (IT)
80
osec
NMI
Iw(NML)
80
osec
BUSRO
IS (BO)
80
osec
BUSAK
IDL(BA)
IDH(BA)
RESET
IS (RS)
IF(C)
Imr
Mi
120
110
90
osec
osec
CL = 50pF
C L = 50pF
osee
100
1111
osec
osec
NOTES:
A. Dala should be enabled onlo Ihe CPU dalO bus when RD is active. During inlerrupl acknowledge dala
should be enabled when Mi and 10RO ore bOlh aClive.
B. All control signals are internally synchronized, so they may be totally asynchronous with resp~ct
10 Ihe clock.
C. The RESET signal must be active for a minimum of 3 clock cycles.
D. OUlpul Delay .s. Loaded Capacilance
TA = 70C
Vcc = +5V 5%
E.
Add 10nsec delay for each 50pf increase in load up to a maximum of 200pf for the data bus & lOOpf for address & control lines
Allhough sIalic by design. lesting guaranlees 1w(<I>H) of 200 j.lsec maximum
210
osec
90
110
100
110
+ tr -
R.- 2.1 KQ
TEST POINT
=
Load circuil for OulpUI
"0"
"I"
CLOCK
OUTPUT
INPUT
FLOAT
_IC_
Vee -.6V
.4SV
2.0 V
2.0 V
I!. V
.8V
.8V
O.S V
....J
f---l
tw I>\.)
--== .. -
A O-A15
10 (AD)
AO- 15
--- ~~ Jd----It-.....I""I'r-----t"'"'
- p -----
---r-:x
,~--- H~--
-----",
';,
IN
.. ---
_=-
10 (D)
00-1 {
-')t,
OUT
t---+-1~IOL (M1)
~~
___
~r------+-+-."
r-
---Iac-mi-+t!l.
H'OL'T'
RD
---~N
---~HM_~~-
~.~:!:.}MR(pr
tOL;j". IMlRII
II
(R~:
IOH.i. (MRl--
V~
(r\-_ _ _-+'I
((
OH'f> (MR)-
V-""'""""'"'M-_~(rrlr-+-_I+II_--+...,.
IW (MRL)
WR
I_
lORa
r-- tmr -
tOH.I. (lR)-
tOLi. (lR)
r=1r---ti---r----+~__~~......
~r--"". . -~~
tOH'f>
~R):-
tTi(RO)-
RD
IOL'i' (WR)
~
-------~---------H_-~---~_+~
~~
~
I---I~
10H<F (WR)-
:Ipr!=-'.
''''-~-/
~~" ... __ / , . - - -
l);
I-
I-,... _~
)<'------.. ~
---------,
tOH.j.(WR)
1-..... __/
_r-I.Ci-t-=r"l~---'lJ",,+-I_-+-1
________++-__
' _______-+I-_+-___-+_~~
.....
OL.i. (R.D)
WAIT
r-. .... __ /
IT__
t IW(WRLI
I--tdcm
tOL'i' (lR)
t=
IFr(e)
I-
-leal
).1-
tOH'f> (RDI-
11
_ _ _H-__
II'_ _ _ _
_ _ _ _+
~--
I.
:=-ItW~MRH)
tOH<i' (RO)-
1J
10H (RFI
~~---H_---IO-L-(R-FI---++~~
RFSH
MREO
),--+1---+
---+t-.. .,I"
Ml
'=-
10H (M1)-
Io-IF (D)
.1(
10 (HT)
,------
..
tW(~
tS(Bn)
IH
f---
)<~-----'x
---IS (RS)
tH
~~
) '-----"K
,--------
----,
~-IOL (BA)
10H (BA)
Comment
Note:
l.5W
T A = 25C, f = 1 MHz,
unmeasured pins returned to ground
Symbol
Parameter
Min.
Max.
Unit
V ILC
-0.3
0.45
V IHC
Vcc -.6
Vce+3
V IL
-0.3
0.8
VIH
2.0
Vcc
VOL
0.4
IOL=I.8mA
VOH
10H = -250/lA
ICC
150
III
10
/lA
VIN=O to Vee
lLOH
10
/lA
VOUT=2.4 to Vee
lLOL
-10
/lA
VOUT =O.4V
ILD
IO
/lA
0';; V IN ';;V ce
2.4
Test Condition
rnA
Min.
V ILC
VIII('
V IL
Typ.
Unit
-0.3
0.45
Vee -.6
Vee +.3
-0.3
OX
VIII
~.O
VOl.
0,4
IOL=I.~mA
VOII
lOll = -c,;O/JA
ICC
Pl)WCr
III
10
/JA
VIN=O to Vee
1l. 01I
10
/JA
VOllT=c.4 to VCc
1l.0l.
-10
/JA
VOUT =0.4V
IJ.D
Data
IO
/JA
O';;VIN';;V"
Bu~
CUI rell!
Parameter
Max.
Unit
C<I>
ClOck Capacitance
35
pF
CIN
Input Capacitance
pF
COUT
Output Capacitance
10
pF
Z80-CPU
Ordering Information
C P S E M-
Ceramie
Plastic
Standard 5 V 5% 0 too 70 0 C
Extended 5V 5% -40 to 85 C
Military 5V 10% _55 0 to 125C
T A = 25(, f = I MHz.
unmeasured pins returned to ground
Max.
Supply
Symbol
Capacitance
Capacitance
Symbol
CC
~.4
90
200
Test Condition
III A
Symbol
Parameter
Max.
Unit
(',~
ell,)I":" CapJI.'llarh:l'
35
pF
('IN
Input
';
pc
eOl Il
Output
10
pF
CapJI.'lIJlh:l'
Clpa(IIJIl\.'l'
Z80A-CPU
Ordering Information
C - Ceramic
P - Plastic
S - Standard 5V S% 0 to 70C
A.C. Characteristics
TA
= oOe
to 70C, Vee
Z80A-CPU
[1]
laem = Iw(4>H) + If - 65
[2]
I,ei = Ie -70
[3]
tea = tw(<I>L) + tr - 50
[4]
[5]
tdem = tc - 170
[6]
[7]
tcdf = tw(<I>L) + tr - 70
[8]
Iw (MRL) = Ie - 30
[9]
Iw(MRH) = Iw(4>H) + If - 20
[10] tw(WRL)
NOTES:
TEST POINT
A. Data should be enabled onlo Ihe CPU dala bus when Ri5 is active. During interrupt acknowledge data
should be enabled when iiI and IORQ are bolh aclive.
B.
All control signals are internally synchronized, so they may be totally asynchronous with respect
10 Ihe clock.
C. The RESET signal must be aclive for a minimum of 3 clock cycles.
D. Oulpul Delay vs. Loaded Capacitance
TA = 70C
Vee = +5V 5%
Add 10nsec delay for each 50pf increase in load up to maximum of 200pf for data bus and 100pf for
address & control lines.
E. Allhough sIalic by design, lesling guaranlees 1w(4)H) of 200 p.sec maximum
=
Load circuit for OUlpUI
=tc -30
Package
Configuration
A11
A12
A 13
A14
A 15
40
39
38
37
36
35
34
33
32
3
4
6
<I>
04
03
05
06
+5V
O2
07
Z80A
13
CPU
DO
01
INT
MREQ
IORQ
18
19
20
23
22
21
Package Outline
I~:::::::g::::::::1
A 10
A9
A8
A7
A6
A5
A4
Aa
A2
Al
AD
GNO
RFSH
Ml
RESET
BUSRQ
WAIT
BUSAK
WR
0.02LIN
10.05081
.0151.03811 _
.023 1.05841
II
.
-.
RD
I--
.0901.22861
.1001.2541
TYP.
.51411.30561
.58811.49351
I
.230 MAX 1.58421
J !
.1001.2541
'"i5O"13siT
".
~ .59011.49861
_I
.71011.80341
Wilshire Electronics
2554 State Street
Hamden, CT 06517
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TEL 3142915350
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Westmont, Illinois 60559
TEL 312 323 9670
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1550 Babbitt Avenue
Anaheim, CA 92805
TEL 7146349600
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MOUNTAIN
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7144539005
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Suite 10
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237 Sou th Curtis
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6921 San Fernando Road
Glendale, CA 91201
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4860 South Division
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CANADA
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Montreal, Quebec,
CANADA H4P 2K5
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MIDATLANTIC REGION
Zilog, Inc.
P.O. Box 92
Bergenfield, NJ 07625
TEL 201 385 9158
TWX 7109919771
MIDWESTERN REGION
Zilog, Inc.
1701 Woodfield Place
Suite 417
Schaumburg,IL 60195
TEL 312 8858080
TWX 910 291 1064
SOUTHWESTERN REGION
Zilog, Inc.
17982 Sky Park Circle
Suite C
Irvine, CA 92714
TEL 714 549 2891
TWX 910 5952803
EUROPEAN HDOTS
Zilog (UK) Ltd.
Nicholson House
Maidenhead, Berkshire
England
TEL (0628) 36131/2/3
TWX 848 609
1WX: 910-388-7621
Printed in U.S.A.
Copyright 1977 by Zilog. Inc.