IEEE - 31661

DESIGN AND FPGA IMPLEMENTATION

OF BINARY SQUARER USING VEDIC
MATHEMATICS
L. Sriraman1, K. Saravana Kumar2, T.N. Prabakar3
1

Asst. Professor , PG Scholar , Dean

Department of Electronics & Communication Engineering,
Oxford Engineering College, Trichy, Tamilnadu, India
1

tnpnls@gmail.com ,kskkavi21@gmail.com ,tnprabakar@gmail.com

Abstract: In this paper, a squarer based on Vedic

mathematics is proposed. Vedic mathematics is one of
the ancient Indian mathematics which contains sixteen
sutras. These sutras can be used to solve problems in
any branch of Mathematics in a faster way. The
proposed squarer is based on sutra called Ekadhikena
Purvena. It means that one more than the previous.
This sutra is used for finding the square of decimal
numbers ending with 5. In this paper this sutra is
generalized and used for squaring of binary numbers.
The proposed squarer is compared with duplex squarer
for 8, 16 and 32-bit cases in Cyclone III FPGA
EP3C16F484C6. The proposed squarer saves area

by almost 50% and reduces delay by 50% when

compared with duplex squarer in 32-bit case.
Keywords: Squarer, Vedic Mathematics, Ekadhikena
Purvena, FPGA, Duplex squarer
I.
INTRODUCTION
In Digital Signal Processing (DSP) applications
multiplier and squarer are the most common
functional units, used to perform various arithmetic
operations. The throughput of the system greatly
depends on the performance of these data path
operators. Hence these functional units must work in
an optimized way consuming less area and power,
and operating in higher speed.
The remaining part of the paper is organized as
follows: The second section gives an introduction
about Vedic Mathematics, third section discusses
about Urdhava Multiplier, fourth section discusses
Dwanda Yoga (Duplex squarer), fifth section
discusses about proposed squarer, sixth section
discusses about experimental results, seventh section
discusses about conclusion.

II. VEDIC MATHEMATICS

Vedic Mathematics[1] is the name given to the
ancient system of Indian Mathematics which was

rediscovered from the Vedas between 1911 and 1918

by Sri Bharati Krshna Tirthaji (1884-1960). Vedic
Mathematics contains sixteen sutras which are
enlisted below alphabetically along with their
meanings.
1. (Anurupye) Shunyamanyat If one is in ratio, the
other is zero.
2.Chalana-Kalanabyham
Differences
and
Similarities.
3. Ekadhikina Purvena By one more than the
previous one.
4. Ekanyunena Purvena By one less than the
previous one.
5. Gunakasamuchyah The factors of the sum is
equal to the sum of the factors.
6. Gunitasamuchyah The product of the sum is
equal to the sum of the product.
7. Nikhilam Navatashcaramam Dashatah All from
9 and the last from 10.
8. Paraavartya Yojayet Transpose and adjust.
9. Puranapuranabyham By the completion or
noncompletion.
10. Sankalana-vyavakalanabhyam By addition and
by subtraction.
11. Shesanyankena Charamena The remainders by
the last digit.
12. ShunyamSaamyasamuccaye When the sum is
the same that sum is zero.
13. Sopaantyadvayamantyam The ultimate and
twice the penultimate.
14. Urdhva-tiryakbyham Vertically and crosswise.
15. Vyashtisamanstih Part and Whole.
16.Yaavadunam Whatever the extent of its
deficiency
Using these sutras, problems in any branch
of mathematics can be solved in a faster way. Due to
its regularity Vedic Mathematics is suitable for
FPGA implementation[2]. A higher throughput can

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IEEE - 31661

be obtained by designing the data path operators

using Vedic Mathematics.[2]
III. URDHAVA MULTIPLIER
Urdhava Tiryakbhyam[1][2] (Vertically and
Crosswise), is one of Sixteen Vedic Sutras and deals
with the multiplication of numbers. The sutra is
illustrated in Example 1 and the hardware
architecture is depicted in Fig.2. In this example two
decimal numbers (31 35) are multiplied. Line
diagram for the multiplication of two, three and four
digit numbers is shown in Fig. 1 using Urdhava
Method. The digits on the two ends of the line are
multiplied and the result is added with the previous
carry. When three or more lines are present, all the
results are added to the previous carry. The least
significant digit of the number thus obtained acts as
one of the result digit and the rest act as the carry for
the next step. Initially the carry is taken to be zero.
Example 1: 31 35 = 1085
3 1
1
3 1

3 5

3 5

15+3=1 8

9 + 1 =10

Carry to next stage

Answer: 31 35 = 1085

In case, if there is a carry in (ad+bc) term, that is

added to ac.
From the Example 1, it is observed that all the partial
products are generated in parallel. So the speed of the
multiplier is higher compared to array multiplier.
The above discussions can now be extended to
multiplication of binary number system with the
preliminary knowledge that the multiplication of two
bits a0 and b0 is just an AND operation and can be
implemented using simple AND gate. To illustrate
this multiplication scheme in binary number system,
consider the multiplication of two binary numbers
a3a2a1a0 and b3b2b1b0. As the result of this
multiplication would be more than 4 bits, the product
is expressed as r7r6r5r4r3r2r1r0. Least significant bit r0
is obtained by multiplying the least significant bits of
the multiplicand and the multiplier as shown in the
Fig.2.

Figure 1: Line Diagram for Urdhava Multiplication of 2, 3 and 4

digits

As shown in fig.1, the digits on both sides of the line

are multiplied and added with the carry from the
previous step. This generates one of the bits of the
result (rn) and a carry (cn). This carry is added in the
next step and thus the process goes on. If more than
one line are there in one step, all the results are added
to the previous carry. In each step, least significant
bit acts as the result bit and the other entire bits act as
carry. For example, if in some intermediate step, we
get 110, then 0 will act as result bit and 11 as the
carry (referred to as cn in this text). It should be
clearly noted that cn may be a multi-bit number.
Thus the following expressions (1) to (7) are derived:
r0 = a0b0
(1)
c1r1 = a1b0 + a0b1
(2)
c2r2 = c1 + a2b0 + a1b1 + a0b2
(3)
c3r3 = c2 + a3b0 + a2b1 + a1b2 + a0b3
(4)
c4r4 = c3 + a3b1 + a2b2 + a1b3
(5)
c5r5 = c4 + a3b2 + a2b3
(6)
c6r6 = c5 + a3b3
(7)
with c6r6r5r4r3r2r1r0 being the final product. Partial
products are calculated in parallel and hence the
delay involved is just the time it takes for the signal
to propagate through the gates.

Figure 2: Urdhava Multiplier Hardware Architecture

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IEEE - 31661

The main advantage of the Vedic

Multiplication algorithm (Urdhava Tiryakbhyam
Sutra) stems from the fact that it can be easily
implemented in FPGA due to its simplicity and
regularity [3]. The digital hardware realization of a 4bit multiplier using this Sutra is shown in Fig. 3.
This hardware design is very similar to that of the
array multiplier where an array of adders is required
to arrive at the final product. Here in Urdhava, all the
partial products are calculated in parallel and the
delay associated is mainly the time taken by the carry
to propagate through the adders.
IV. DWANDWA YOGA
The Duplex squarer or Dwanda Yoga[3] is
based on duplex property which is used for squaring
of numbers. To find the square of a number
containing even number of digits, the result is taken
as twice the product of the outermost pair and then
twice the product of the next outermost pair and so
on, till no pairs are left. To find the square of a
number containing odd number of elements, the same
procedure is followed except one bit left in the
middle and this enters as its square along with the
product elements. This is explained in (8) to (13).
D(a) = a2
(8)
D(ab) = 2ab
(9)
D(abc) = 2ac + b2
(10)
D(abcd) = 2ad + 2bc
(11)
D(abcde) = 2ae + 2bd + c2
(12)
D(abcdef) = 2af + 2be + 2cd
(13)
As seen above, D of any number is the sum of square
of the middle number and two times the product of
the other pair. The following example 2 illustrates
the algorithm for decimal numbers.
Example 2: (13) 2 = 169
D (3) = 32 = 9
D (13) = 2*1*3 = 6
D (1) = 12 = 1
Thus for a single bit number, the D is square of the
number itself. For a 2 bit number, it is twice their
product. For a 3 bit number, it is the sum of twice the
product of the outermost pair and square of the
middle number. For a 4 bit number, it is the sum of
twice the product of the outermost pair and twice the
product of the innermost pair. Example 3 describes
the procedure for binary numbers.
Example 3: (112)2 = (1001)2
D (1) =12.
D(11) =2*1*1=102
D (1) =12.

D (b)

D (ab)

10

10

D (a)

Thus, 1122 = 10012

V. PROPOSED SQUARER
The proposed squarer is based on the Vedic
sutra of Ekadhikena Purvena[1]. It means one more
than the previous. It is suitable for squaring of
numbers ending with 5. Example 4 explains this
sutra in detail for decimal numbers.
Example 4: 352=1225
1. The square of 5 is 25 which is written in
the right part of the answer.
2. As per sutra the previous of 5 is 3 and
one more than that is 4. Thus 34=12(i.e.
n(n+1)=n2+n). This forms the left part of
the answer.
In the same way, the sutra can be applied to find the
square of any number ending with 5. In the
proposed system, the above sutra is suitably modified
for squaring binary numbers. The algorithm is
explained below, for two bit binary numbers.
Algorithm:
Step 1: Identify the LSB of the number.(12 or 02)
Step 2: If it is 12, then n(n+1)is to be used where n
is the MSB after truncating LSB. Hence, n2=n (same
number). Further, n2+n = n+n = 2n, for which one
bit left shift is performed.
Step 3: If it is 02, take MSB as it is. Because for
LSB 02, n2 is obtained which is equal to n.
Step 4: Shift the answer of step 2 or step 3, two
times towards left.
Step 5: If LSB is 12 add 12 to the shifted value to
get the final answer. If LSB is 02 the shifted value
itself, is the final answer.
Example 5 explains the above algorithm for LSB
ending with 02. Example 6 explains the same
algorithm for LSB ending with 12.
For realization of higher order cases the
formula (a+b)2 [5] is used. For finding the square of
4-bit number a2 and b2 are obtained by
instantiating 2-bit squarer. The term 2ab is obtained
by using a 22 Urdhava multiplier. Thus in this way
the higher order squarers are realized. Example 7
explains the squaring of a 4-bit number.
Example 5: (102)2 = (100)2
1. LSB = 02

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IEEE - 31661

2. MSB = 12. Same number is retained = 12

3. Two times left shift. 12= 1002
(102)2 = (100)2
Example 6: (112)2 = (1001)2
1. LSB = 12
2. MSB = 12. Perform 1-bit left shift. 12 = 102
3. Two times left shift. 102= 10002
4. Add 12 to the final answer 10002+12 = 10012
(112)2 = 10012
Example 7: (11112) 2 = (11100001)2
Step 1: Split the input in to two equal halves (a=112
and b= 112).
Step 2: Apply these inputs to 2-bit squarer. Thus
a2=10012 and b2= 10012
Step 3: Multiply the two inputs 112 and 112 by using
urdhava multiplier. Product =10012 Perform left shift
by one time to get the result 2ab as (10010)2.
Step 4: Perform left shift by 4-times for a2 to get the
result as 100100002 and 2-times for 2ab= 10010002.
Step 7: Add the results a2, b2 and 2ab to get the result
as 111000012
VI. EXPERIMENTAL RESULTS
Tables 1, 2, and 3 depict the results for 8-bit, 16bit and 32-bit cases of the duplex squarer and the
proposed squarer. All the squarers are implemented
as combinational blocks and compared. Fig. 3[a] and
3[b] shows the schematic view of the proposed
system and on board results using in-system memory
content editor respectively.
Table 1 : 8-bit squarer
Criterion
Duplex
Squarer
Area - Logic Elements
107
Delay(ns)
16.704
Dynamic(mW)
3.60
Static(mW)
51.84
I/O Thermal (mW)
65.13
Total power
120.58
dissipation(mw)
Table 2 : 16-bit squarer
Criterion
Duplex
Squarer
Area - Logic Elements
386
Delay(ns)
29.437
Dynamic(mW)
7.85
Static(mW)
51.49
I/O Thermal (mW)
106.39
Total power
166.18
dissipation(mw)
Table 3 : 32-bit squarer
Criterion
Duplex
Squarer
Area - Logic Elements
1,417
Delay(ns)
73.556
Dynamic(mW)
27.33
Static(mW)
52.34
I/O Thermal (mW)
264.32
Total power
343.98
dissipation(mw)

Proposed
Squarer
68
16.520
1.94
51.78
35.02
88.74
Proposed
Squarer
228
25.449
1.98
51.83
58.34

Figure 3[a]: Schematic view of the Proposed squarer

Figure 3[b]: Output response of proposed squarer using on

board In-system memory content editor

VII. CONCLUSION
From figure 4 to figure 6, it is evident that
for higher order bits the proposed squarer yields
better performance than the duplex squarer. The
proposed squarer saves area by almost 50% and
reduces delay by 50% when compared with duplex
squarer in 32-bit case. In [20], multiplier is realized
using squarer. [20] use a ROM having squares of
numbers. This ROM can be replaced by the proposed
squarer which will reduce the dynamic power. Also
the same squarer module can be used as a multiplier
and also as a squarer.

112.16
Proposed
Squarer
728
36.979
5.09
51.92
88.38
145.38

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Figure 4: 8-bit

IEEE - 31661

Figure 5:16-bit

Figure 6:32-bit

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