SPEF: Standard

Parasitic
Exchange Format
Shanuj Garg (2014H123162P)
Meet Shah (2014H123168P)

OUTLINE

Introduction

Header denition

Name map denition

External denition

Internal definition

Process and temperature variation denition

References

Introduction

IEEE STD for representing parasitic data

Data representation in ASCII format

Resistance Inductance and Capacitances are called

parasitic data

Done after place and route

Used to calculate IR drops and power calculations.

Post layout static timing analysis can be done

Inductance information is not included in spef

General syntax

A typical SPEF file will have 4 main sections

a header section,
a name map section,
a top level port section and
the main parasitic description section.

keywords are preceded with a *. For example, *R_UNIT,

*NAME_MAP and *D_NET.

Comments start anywhere on a line with //.

Header definition

14 lines long
contains information about

the design name,

the parasitic extraction tool,
naming styles and
- units.

it is important to check the header for units as they vary

across tools. For example SPEF from Astro will be in pF
and kOhm while SPEF from Star-RCXT will be in fF and
Ohm.

Header example
// Header definition
*SPEF "IEEE 1481-2009"

*DESIGN "Sample"
*DATE "Monday December 18, 1995"
*VENDOR "Sample Tool"
*PROGRAM "Sample Generator"
*VERSION "1.1.0"
*DESIGN_FLOW "Sample Flow"
*DIVIDER /
*DELIMITER :
*BUS_DELIMITER [ ]
*T_UNIT 1 NS
*C_UNIT 1 PF

*R_UNIT 1 OHM
*L_UNIT 1 HENRY

Name Map Section

allows to map a positive integer number to a name that may

be used multiple times.

Using an integer number instead of complete name leads to

reduction of file size considerably.

User can write a script file also to replace the existing

integer with its name. but file size will increase.

Power and ground net denition may be given after that

Example
// Name map definition
*NAME_MAP
*1 in1
*2 out1

*3 net1
*4 net2
*5 net3
*6 net4

External definition (Port Section)

Simply a list of the top level ports in a design

Annotated as input, output or bi-direct with an I, O or

B representation.

For example:
*PORTS

*1 I
*2 I
*3 O
*4 O
*5 B
*6 B

Internal definition (Parasitics)

Each extracted net will have a *D_NET (Detailed Net)

section.

consisting of a *D_NET line, a *CONN section, a *CAP

section, *RES section and a *END line.

Single pin nets will not have a *RES section.

Nets connected by abutting pins will not have a *CAP

section.

The *D_NET line tells the net name and the net's total
capacitance. This capacitance will be the sum of all the
capacitances in the *CAP section.

*R_Net (Reduced Net) specification is also available in

some tools

CONN section

The *CONN section lists the pins connected to the net.

A connection to a cell instance starts with a *I.

A connection to a top level port starts with a *P.

Syntax: *I/*P <pin name> <co-ordinates> <direction>

<loading or driving information>

The direction will be I, O or B for input, output or bi-direct.

the loading information will be *L and the pin's capacitance.

the driving information will be *D and the driving cell's type.

Coordinates for *P port entries may not be accurate because

some extraction tools look for the physical location of the
logical port (which does not exist) rather than the location
of the corresponding pin.

CAP Section

The *CAP section provides detailed capacitance

information for the net.

Entries in the *CAP section come in two forms,

one for a capacitor lumped to ground (lumped
capacitance) and
one for a coupled capacitor (coupling capacitance).

The entries includes identifying integer, node

names (pin name in case of 1 ground connection)
and capacitance values

RES Section

The *RES section provides the resistance network for the

net.

Entries in *RES section contain 4 fields,

an identifying integer,
two node names and

the resistance between these two nodes.

Example
// Detailed one net description
*D_NET *4 0.287695
*CONN
*I *5:Z O *D DRIVER_CELL_1
*I *6:A I *D DRIVER_CELL_1
*CAP
1 *5:Z 0.189802
2 *6:A 0.097893
*RES

1 *5:Z *6:A 1.054678

*END

Process and Temperature

Variations

New in the IEEE Std 14812009 compared to older

versions of the standard.

It denes the process parameters that affect

capacitances, inductances, and resistances of
interconnects.

Example
*VARIATION_PARAMETERS
0 "field_oxide_T" D X X 0.080 1

1 "poly_T" D X X 0.030 1
2 "poly_W" D X X 0.023 1
3 "Diel1_T" X X D 0.050 1

4 "metal1_T" X N X 0.050 1
5 "metal1_W" X N X 0.030 1
6 CRT1
7 CRT2

27.0000

The rst lines characterize process parameters as

thickness, width, and permittivity of dielectric layers by its
parameter index i, a string and the variation parameters
types (N, D, or X) for capacitance, resistance, and
inductance

followed by the variation coefcient and the normalization

factor.

Afterward, the parameter indices for rst and second order

temperature sensitivities of resistances are given.

The characterization of capacitances, inductances, and

resistances can be extended by its sensitivities.

The variation description follows after *SC. It is given by

pairs of parameter index and then associated sensitivity
coefcient.

For example
*CAP
1 *5:Z 0.189802 *SC 0:-0.005 1:0.029 1 2:0.026 1
*RES

1 *5:Z *6:A 1.054678 *SC 4:0.900 5:0.53 1 6:0.0032 1 7:-0.0002 1

References

http://en.wikipedia.org/wiki/Standard_Parasitic_Exchan
ge_Format Dated: March 29, 2015

http://www.vlsi-expert.com/2010/08/how-to-readspef.html Dated: March 29,2015

Standard Formats for Circuit Characterization Process

Variations and Probabilistic Integrated Circuit Design
(springer document) by Manfred Dietrich, Joachim
Haase