AfterLogintotheLinuxmachinefollowthestepstoworkonCadencenclaunch/ncsimulator:

A
Awordofcaution,Linuxiscasesensitivesopleasemindthelettercaseandthespaces.
1...Let'sSaywearehere:[user@localhost~]$thatisthepromptatcurrenthomedirectoryforuser.Youwilltype
c
commandsafter$(don'ttypeletter$)
Makingadirectory:makeadirectoryataplaceyouwouldliketo.Say,wearecreatingadirectoryontheDesktop
(mindthecase):
m
mkdirDesktop/exercises.
2.Changetothisdirectory:
cdDesktop/exercise
promptwillchangeto[user@localhostexercise]$
t
thismeansweareintheexercisefolder.
3.nowmakethevhdl/verilogfilesinthisdirectoryinanytexteditor:
l
likeso:gedit(alternativelyyoucanusevieditor)adder.vhd,startwritingandsave.
wearesettoopenCadencetools:
4.Firstchangetocshellbytypingcshoncommandpromptie.
[user@localhostexercise]$csh
5.
[user@localhostexercise]$source/cad/cadence/cshrc1
6.
[user@localhostexercise]$nclaunchnew
ClickonMultiStep:

click'createcds.libfile'

ClickSaveandatnextwindowclick'OK',click'OK'oncemoreonthe'opendesigndirectory'window:

ThisistheNCLaunchmaininteractivewindow:
Youwillseeyourvhdlfilesinthefilesbrowserontheleftandthereisalibrarybrowserontheright:

CompiletheleafcellsFIRSTbyselectingitandclickingonVHDLbutton.Alternatively,youcandoubleclick.
Compilealltheleafcells(VHDLfiles)FIRST.Nowcompilethetopmodule.Here,aluistheleafcellandalu_test
isthetopcell(asalu_testcontainsalu).
Aftercompilationthecellscanbeseeninthelibrarybrowserundertheyellowhat(thisistheworklibrary).

Elaborate:
Nowyouelaborateyourdesignbyexpandingthe+ontheyellowhatandselectingandelaboratingthecompiles
modulesfromthere.Foreleborate,eitherrightclickandchoose'NCElab'orclicktheelaboratebutton.You
elaborateallthemodulesonebyonestartingfromtheleafmodulesfinallytothetopmodule.

Ifyouhavedonethingsright,youwillseesomeentriesalreadypopulatedunder'snapshots'inthelibrarybrowse:

Compile

Elaborate

Elaboratethese
Compilethese

Simulatethese

LaunchCadenceSimulatorNCSim:
Forinstance,inthisexample,rightclickon'worklib.alu_test.vhdl'andselectNCSim(Wewillanalyze/simulatethis
snapshot).Click'OK'onthenextwindow.
Thiswillopenthesimulator/analyzertoolwindow.
Rightclickthechipsign(WORKLIB.ALU_TEST(VHDL))intheDesignBrowser.Andselect'sendtowaveforn
window'.

Sendthistowaveform

Thisopensthewaveformwindow:
Nowifyouhavealreadymadeatestbench(whichinthiscasewealreadyhave,alu_test)youarejustclickaway
fromthesimulationresults.
Play/RunButton

fs

Rightnexttotheplaybuttonthereisadownarrow,clickthisarrowanditwillshowsomenumeralvaluesay,10.If
not,typeinsomevalue.Thisvalueistheunitoftimethatyouwantyoursimulationtobecarriedout.
Timeframeunit'fs'nexttothereddownarrowbuttondecidestheunit.Forthisinstance,theunitsarechosentobe
'fs'andyouinserted10atthe'play'buttonsoitmeansthatthesimulationcanbecarriedouttill10fstime.Itwill
endthereandifyouwanttorunanother10fswhatyoudoistojustclicktheplaybuttonagain.
NCLaunchhasveryextensivehelponthedetailsonhowtousedifferenttoolsandwindows.Forfurtherdetails
clickonhelpintheextremerightcorner,selectthe'<tool>userguide'