Digital Design Review

Carlos Luis Bernal

Basic Logic Gates

Designing with NAND and NOR

Gates

Implementation of NAND and NOR

gates is easier than that of AND and
OR gates (e.g., CMOS)

Implementation
VDD

VDD

A
B

A&B

A+B

Designing with NAND and NOR

Gates

a ~& b
a ~| b
1
0
~a

a&b
a|b
a^b
a ~^ b

Y = ~A

A
Y=(A|B)

A
B

Y = ~( A & B )

A
B

Y=~(A|B)

Y=(A&B)
B

A
Y=(A^B)
B
A
B
Y=~(A^B)

Combinational Logic

Has no memory => present state depends

only on the present input
X = x1 x2... xn
Z = z1 z2... zm
x1
x2

z1
z2

xn

zm

Z( t ) = F( X( t))

Combinational-Circuit Building
Blocks

Multiplexers
Decoders
Encoders
Code Converters
Comparators
Adders/Subtractors
Multipliers
Shifters

Multiplexer

Have number of data inputs, one or more select

inputs, and one output
It passes the signal value on one of data inputs to
the output

w0

s
w0
w1

(a) Graphical symbol

f
s
0
1

w1
(c) Sum-of-products circuit

w0
w1

(b) Truth table

f = s' w0 + sw1

4 To 1 Mux
S0
S1

D0
D1

D2
D3

Combinational circuit that selects binary information

from one of many inputs lines
Selection of a particular input line is controlled by a
set of selection input variables
There are 2n input lines and n selection inputs

Using Multiplexers for

combinational functions
F( X, Y, Z) = m(1, 2, 6, 7)

m0
m1
m2
m3
m4
m5
m6
m7

X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

F
0
1
1
0
0
0
1
1

X
Y

Z
0
1

S0
S1
D0
D1
D2
D3

F = m1 + m2 + m6 + m7

Multiplexer provides a method of implementing any a Boolean

function of n variables with a multiplexer that has n - 1
selection inputs
The first n - 1 variables of the function are connected to the
selection inputs of the multiplexer.
The remaining single variable of the function is used for the
data inputs. If the single variable is denoted by Z, each data
input of the multiplexer will be either Z, Z, 1, or 0

Multiplexers: 4-to-1 Multiplexer

s0
s1
w0
w1
w2
w3

s1 s0
00
01
10
11

(a) Graphic symbol

0
0
1
1

0
1
0
1

f
w0
w1
w2
w3

s0
w0
s1
w1
f

(b) Truth table

w2

w3
(c) Circuit

f = s1 ' s0 ' w0 + s1 ' s0 w1 + s1s0 ' w2 + s1s0 w3

Multiplexers: Building Larger

Mulitplexers
s
0

s1
w0

s1

w3

s0
w0

w1

w4

s2
s3

w7
0
1

w2

w3

f
w8
w11

(b) 16-to-1 using 4-to-1

(a) 4-to-1 using 2-to-1

w12
w15

Synthesis of Logic Functions

Using Muxes
w1 w2

w2
w1

0
1
1
0

(a) Implementation using a 4-to-1 multiplexer

w1 w2

(b) Modified truth table

w1

w2

w2

w1
w2
f

(c) Circuit

Synthesis of Logic Functions

Using Muxes
w1 w2 w3

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

w1 w2

0
0
1
1

0
1
0
1

(a) Modified truth table

0
w3
w3

w2
w1

1
0

w3

1
(b) Circuit

Demultiplexers
Y
D0
S0

D1
D2
D3

S1

The data input Y has a path to all four outputs, but the input
information is directed to only one of the outputs, as specified
by the two selection lines S1 and S0
The demultiplexer circuit shows that it is identical to a 2 to 4
line decoder with enable input, with F as the enable input
Although the two circuits have different applications, their
logic diagrams are exactly the same. For this reason, a
decoder with enable input is referred to as a
decoder/demultiplexer

Half Adder
X

Half
Adder

C = X.Y
S = X'.Y + X.Y' = XY

(X + Y)

X
Y

X
0
0
1
1

Y
0
1
0
1

C
0
0
0
1

S
0
1
1
0

Full Adder
Module

Truth table

Sum = X' Y' Cin + X' YCin'+ XY' Cin'+ XYCin

Cout = X' YCin + XY' Cin + XYCin'+ XYCin

X
Y

(XY)

S
(XY)

C
Z

C = X.Y + (XY).Z
S = (XY)Z

N bits Adder
Y4 X4

Y3 X3
C4

C5

FA

S4

Y2 X2
C3

FA

S3

Y1 X1
C2

FA

S2

Input
Output

Ci+1 = Xi .Yi + (Xi Yi ) .Ci

Si = Xi Yi Ci

FA

S1

C1

Adder cum Substractor

Y4 Y3 Y2 Y1
S
X4 X3 X2 X1

Cout

4-bit
parallel adder

Cin

S4 S3 S2 S1

A 4-bit adder cum subtractor

Analysis:
If S=1, then
X + (1's complement of Y) +1
appears as the result.
If S=0, then X+Y appears as
the result.

Comparators
Let A = A3A2A1A0 , B = B3B2B1B0; xi = Ai.Bi + Ai'.Bi'
A3

x3
A3.B3'

B3
A2

A3'.B3
A3'.B3 + x3.A2'.B2

x2

+ x3.x2.A1'.B1
+ x3. x2.x1.A0'.B0

B2

(A < B)
A1

x1
A3.B3' + x3.A2.B2'

B1

+ x3.x2.A1.B1'
+ x3. x2.x1.A0.B0'

A0

x0

(A > B)

B0
(A = B)
x3. x2.x1.x0

Decoders: n-to-2n Decoder

Decode encoded information: n inputs, 2n

outputs
If En = 1, only one output is asserted at a
time
One-hot encoded output


m-bit binary code where exactly one bit is set to

1
y = w '...w ' w ' En
0

w0
n
inputs
Enable

2
outputs

En

y2n 1

y1 = w n 1'...w1' w0En

y0

wn 1

n 1

y 2 = w n 1'...w1w0' En
...
y 2n 1 = w n 1...w1w0En

Decoders: 2-to-4 Decoder

En w w
1
1
1
1
0

0
0
1
1
x

0
1
0
1
x

1
0
0
0
0

0
1
0
0
0

0
0
1
0
0

0
0
0
1
0

w0
y0
w1
y1

y2

(a) Truth table

w0
w1
En

y0
y1
y2
y3

y3
En
(c) Logic circuit

(b) Graphic symbol

Decoders: 3-to-8 Using 2-to-4

w0
w1
w2

En

w0
w1
En

w0
w1
En

y0
y1
y2
y3

y0
y1
y2
y3

y0
y1
y2
y3

y4
y5
y6
y7

Decoders: 4-to-16 Using 2-to-4

w0
w1

w0
w1
En
w0
w1

w2
w3

w0
w1

En

En

y0
y1
y2
y3

En
w0
w1
En
w0
w1
En

y0
y1
y2
y3

y0
y1
y2
y3

y0
y1
y2
y3

y4
y5
y6
y7

y0
y1
y2
y3

y8
y9
y10
y11

y0
y1
y2
y3

y12
y13
y14
y15

Encoders

Opposite of decoders

Encode given information into a more compact form
Binary encoders

2n inputs into n-bit code

Exactly one of the input signals should have a value of 1,
and outputs present the binary number that identifies which input is equal to 1
Use: reduce the number of bits (transmitting and storing information)

w0
y0
n

n
outputs

2
inputs
w

2n 1

yn 1

Encoders: 4-to-2 Encoder

w3 w2 w1 w0
0
0
0
1

0
0
1
0

0
1
0
0

1
0
0
0

y1 y0
0
0
1
1

0
1
0
1

w0
w1

y0

w2
y1

w3

(a) Truth table

(b) Circuit

Priority Encoders

Each input has a priority level associated

with it
The encoder outputs indicate the active
input
that has the highest priority
(a) Truth table for a 4-to-2 priority encoder

w3 w2 w1 w0
0
0
0
0
1

0
0
0
1
x

0
0
1
x
x

0
1
x
x
x

y1 y0

d
0
0
1
1

0
1
1
1
1

d
0
1
0
1

Code Converters

Convert from one type of input encoding to a

different output encoding


E. g., BCD-to-7-segment decoder

w3 w2 w1 w0

w0
w1
w2
w3

a
b
c
d
e
f
g

(a) Code converter

a
f
e

b
g

d
(b) 7-segment display

0
0
0
0
0
0
0
0
1
1

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
0
0

0
1
0
1
0
1
0
1
0
1

1
0
1
1
0
1
1
1
1
1

1
1
1
1
1
0
0
1
1
1

1
1
0
1
1
1
1
1
1
1

1
0
1
1
0
1
1
0
1
1

1
0
1
0
0
0
1
0
1
0

1
0
0
0
1
1
1
0
1
1

0
0
1
1
1
1
1
0
1
1

(c) Truth table

Connecting Building Blocks: Tristate

Logic and Busses

Four kinds of tri-state buffers



B is a control input used to enable and

disable the output

Data Transfer Using Tristate Bus

Laws and Theorems of Boolean

Algebra

Laws and Theorems of Boolean

Algebra

Sequential Circuits

Circuits with Feedback

Outputs = f(inputs, past inputs, past outputs)
 Basis for building "memory" into logic circuits


Door combination lock is an example of a sequential

circuit

State => memory

State is can be "output" and "input" to combinational

logic or to other sequential logic

Simplest Circuits with Feedback

Two inverters form a static memory cell



Will hold value as long as it has power applied

"1"
"stored value"
"0"

How to get a new value into the memory

cell?



Selectively break feedback path

Load new value into cell
"remember"

"data"

"load"

"stored value"

General CircuitM
inputs

::

Combinational
Logic

::

outputs

Memory

Clocks

Used to keep time




Wait long enough for inputs to settle

Then allow to have effect on value stored

Clocks are regular periodic signals




Period (time between ticks)

Duty-cycle (time clock is high between ticks expressed as % of period)
duty cycle (in this case, 50%)

period

Edge-Triggered Flip-Flops

Positive edge-triggered


Inputs sampled on rising edge; outputs change after

rising edge

Negative edge-triggered flip-flops



Inputs sampled on falling edge; outputs change after

falling edge
100
D

CLK
Qpos
Qpos'
Qneg
Qneg'

positive edge-triggered FF
negative edge-triggered FF

Comparison of Latches and

Flip-Flops
D Q
CLK
positive
edge-triggered
flip-flop

CLK

Qedge
D Q
G

Qlatch

CLK
transparent
(level-sensitive)
latch

behavior is the same unless input changes

while the clock is high

Timing Methodologies

Rules for interconnecting components and clocks



Guarantee proper operation of system when strictly

followed

Approach depends on building blocks used for

memory elements


Focus on systems with edge-triggered flip-flops

Found in programmable logic devices

Basic rules for correct timing:



(1) Correct inputs, with respect to time, are provided to

the flip-flops
(2) No flip-flop changes state more than once per
clocking event

Definition of terms
 clock: periodic event, causes state of memory element to change;
can be rising or falling edge, or high or low level
 setup time: minimum time before the clocking event by which the
input must be stable (Tsu)
 hold time: minimum time after the clocking event until which the
input must remain stable (Th)
Tsu Th

data

D Q

input
clock
there is a timing "window"
around the clocking event
during which the input must
remain stable and unchanged
in order to be recognized

clock
stable changing
data
clock

D Q

Typical Timing Specifications

Positive edge-triggered D flip-flop

 Setup and hold times
 Minimum clock width
 Propagation delays (low to high, high to low, max and
typical)
D

CLK

Tsu Th
20ns 5ns

Tsu
20ns

Th
5ns

Tw 25ns
Tplh
25ns
13ns

Tphl
40ns
25ns

all measurements are made from the clocking event that is,
the rising edge of the clock

Synchronous vs.
Asynchronous Designs

Clocked synchronous circuits

 Inputs, state, and outputs sampled or changed in relation to a
common reference signal (the clock)
Asynchronous circuits
 Inputs, state, and outputs sampled or changed independently
of a common reference signal (glitches/hazards a major
concern)

Stay away from asynchronous designs!
Asynchronous inputs to synchronous circuits
 Inputs can change at any time, will not meet setup/hold times
 Dangerous, synchronous inputs are greatly preferred
 Cannot be avoided (e.g., reset signal, memory wait, user
input)

Solution: synchronize with clock as early as possible !

Latches
S

E
Q

0
1

1
1

1
1

0
0

1
1

0
1

0
0

1
1

1 (forbidden)

1
1

0
1

0
1

0
0

no change

Flip Flops
D
Clk

S
C
R

CLK

CLK
CLK
E

S
C
R

1
1

0
1

0
1

0
0

no change

Flip Flops
J
0
0
1
1

D
0
1

K
0
1
0
1

JK Flip-Flop
Q+
Operation
Q
no change
0
Reset
1
Set
Q
Complement

D Flip-Flop
Q+
Operation
0
Reset
1
Set

S
0
0
1
1

SR Flip-Flop
R
Q+
0
Q
1
0
0
1
1
?

T
0
1

SR Flip-Flop
Q+
Operation
Q
no change
Q
Complement

Operation
no change
Reset
Set
Undefined

Registers with Parallel load

Load

DQ
D0

Q0

DQ
D1

Q1

DQ
D2

Q2

DQ
D3
Clock

Q3

Shift registers

SERIN

CLOCK

SEROUT

Shift registers with parallel load

Used in serial communications applications

Bidirectional shift register with

parallel load
S0
S1

D0

0
1
2
3

D Q

Q0/Sup

0
1
2
3

D Q

Q1

0
1
2
3

D Q

Q2

0
1
2
3

D Q

Q3/SDW

S0
S1

D1
S0
S1

S2
S0
S1

S3

S1
0 0
1 0
2 1
3 1

S2
0
1
0
1

Operation
No change
Shift down
Shift up
Parallel load

Ring Counters

Johnson Counter

Binary Counters

Using Serial Enable logic

Using Parallel Enable logic