The Inverter

References:
Adapted from: Digital Integrated Circuits: A Design
Perspective, J. Rabaey, Prentice Hall UCB
Principles of CMOS VLSI Design: A Systems Perspective,
N. H. E. Weste, K. Eshraghian, Addison Wesley

Regions of Operation
Cutoff

Vgsp > Vtp

Non-saturated
Non
saturated

Saturated

Vgsp < Vtp

Vin < Vtp + VDD

Vgsp = Vtp
Vin < Vtp + VDD

Vdsp > Vgsp - Vtp

Vout > Vin - Vtp

Vdsp < Vgsp - Vtp

Vout < Vin - Vtp

Vggsn > Vtn

Vin > Vtn

Vggsn > Vtn

Vin > Vtn

Vdsn < Vgs - Vtn

Vout < Vin - Vtn

Vdsn > Vgs - Vtn

Vout > Vin - Vtn

p-device
Vin > Vtp + VDD

Vgsn < Vtn

n-device
Vin < Vtn

Digital Gates
Fundamental Parameters

Area and Complexity

Robustness and Reliability
Performance
Power Consumption

Noise in digital Integrated Circuits

unwanted variations of voltages
g and currents at the logic
g nodes

v(t)

VDD

i (t)

(a) Inductive coupling

(b) Capacitive coupling

(c) Power and ground noise

DC Operation:
V lt
Voltage
T
Transfer
f Characteristic
Ch
t i ti (VTC)
Vout
Vout = Vin

VOH

VM

Switching Threshold Voltage

( Transistor Threshold Voltage)

VOL
VOL

VOH

Vin

Nominal Voltage Levels

Mapping between analog and digital signals

V(y)
1

VOH
V1H

VOH

dVout
Slope = -1 = dVin (gain)

Undefined
Region
0

dVout
Slope = -1 = dVin

VIL
VOL

VOL
VIL

VIH

Undefined Region
(Transition width TW)

V(x)

Definitaion of Noise Margins

NMH = VOH VIH

1
1
VOH
NMH

VO
L

0
0
Gate Output
Stage M

NML

VIH
Undefined
Region
VI
L

NML = VIL - VOL

Gate Input
Stage M+1

The Regenerative Property

A chain of inverters

5
V

-1
0

10

Conditions for Regeneration

Vout
V3

Vout
f(v)

finv(v)

f(V0)

V1

V1
V3
fi ( )
finv(v)
f(v)

V2

V0

Vin

(a) Regenerative gate

V0

V2

Vin

(b) Non-regenerative gate

Fan-in and Fan-out

( ) Fan-out
(a)
F
tN

M
N
(b) Fan-in M

The Ideal Gate

Vout

Ri =
Ro = 0

g = -

Vin

VTC of Real Inverter

VDD

5.0

Vout(V)

4.0

NML

3.0
20
2.0

VM

NMH

1.0

0.0

1.0

2.0

Vin (V)

3.0

4.0

5.0

Delayy Definitions
Vin

50%
t

Voutt

tpLH

tpHL

90%
50%
10%
tf

t
tr

Ring Oscillator

V0

V1

V0

V2

V3

V1

T = 2 x tp x N
2Ntp >> tf + tr

V4

V5

V5

Power Dissipation
P(t) = instantaneous power
Ppeak = ipeakVsupply = max (p(t))

1
Pav =
T

p (t )dt =

Vsup ply
T

isup ply (t )dt

Power-Delay Product
PDP = tp x Pav
= Energy dissipated per operation

Static Load MOS Inverters

Static Load MOS Inverters

Rload

Ibias

Vout
Vin

Vout
Vin

Basic Inverter
VDD
Vout
Vin

Vin < Vth ; NMOS off; Vout pulled to VDD

Vin > Vth ; NMOS on, currentt flows
fl
through
th
h R tto
ground
g Vout could be p
pulled down
If R is sufficientlyy large,
well below Vth;

St ti Load
Static
L d MOS IN
INverter
t

Ids

R
Vout

Vout = Vds
Ids.R = VDD-Vds

VTC of Resistive Load

Resistive Load Device

Rload

Voh = 5.0V
Vol = ???

Vout
Vin

I = (Vdd-Vol)/R
I = .((Vdd-Vt)Vol-0.5Vol2)

(Vdd Vol )
R=
.((Vdd Vt )Vol 0.5Vol 2 )

Sizing for VOL

(Vdd Vol )
R=
2
.((Vdd Vt )Vol 0.5Vol )
Assume:

Vdd = 5.0V
Vt = 1.0V
= 10-44A/V

Proper design: Vol < Vt

Let:

Vol = 0.5V
R = 24k

Resistor and Current-Source Loads

R
Resistance/length
i t
/l
th off minimum-width
i i
idth lilines off various
i
connecting elements is far less than effective
resistance of the switched on MOSFET
In some memory processes, resistors are
implemented by highly resistive undoped polysilicon
Normally
N
ll use ttransistors
i t
iin CMOS tto iimplement
l
t
resistor and current-source loads
resistor, called an unsaturated
If biased for use as a resistor
load inverter
If load transistor operates in saturation as a constant
current source, called a saturated load inverter

Pseudo NMOS Inverter

Vout
Vin

VDD + Vdsp = Vout

Vdsp = Vout - VDD
Vdsp = Vout + Vgsp
Vdsp > Vgsp - Vtp or Vout > - Vtp
Non-saturated region

Ln = 1

DC Transfer Characteristics

Pseudo-NMOS Inverter

Vout
Vin

DC current flows when the inverter is turned on unlike

CMOS inverter
CMOS is great for low power unlike this circuit (e.g.
watch needs low power lap-tops etc)
Need to be turned off during IDDQ (VDD Supply
Current Quiescent) testing

PMOST Load with Constant VGS

Voh = 5.0V
Vol = ???
I = 0.5p.(Vdd-Vtp)2
Vout
Vin

I = n.((Vdd-Vtn)Vol-0.5Vol2)

0.5(Vdd Vtp )
n
=
p ((Vdd Vtn )Vol 0.5Vol 2 )
2

Sizing for VOL

0.5(Vdd Vtp )
n
=
p ((Vdd Vtn )Vol 0.5Vol 2 )
2

Assume:

Vdd = 5.0V
Vtn = Vtp = 1.0V

Proper design: Vol < Vth

Let
Let:

Vol = 0.5V
0 5V

n
= 4.266
p

Sizing for Gate Threshold Voltage (Trip Point)

N-device: saturated (Vout >Vin Vtn )

Idsn =

n
2

(Vin Vtn )2

P-device: non-saturated

Vgsp = VDD
I dsp = p [(VDD Vtp )(Vout

(Vout VDD ) 2
VDD )
]
2

Equating the two currents we obtain,

n
2

(Vin Vtn ) = p [(VDD Vtp )(Vout

2

(Vout VDD ) 2
VDD )
]
2

Sizing for Gate Threshold Voltage

Solving for Vout

Vout = Vtp + (VDD + Vtp ) 2 C

Where C = k (Vin - Vtn)2
k=

n
p

n (VDD + Vtpp ) (Vout + Vtpp )

=
p
(Vin Vtn ) 2
2

Also
Also,

To make g
gate threshold voltage
g = 0.5VDD
n
= 6.11
p

Noise Margin

n/p

VIL

VIH

VOL

VOH

2
4
6
8
100

3
3.4
4
1.8
1.4
1
1.1
1
0.5

4
4.5
5
3.3
2.8
2
2.4
4
1.1

1
1.4
4
0.6
0.35
0
0.24
24
0.00

5
5
5
5
5

NML
2
2.0
0
1.2
1.05
0
0.86
86
0.5

NMH
0
0.5
5
2.7
3.2
3
3.6
6
3.9

VTC of Pseudo-NMOS Inverter

Unsaturated Load Inverter

Vout
Vin

High is n threshold down from VDD

Used when depletion mode transistors were not
available
Low noise margin
p transistors
Might be used in I/O structures where p-transistors
were not wanted

VTC of Unsaturated Load Inverters

For k = 4
VOL = 0.24V
VIH = 2.2V
VOH = 3.8V
3 8V
VIL = 0.56V

Current Source Load

Ibias

Vout

Vout
Vin

Vin

Saturated Load Inverter

Vout
Vin

Vout > Vin - Vtn driver transistor in saturation

When Vin is small

Load transistor permanently in saturation

Vdsp = Vgsp
Vdsp < Vgsp - Vtp or 0 < - Vtp Saturated region

When Vin is Small

I ds ,driver =

driver
2

(V in V tn ) 2

Load in saturation:

I ds ,load =

load
2

(V out V DD Vtp ) 2

Equating the currents:

Vout = VDD + Vtp + k (Vin Vtn )

where k =

driven
load

VTC of Saturated Load Inverter

For k = 4
VOL = 0.24V
VIH = 2.1V
VOH = 4
4.4V
4V
VIL = 0.5V

NMOS Inverter
Use depletion mode transistor as pull-up
Vtdep transistor is < 0 V

diffusion

VDD
(poly)

depletion mode transistor

Vout
Vin

enhancement mode
transistor

out
in

The depletion mode transistor is always ON:

gate and source connected Vgs = 0
Vin = 0 transistor pull down is off Vout is high

Vout vs Vin using Graphical Method

Ids (dep)

Ids (enh)
Vgs = 0.0
00
Vgs = -0.2 VDD
Vds (dep) VDD

Ids

Ids

Ids

Vgs (dep) = 0
Vgs (dep)

VDD
Vds (dep)

VDD -Vds(dep) = Vds(enh) = Vout

In a steady state,
Ids of both transistors are equal

VDD - Vds (dep)

Vds (enh) = VDD - Vds (dep)

Vds (enh) = Vout
Therefore Vout = VDD - Vds (dep)

Gate Threshold Voltage

Gate threshold voltage = Vinv
= Input voltage at which Vin = Vout
Assume that both driver and load are in saturation with input Vinv

I DS ( sat ) =

Hence,

driver
2

driver
2

(Vgs Vt ) 2

(Vinv Vt ) =

Vinv = Vt Vdep

load
2

load
driver

If driver is increased relative to load then,

Vinv decreases

(Vdep ) 2
VDD

Vout
Vin

VTC of NMOS inverter

Sl
Slope
|G| iincreases, Vinv decreases
d

increasing

driver
load

CMOS INVERTER

CMOS Inverters

The CMOS Inverter: A First Glance

VD
D

Vin

Vout
CL

Switch Model of MOS Transistor

| VGS
|

| VGS | < | VT |

| VGS | > | VT |

CMOS Inverter: Steady State Response

VDD

VDD

Ron

VOH = VDD
VOL = 0
Vout

VM = f(Ronn, Ronp)

Vin = VDD

Vin = 0

PMOS Load Lines

IDn

Vin = VDD - VGSp

Idn = -IDP
Vout = VDD-V
VDSp

Vout
IDp

Vin = 0

IDn

IDn

Vin = 0

Vin = 3

VDSp

Vin = 3

VDSp

VGSp = -2
VGSp = -5

Vin = VDD + VGSp

IDn = - IDp

Vout = VDD - VDSp

Vout

Construction Of Inverter Curves

Ids

Vds

Construction Of Inverter Curves

Ids

Vds

Construction Of Inverter Curves

Ids

Vds

CMOS Inverter Load Characteristics

In,p
Vin = 0

Vin = 5

PMOS

NMOS

Vin = 1

Vin = 4

Vin = 3
Vin = 4
Vin = 5

Vin = 2
Vin = 3

Vin = 3
Vin = 2

Vin = 2
Vin = 1
Vin = 0

0.0

Vout

5.0

CMOS Inverter VTC

0.0

Vin

5.0

Idnn=Idp=Isuppply

Inverter Supply Current

Small Signal Model for an MOS Transistor

Vsb = 0
voltage-controlled current source (gm)
output conductance (gds)
interelectrode capacitance
Cgd

G
gmVgs

Cgs + Cgb

gds

Cdb

Output Conductance
By differentiating Ids w.r.t. Vds
In linear region
2
I ds = [(Vgs Vt )Vds

Vds
]
2

g ds = [(Vgs Vt ) Vds ]

Rlinear =

1
(Vgs Vt Vds )

In saturation, device behaves like a current source:

the current being almost independent of Vds
d
I ds = [

dI ds
=
dVds

(Vgs Vt ) 2 ]

d[

(Vgs Vt ) 2 ]
dVds

=0

In
I reality,
lit secondary
d
effects
ff t resultlt in
i a slope
l

g ds = I ds

Transconductance
Expresses relationship between output current and
input voltage
gm =

dI ds
| Vds = constant
dVgs

g m (linear
li
) = Vds
g m ( sat.) = (Vgs Vt )

MOS Transistor Small Signal Model

G
+
vgs
-

gmvgs

r0

S
gm

ro

Linear

kVDS

[k(VGS-VT-VDS)]-1

Saturation

k(V
( GS-VT)

1/ID

CMOS Inverter
VDD
s

Vout = VDD - Vsdp

= VDD + Vdsp
Vin = VDD - Vsgp
= VDD + Vgsp

d
d
Vout

Vin
s

Vin = Vgsn, Vout = Vdsn

Regions of Operation
Cutoff

Vgsp > Vtp

Non-saturated
Non
saturated

Saturated

Vgsp < Vtp

Vin < Vtp + VDD

Vgsp = Vtp
Vin < Vtp + VDD

Vdsp > Vgsp - Vtp

Vout > Vin - Vtp

Vdsp < Vgsp - Vtp

Vout < Vin - Vtp

Vggsn > Vtn

Vin > Vtn

Vggsn > Vtn

Vin > Vtn

Vdsn < Vgs - Vtn

Vout < Vin - Vtn

Vdsn > Vgs - Vtn

Vout > Vin - Vtn

p-device
Vin > Vtp + VDD

Vgsn < Vtn

n-device
Vin < Vtn

5.0

Inverter Operating Regions

A: nmost off
pmost linear reg.

Vout

B: nmost saturated
pmostt linear
li
reg.
C: nmost saturated
pmost saturated

0.0

D: nmost linear reg.

pmost saturated

0.0

Vin
i

5.0

E: nmost linear reg.

pmost off
p

Inverter Operating Regions

A: nmost off
pmost linear region
B: nmost saturated
pmostt linear
li
region
i

out

out

outt

out

out

C: nmost saturated
pmost saturated
D: nmost linear region
pmost saturated
E: nmost linear region
pmost off
p

Assume infinite ro
when a device is in saturation

Region A
(0 Vin Vtn)
Idsn = 0 n-device is cut-off
p-device
p
device in linear region

VDD

Idsn = - Idsp = 0, as Idsn = 0

Vdsp = Vout - VDD
With Vdsp = 0, Vout = VDD

Vin

Vout

Region B
VDD
(Vtn Vin
)
2

p-device in non-saturated region (Vds 0)

n-device is in saturation

Idsp
Vin = Vgsn
Idsn

Vout

Region B
I dsn

[Vin Vtn ]2
W
= n
; = n ( n )
2
tox Ln

Vgsp = (Vin - VDD) & Vdsp = (Vout - VDD)

I dsp = p [(Vin VDD Vtp )(Vout

p =

pt W p
tox

Lp

(Vout VDD ) 2
VDD )
]
2

Equating Idsp = -Idsn

Vout = (Vin Vtp ) + (Vin Vtp ) 2 2(Vin

VDD
Vtp )VDD n (Vi n Vtc ) 2
2
p

Region D
(

VDD
< Vin VDD Vtp )
2

p : saturation
n : non-saturated
I dsp
I dsn
I dsp

Idsp

1
= p (Vin VDD Vtp ) 2
2
2
Vout
= n [(Vin Vtn )Vout
]
2
= I dsn

Vout

Idsn

p
= (V inVtn ) (Vin Vtn )
(Vin VDD Vtp ) 2
n
2

Vout

Determining VIH and VIL

R i E
Region
(Vin >= VDD - Vtp)
p: cut-off Idsp = 0
n: linear
li
mode
d
Vgsp = Vin - VDD more p
positive than Vtp
Vout = 0

Region C
(B th devices
(Both
d i
iin S
Saturation)
t ti )
I dsp =
I dsn =

n
2

(Vin VDD Vtp ) 2

(Vin Vtn ) 2

E
Equating
ti Idsp = -IIdsn
VDD + Vtp + Vtn
Vin =

n
1+
p

n
p

Gate Threshold Voltage

If n = p & Vtn = -Vtp

VDD
Vin =
2
Region
g
C exists for one value of Vin
Possible values of Vout in region C
n-channel
p-channel

Vin - Vout < Vtn

Vout > Vin - Vtn
Vin - Vout > Vtp
Vout < Vin - Vtp

saturation conditions

Vin - Vtn < Vout < Vin - Vtp

In reality, region C has a finite slope
- because in reality Ids increases slightly with Vds in saturation

Typical Parameter Values (1m process)

n = 500cm 2 / V sec
= 3.9 8.85 10 14 F / cm
tox = 200A

n =

W
tox

500 3.9 8.85 10 14 W

=
.2 10 5
L
W
= 88.5 A / V 2
L

p 180cm 2 / V sec
p = 31.9

n
= 2.8
p

W
A / V 2
L

(The ratio varies from 2-3)

n/
p Ratio

n
increasing
g
p

Vout

Vin

Wn
increasing W p
Vout

Vin

Effect of n/
p Ratio
n
p

Vm dependent on
n
with change in p transition still remains sharp and hence
switching performance does not deteriorate
It is desirable to have

n
=1
p

allows capacitance load to change and discharge in equal

times by providing equal current source & sink capability

Gate Switching Threshold

4.0

VM

3.0

2.0

1.00.1

VM =

0.3

1.0
kp/kn

r (VDD + Vtp ) + Vtn

r +1

3.2

p
with r =
n

10.0

Effect of Temperature
p
Temperature similarly affects mobility of holes and
electrons
l t
Temperature increases decreases
decreases

T 1.5

Ratio n/p is independent of temperature to a good

approximation
Temperature, however, reduces threshold voltages
Extent of region A reduces and extent of region E
increases
VTC shifts to the left as the temperature increases

Switching Characteristics
Switching speed - limited by time taken to charge and
discharge, CL
Rise
Ri titime, tr : waveform
f
to
t rise
i from
f
10% tto 90% off itits
steady state value
Fall time, tf : 90% to 10% of steady state value
Delay time, td : time difference between input
transition (50%) and 50% output level

CMOS Inverter: Transient Response

p
VDD
tpHL = f(RonCL)
= 0.69 RonCL
Vout

CL
Ron

1 VDD

0.5
0.36

Vin = VDD

RonCL

CMOS
C
OS Inverter
e te Propagation
opagat o Delay
e ay
VDD

t pHL =

Vout
CL

Iav

Vin = VDD

C LVswing
/2
i
I av

I (Vout = VDD ) + I (Vout = VDD / 2)

I av =
2
2
n 7VDD
Vtn2 3VDDVtn

=
+

2 8
2
2

Inverter Propagation Delay

Assume n-device still in saturation at Vout = VDD/2
I av =

t pHL =

(VDD Vtn ) 2

C LVDD
n (VDD Vtn ) 2

CL

nVDD
t pLH
LH

CL

pVDD

C
tp L
2VDD

p n

Analysis of Fall Time

VDD
Vin(t)

Vout(t)
CL

x2
2

non-saturated

saturated
(Vds = Vgs - Vt)

Ids

x1
x3

Vout (t)

VDD

Application of step
input

Components of Fall Time

tf = tf1 + tf2

Vout drops from Vdd - Vt to 0.1 VDD

Vout drops from 0.9Vdd to Vdd - Vt

0.9 VDD
VDD - Vt
0.1 VDD
Vout

Vin
tf

Fall Time for Saturated Region

P

Saturated, Vout VDD - Vtn

Ic

Input rising

dVout n
CL
+
(VDD Vtn ) 2 = 0
dt
2

Idsn

Vout
CL

Integrating from t = t1 (corresponding to Vout = 0.9 VDD) to t = t2

(
(corresponding
di tto Vout = (VDD - Vtn))

CL
tf1 = 2
n (VDD Vtn ) 2

0.9VDD

VDD Vtn

2C L (Vtn 0.1VDD )
=
n (VDD Vtn ) 2

dVout

Fall Time for Non-Saturated Region

p
Vout
n

CL

Non-saturated : 0 Vout VDD - Vtn

dVout
V 2 out
CL
+ n [(VDD Vtn ).Vout
]=0
dt
2
0.1VDD
dVout
CL
tf2 =
V 2 out
n (VDD Vtn ) VDD Vtn
Voutt
2(VDD Vtn )

Fall Time for Non-Saturated Region

tf2 =

CL

dVout

0.1VDD

n (VDD Vtn ) V

DD Vtn

V 2 out
Vout
2(VDD Vtn )

19VDD 20Vtn
=
ln(
)
n (VDD Vtn )
VDD
CL

CL
=
ln(19 20n)
nVDD (1 n)
where n =

Vtn
VDD

Fall Time Computation

tf = tf1 + tf 2
(n 0.1) 1

CL
+ ln(19 20n)
=2

nVDD (1 n) (1 n) 2

tf k

CL
nVDD

k = 3 ~ 4 for
f VDD = 3 ~ 5V andd Vtn = 0.5 ~ 1V

Rise Time
( p 0.1) 1

CL
+ ln(19 20 p )
tr = 2

pVDD (1 p) (1 p) 2

with p =

| Vtp |
VDD

CL
tr k
pVDD
For equally sized n- and p transistors
n 2p

tr
tf
2

Sizing
g for Identical Rise/Fall Time

For same tf and tr

n
=1
p
Increase the width of p-device to

W p 2 3Wn

Delay Time: First Order Approximation

Gate delay is dominated by the output rise and fall
time

tr
t dr =
2
tf
t dff =
2

General Delay Time Computation

Similar to the computation of rise/fall times
Saturation region from t = t1 (corresponding to Vout = VDD) to t
= t2 (corresponding to Vout = (VDD - Vtn))
Linear region from t = t2 (corresponding to Vout = (VDD - Vtn))
to t = t3

CL
t 2 t1 = 2
n (VDD Vtn ) 2

2C L (Vtn )
=
n (VDD Vtn ) 2

VDD

VDD Vtn

dVout

Delay Time Computation

t3 t 2 =

CL

'
dVout

Vout

n (VDD Vtn ) V

DD Vtn

'2
Vout
'
Vout
2(VDD Vtn )

2VDD 2Vtn Vout

=
ln(
)
n (VDD Vtn )
Vout
CL

2(1 n) VO
CL
=
ln(
)
nVDD (1 n)
VO
where

Vtn
Vout
n=
, VO =
VDD
VDD

Delay Time

t Dn

CL
= t3 t1 = An
nVDD

Delay CL (optimize CL to decrease delay)

1
(decrease VDD increases delay)
VDD
1
(if W or L ,
delay decreases)

Three major parameters for optimizing speed of CMOS

Components of CL

Cw = wiring capacitance
Cg = gate capacitance = CoxWL

Miller Effect

Effective voltage change over the gate-drain

capacitor is actually twice the output voltage swing
Contribution of gate-drain capacitor should be
counted twice

Junction Capacitance
p
Non-linear capacitor modeled by linear capacitor with
the same change in charge for the voltage range of
interest
Ceq = K eq C j 0
0m
K eq =
(0 Vhigh )1 m (0 Vlow )1 m
(Vhigh Vlow )(1 m)

Linearize over the interval {5V, 2.5V} for the high-tolow transition and {0, 2.5V} for the low-to-high
low to high
transition
Correspond to {Vhigh=-5V, Vlow=-2.5V} and {Vhigh=0,
Vlow=-2.5V}
2 5V} ffor NMOS

Delay in function of VDD

Sizing
S
go
of Inverter
e te Loaded
oaded by a
an Identical
de t ca Gate

Load cap.
p of first g
gate:
CL = (Cdp1 + Cdn1) + (Cgp2 + Cgn2) + CW
where
Cdp1
p , Cdn1 diffusion capacitance of first gate
Cgp2, Cgn2 gate capacitance of second gate
Cw wiring capacitance
If PMOS devices
d i
are times
ti
llarger th
than th
the NMOS ones,

(W / L) p
(W / L) n

all transistor capacitances will scale in approximately the same way

Sizing of Inverter
Cdp1 Cdn1
C gp 2 C gn 2
C L = (1 + )(Cdn1 + C gn 2 ) +Cw
tp =

tr + t f
2

C L An Ap
=
( +
)
2VDD n p
Ap n
CL
=
( An +
)
2VDD . n
p
Ap n (W / L) n
CL
( An +
.
=
)
2VDD . n
p (W / L) p
Ap n
CL
=
( An +
)
2VDD . n
p

Sizing of Inverter
Ap n
CL
( An +
)
tp =
2VDD . n
p
(1 + )(Cdn1 + C gn 2 ) + CW

Let

2VDD . n

t p

( An +

Ap n

p .

= 0 to get optimal

opt

n Ap
CW
(1 +
)
=
p An
Cdn1 +C gn 2

If CW << Cdn1 + Cgn2, Ap = An

opt

1.73
p

Contrast
C
t t to
t 3 which
hi h iis normally
ll used
d
in the non-cascaded case

Impact of Rise Time on Delay

t PHL (actual ) = t 2 pHL ( step) +(t r / 2) 2

Minimum-size inverter with fanout of a single gate

Velocity Saturation

Under long channel model, saturation current VDD2

In small-geometry devices, this no longer holds: Iav VDD
Therefore, for VDD >> VT we have,

CL 1 1
tp
( + )
2 k p kn

k n , p = vSAT CoxWn , p

Running velocity saturated devices

at high VDD is not beneficial
f
Lowering VDD below 2VT sharply
increases delay

Source/Drain Resistance
In small-geometry devices, source and drain
resistance affects switching currents
Source of the transistor is no longer grounded
grounded, body effect
increases threshold voltage
Vgs is also reduced
Current is reduced

Power Consumption
Static Power
Leakage current
Sub-threshold
Sub threshold conductance

Dynamic Power
Capacitive
p
Power due to charging/discharging
g g
g g of capacitive
p
load
Short-circuit power due to direct path currents when there is
a temporary
p
y connection between p
power and g
ground

Static Power Consumption

VDD

VDD
Vout = VDD
Diode leakage

I O = is ( e

Vq / kT

Sub-threshold current

ID = K e

(V gs Vt ) q / nkT
kT

Pstatic = Ileakage. VDD

(1 e

Vds q / kT

1)

Static Consumption
p
Leakage current through the reverse biased diode
junctions
For typical devices it is between 0.1nA - 0.5nA at
room temperature
For a die with 1 million devices operated at 5 V
V, this
results in 0.5mW power consumption not much
g current is caused by
y thermally
y
Junction leakage
generated carriers -> therefore is a strong function of
temperature
More
M
i
important
t t is
i sub-threshold
b th h ld lleakage
k
when
h
threshold voltage is close to 0

Dynamic Consumption due to CL

VDD

Vout

- low-to-high
l
hi h transition
ii
- Assume 0 rise and fall times

Dynamic Power due to CL

Vout
VDD
t
in

iVDD

CL

discharge
charge

Define:
EVDD : energy taken
t k from
f
supply
l during
d i a ttransition
iti
EC: energy stored on capacitor at the end of transition

Energy Consumed and Stored

EVDD = iVDD (t )VDD dt = VDD

VDD

= C LVDD

dVout
.dt
CL
dt

dVout

= C LVDD (= QVDD )
2

EC = iVDD (t )Vout dt =
VDD

= C LVDD

C L .VDD
=
2

dVout
CL
Vout dt
dt

Vout dVout

Half the energy is stored in Capacitor ! Other half is dissipated in

the PMOS transistor !!
For each switching cycle ( L H & H L), amount of energy
dissipated in CL. VDD2

Pdynamic = CL.VDD2.f

Example

1.2 CMOS chip

100 MHz clock rate
Average load capacitance of 30 fF/gate
5V power supply

Power consumption/gate = 75 W
Design with 200,000 gates: 15W !
Pessimistic evaluation: not all gates switch at the full rate
H
Have
tto consider
id the
th activity
ti it ffactor
t : Effective
Eff ti switching
it hi
capacitance = CL
Reducing VDD has a quadratic effect on Pdynamic

Direct Path Current

inputs have finite rise and fall times
Direct current path from VDD to GND while PMOS and
NMOS are ON simultaneously for a short period
Psc = Imean.VDD
VDD + Vtp

tr

tf

Vtn
T

Imax
Imean
t1 t2 t3

Symmetrical Inverter Without Load

I mean

1
= 2
T

t2

t1

1 t3

I (t )dt + I (t )dt
T t2

If Vtn = -Vtp=VT and n = p =

and that the behavior around t2 is symmetrical

I mean
with

2 t2
= 2
(Vin (t ) Vt ) 2 dt
T t1 2
Vin (t ) =

VDD
t
tr

Vt
.t r
t1 =
VDD
tr
2
t r = t f = t rf

t2 =

Symmetrical Inverter Without Load

I mean

2
=
T
2
=
T
=

2t rf

t rf

Psc =

VDD
2
(

V
)
t dt
trf VT /VDD trf
t rf / 2

t rf / 2

t rf VDD

3
(
t Vt )

3VDD t rf
trf VT / VDD

3T VDD

12T VDD

12

VDD
(
Vt ) 3
2
(VDD 2Vt ) 3

(VDD 2Vt )

3 rf

Short Circuit Current with Loads

Output Transitions under Different Loads

CL Power vs. SC Power under Different Loads

CL Power vs. SC Power under Different Inputs

Impact
p
of Load Capacitance
p
on SC Current
Large capacitance
Fast input transition, slow output transition
Input moves through the transient region before output
begins
g
to change
g
Short-circuit current close to zero

Small capacitance
Relatively slower input transition, fast output transition
Both devices in saturation during most of the transition
Maximum short-circuit current

[Veendrick84]: rise/fall times of all signals should be

kept constant within a range to keep SC power
minimal 10%~20% of total dynamic power
minimal,

Technology Evolution

Technology Scaling (1)

Minimum Feature Size

Technology Scaling
108
107
mosfet

Compo
onents/Chip
p

106

bipolar
transistor

105
104

mesfet
103
102
101
1

bipolar
Transistor

enhancement
mosfet

1950

IC
1960
1970
YEAR

1980

Number of components per chip

1990

Propagation
p g
Delay
y Scaling
g
1n

Gatte Delay: DDd(sec/stage

e)

500p

F/O = 1
R.T. Operation

Ref.[4]
3.5V

200p

Ref.[5]
3.5V

100p

3.3V

2.5V
Ref.[7]

50p

Present Results
Reported Results

2.5V
VDD
Scaling

20p
10p
0.1

05
0.5

VDD=5V

10
1.0

Channel Length : Left (m)

50
5.0

10 0
10.0

Technology Scaling Models

Full Scaling (Constant Electrical Field)

ideal model dimensions and voltage scale
together by the same factor S

Fixed Voltage Scaling

most common model until recently
only dimensions scale, voltages remain constant

General Scaling
most realistic for todays situation
voltages and dimensions scale with different factors

Scaling Relationships for Long channel Devices

Scaling of Short Channel Devices

Homework Problem (due next Thursday)

Design a static CMOS inverter with 0.4pF load capacitance. Make sure
that you have equal rise and fall times. Layout the inverter using the
Mentor tools, extract parasitics, and simulate the extracted circuit on
HSPICE tto make
k sure th
thatt your d
design
i conforms
f
tto th
the specification.
ifi ti
Do the same analysis for a three input NAND gate.