RESUME

Trivikrama Rao Ch
Bangalore
Mobile: +91 7204568708 / 9483089798
Email: trivi.4a6@gmail.com
OBJECTIVE
To seek an Analog /RF/Mixed-Signal Design Engineer position emphasizing design and
development for wide variety of Analog Circuits.
PROFILE
3+ years of experience in RF/analog/mixed-signal integrated circuits design, researching analog
engineering techniques and approaches, developing circuit and logic designs, verifying and
validating designs through simulations and tests. Experience in designing blocks including DAC,
VCO, OPAMP, UWB PULSE GENERATOR and also had hands on experience in layout and
Post Silicon Validation.
SKILLS

EDA Tools: Cadence Virtuoso Schematic Editor L &XL, Virtuoso Layout suite, Calibre,
Programming languages: Matlab, Verilog, VHDL, C/C++
Project Tracking Tools: JIRA
Computer Applications: Office, Linux.

RESPONSIBILITIES
Participate in analysis of requirement and specification of the Analog/RF design
block
Implement and verify analog/RF circuits
Collaborate closely with team in exploring new design circuits to meet
specification
Implementation of behavior model of Analog blocks in verilog_AMS
Design and build AMS Testbenches to verify integration of Analog and Digital
blocks
Responsible for layout of the block design and RC extraction
Verify Design with extensive test-cases simulation to show design works across
all corners
Post silicon validation of the designed block after fabrication

 Writing test plans for silicon validation, collobarating with the digital verification
and firmware team and validating the block on chip
Preparing the design book, datasheet and results sheet for the designed block

PROFESSIONAL EXPERIENCE

July 2012-July 2014: Analog/RF IC Design, Redpine Signals.Inc, Hyderabad

DAC DESIGNS:3
Designed 10 bit Digital to Analog Converter using tsmc 0.13m technology
for 160MHz clock rate with power consumption of 6mW
Implemented using Current Steering Mechanism
Differential output was used for high output swing
To reduce the area and the glitch at mid code transitions, RRBS (Random
Rotation based Scheme) was implemented
10 bit binary input was converted to 4R+4R+2C convention and used
thermometric coding for DAC input
Dual cascode configuration was implemented for reducing the glitch at the output
due to feed forward path
Latch was implemented using NAND gates, to synchronise the data with clock
signal
Efficient floor plan for layout was done to reduce the mismatch between unit
current cells, keeping in mind the coupling capacitances between nets of same cell
and adjacent nets
Layout was extracted for RC parasitics using Calibre tool, and used the
pex.netlist for layout simulations
Checked the performance of DAC using bond wire, and used required capacitors
to reduce the effect of bond wire inductance on the circuit
Designed 10 bit Digital to Analog Converter using chrt40lp technology for
40MHz clock rate with power consumption of 1.5mW
Designed 10 bit Digital to Analog Converter using chrt40lp technology for
1MHz clock rate
Implemented using combination of R-2R ladder (2 bits) and Thermometer coded
input bits (4+4)
Designed for variable reference voltage i.e. 1.8-3.6 V
A two stage Differential amplifier was designed and used as a voltage buffer
10 bit binary input was converted to 4R+4R+2C convention and used
thermometric coding for DAC input

 VCO DESIGNS :2
2.9-4.5 GHz VCO using LC tank and cross coupled NMOS/PMOS pairs
2.2-3 GHz VCO using LC tank and cross coupled NMOS/PMOS pairs
Used tsmc 0.13m Technology
Uses both N mode and PN mode
Coarse capacitor bank and Fine capacitor bank tuning was used
Multiple CMOS varactors were used for linearity in Voltage controlled sensitivity
Generated Center Tapped Inductors layout using Velocerf tool for 2.5nH and 750
pH inductors
Generated s-parameter files for the layout of inductors by placing the pins at
required positions
Minimized the parasitic inductance observed in layout efficiently
Layout was extracted for RC parasitics using Assura and checked for EM +IR
violations

POST SILICON VALIDATION

o Obtained VCO tuning curves by sweeping the coarse and fine words in matlab
and the frequency at each step is read back from oscilloscope to system through
automated program
o Obtained Kvco, PPM curves across temperature
o Obtained PLL frequencies at all 2G and 5G WLAN channels
o Obtained power consumption for PLL blocks individually
o Familiar with equipment like Signal Analyser, oscilliscope etc
o Worked on SDIO and USB cards
o Obtained the spurs at 2G and 5G spurs manually and also automated it
o Tested the DAC parameters common mode voltage, DNL & INL, ENOB, current
consumption for the designed DAC

DOCUMENTATION
o Prepared design book, datasheet, test cases excel for post silicon validation for
DAC-160, DAC-40 and AUXDAC

October 2014-Present: Analog Circuit Design Engineer, Analog-Semi, Bangalore

SAR ADC 160 MSPS
Involved in designing clock generation block with trimming, high speed latch by
minimum delay
Reduced comparator offset by following layout symmetry and reducing parasitic

mismatch
Designed Schmitt trigger circuit as a part of delay generation block
Designed a 700ns pulse for start up circuit
July 2011-July 2012 : M.Tech thesis, IIT Kharagpur,IIT Hyderabad
UWB Pulse Generator Design
Designed Tunable UWB Pulse generator in 180nm technology
Designed layout for the same schematic
Extracted RC parasitics for the layout checked the performance of circuit with it
Documented and written a paper about the thesis and got published the paper
International Conference
EDUCATION
M.Tech, Microelectronics and VLSI, IIT Hyderabad, 2010-2012, GPA : 8.96
B.Tech, Electronics and Communication Engineering, Gudlavalleru Engineering College,
JNTU Kakinada, Andhra Pradesh,2005-2009,Percentage:71.6%
Intermediate, MPC, Board of Intermediate Education, Andhra Pradesh, 2003-2005,
Percentage : 94.4%
SSC, Board of Secondary Education, Andhra Pradesh, 2005, Percentage: 84.83%

HONORS & AWARDS

Received Accolades from Project Manager on successful post silicon validation of
designed DAC
Secured All India GATE-2010 percentile 99.17
Presented a Technical paper on Trends in Mobile Communications in Gudlavalleru
Engineering College in 2008 and received 1st prize
Received Merit Scholarship in B.Tech from our college in 2005

PUBLICATIONS
A Tuneable CMOS pulse generator for detecting the cracks in concrete walls, IEEE
conference ISVLSI-2012, Amherst, USA, August 19-21, 2012.