n-well-shallow is better

n-well
n-tub
(for p-device)
Grow SiO2/SiN

Channel-stop implant :
prevent conduction between
unrelated transistor
Grow field oxide
(LOCOS) (birds break)smaller L
adjust threshold voltage

add polysilicon etch

N+ mask
(self-aligned by poly)

Light-Doped Drain (LDD)

P+ mask
(LDD is not required)

Grow SiO2
Etch SiO2
(Define contact cut)

Add metal
(circuit connectivity)

(7~8um)
or SiO2()

Anisotropic etch

Form p-island
(for n-device)

Form n-island
(for p-device)

- Grow gate oxide through

thermal oxidation

- Deposit doped polysilicon

Etch polysilicon

n-implantation for source

& drain (self-alignment)

p-implantation
1. Grow phosphorus glass
2. Etch glass to form contact cut
3. Evaporating alumni

3.3 CMOS process enhancement (Interconnection)

- A CMOS circuit
= CMOS logic process + signal/power/clock-routing layers
- Second-layer of metal (VIA1=M1 to M2)
- Note : M1 must be involved in any contact to underlying

1. Etch
isolation
layer
Contact

2.Form

a VIA

areas (polysilicon , diffusion)

- Process steps for two-metal process ()
3.3.1.2
- Reduce resistor of polysilicon to make long-distance
interconnection
- Combine polysilicon with a refractory metal
(silicon + tantalum)

=20-40

=1-5/square

Make long-distance
(interconnect)

3.3.1.3 Local Interconnection

- Local Interconnection allow a direct connection between
polysilicon and diffusion , alleviating the need for
area-intensive contacts and metal
- Example : use of L.I. in SRAM(save 25%)

3.3.2 Circuit elements

1. Resistor
- Polysilicon (undoped) in static memory cell
- Resistive metal (nichrome) to produce high-value,
high-quality resistors in mixed-mode CMOS circuits
2. Capacitors
Geometry

Process cross
section

- Polysilicon capacitor
- Memory capacitor(3-dimensional to increase cap/area)
Example : 1.Trench capacitor(Fig3.18(a))
2. Fin-type capacitor(Fig3.18(b))
* Advanced CMOS process
1.BiCMOS process
2.Thin-film transistors
3.3-D CMOS

3.4 Layout design rules

- Function : obtain a circuit with optimum yield in an area as
well as possible
- Performance yield

* Conservative design rules functional circuit

good yield
* Aggressive design rules

bad yield
compact circuit/layout

- (A) Line width/spicing

small open circuit
close short circuit
- (B) Spacing between two independent layers
- In process:
(a) Geometric features for mask-making and lithographical
(b) Interactions between different layers(eg.polydiff)
- Rules:
Micro()-based rules Industry(submicron)
Lambda-based rules (In general 1=0.5um)
(4-1.2um process)
- see Table3.1&3.2

C o n t a c t R u l e s : There are several generally available

contacts:
. Metal to p-active (p-diffusion)
. Metal to n-active (n-diffusion)
. Metal to polysilicon
. VDD and VSS substrate contacts
. Split(substrate contacts)

Vertical : pnp
p = source/drain of p device (Emitter)
n = n-well (Base)
p = p-substrate (Collector)
Lateral : npn
n = source/drain of n device (Emitter)
p= p-substrate (Base)
n= n-well (Collector)
Rsubstrate, Rwell
*Parasitic devices and resistors

3.4.5 Layer assignment (Table3.4)

CIF : caltech Intermediate Form
Calma stream format
3.5 Latchup
- Latchup : shorting of VDD and Vss lines chip breakdown
- (watch Fig3.2.9)
- Latchup triggering :
Transient current
Impluse current in start-up
A. Lateral triggering : current flows in the emitter of the
lateral npn-transistor
Trigger point : In, trigger =
Vpnp, on = 0.7V

Vpnp-on
npn

Rwell

npn = common base gain of the lateral npn device

Rwell = well resistance

B. Vertical triggering : sufficient current is injected into the

emitter of the vertical pnp transistor
3 .5.3 Latchup prevention
- Latchup occur
(npn+1)(IR,sub+I R,wellpnp)

npnpnp > 1 +

(IDD-IR,sub)
Where

IR,sub =

VBE,,npn
Rsub

IR,well =

VBE,,npn
Rsub

IDD = total supply current

- Observation to prevent latchup :
1. Reduce the resistor values
2. Reduce the gain of the parasitic devices
- Approach :
1.Latchup-resistant CMOS process
2.Layout techniques
(see section 3.5.4,3.5.5)
3.6 Technology-related CAD tools
- DRC(Design Rule Check) CAD tool ( 3.6.1)
- Circuit extraction
-

CAD tool (3.6.2)

CMOS process simulator (Process Input Description

Language(PIDL))(sec.3.9)