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AbstractThis paper presents a study on techniques for characterization of metaloxidesemiconductor field-effect transistor
(MOSFET) transconductance mismatch, using matched pairs with
intentional 1% dimensional offsets. The relevance of this kind of
work is demonstrated by the introduction of a new mismatch phenomenon that can be attributed to mechanical strain, associated
with metal dummy structures that are required for backend chemical mechanical polishing (CMP) processing steps.
Index TermsMicroelectronic test structure, MOSFET measurement method, systematic parametric mismatch.
I. INTRODUCTION
RANSISTOR size reduction and the continuing evolution toward mixed signal system-on-a-chip solutions
that require integrated high-precision analog small-signal
processing, have considerably intensified the attention for
metaloxidesemiconductor field-effect transistor (MOSFET)
matching in modern complimentary metaloxidesemiconductor (CMOS) technologies [1][7]. Matching, short for
statistical device behavior differences between supposedly
identical components, is usually attributed to random variations
of microscopic physical quantities, like edge roughness, fluctuation of the number of dopant atoms or interface states, etc.
[3], [4]. Usually these stochastic variations are characterized
through the standard deviations of mismatch distributions of
and
the main MOSFET compact model parameters (
). Besides these random fluctuations, several physical
effects are causing so-called systematic mismatch, meaning that
the median (or the average) of the mismatch distribution deviates significantly from zero. Causes for systematic mismatch
observations are for example: photomask offsets, topography
related offsets [5] and local mechanical stress asymmetries [6],
[7]. Although systematic mismatch effects are often relatively
small (from a few percent down to a fraction of a percent),
their impact on the performance of high precision analog
electronic circuits can be quite significant. Applications like
high-resolution A/D and D/A converters (10 bits and higher)
suffer (yield loss) from levels of component inequality down to
as low as the 0.01% range. Apart from the efforts that need to
go into the fabrication of devices with these low mismatches,
=0
= 10 10
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303
Fig. 2. Schematic drawing of CS/CG matched pair test structure layout. The
two drains of each pair are padded out separately.
Fig. 3. Composite photograph of full suite of matched pair test structures. The
set of 45 matched pairs is placed twice on a multiproject chip. (The rest of the
test chip is not shown.)
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304
TABLE I
OFFSET PAIRS: LAYOUT DIMENSIONS
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same gate voltage as its twin in the CS/CG pair. Hence, due to
the voltage offset of the zero volts SMU, a substantial current
(order of pico-Amps or even nano-Amps) will flow through this
transistor, which will add to the main transistor current in the
(common) source connection. This is a fundamental limitation
of this approach. The choice between measuring the two drain
currents (simultaneously) in separate SMUs or measuring them
(sequentially) in the common source SMU depends on the hardware specifications and the calibration accuracy of the available measurement system. In practice we have seen no evidence
of possible systematic mismatch contributions of the described
time-sequential measurement technique. Nevertheless, some alternative techniques are discussed in the discussion section of
this paper.
All transistors of a particular population are measured using
(e.g.,
V,
the same three fixed gate voltages
V and
V, see Fig. 5). This means that
may vary slightly due
the gate overdrive voltages
to the threshold voltage spread across the wafer. In the reported
experiment, the effect of this variation is negligible, as the stanvariation across the wafer was found to
dard deviation of the
devices. The most
be less than 1 mV for these
important criterion for the selection of the three gate voltages
is that the lowest point should at least be located at (or slightly
above) the peak-transconductance point (Fig. 5). This assures
that the transistor operates in the (linear) modeling regime that
is used for the parameter calculations. This is quite similar to
what was suggested by Hamer in [8].
For most studies on MOSFET matching, the system and
method described above proves to be more than adequate.
The short-term repeatability performance for determination of
and current factor mismatch standard deviations (
and
) are typically better than 50 V and 0.02%,
respectively. This is for instance visualized in Fig. 7, which
displays results of measuring the mismatch distribution for
a particular population of (standard) 10/10 pairs two times.
Along the horizontal axes, the individual mismatch observations are depicted as determined initially, whereas the vertical
axes corresponds to the results for exactly the same population
measured approximately one hour later. The correlation speaks
for itself while the scatter gives an impression of the normal
short-term repeatability levels as mentioned above.
IV. RESULTS AND DISCUSSION
The main purpose of the study as reported in this work was
to identify how useful the standard algorithm as discussed in
the previous section is for identification of systematic transconductance mismatch occurrences. As will become clear during
the remainder of this paper, the example of Fig. 1 is in fact
a classical example of a double distribution coming from two
slightly different populations, each with their own systematic
mismatch component. The questions that we were faced with
were: how real are these systematic mismatch observations and
what causes them?
During this study, we came to the conclusion that the main
weakness of the no-switching-matrix measurement approach
described in the previous section lies in the fact that the two
305
transistors of the pair are not biased with exactly identical drain
SMUs. Voltage forcing differences of up to 200 V are not uncommon according to the specifications of the used parameter
analyzer system. When studying subtle systematic mismatch effects, differences of this magnitude can be quite significant, as
the voltage forcing offset propagates linearly into the observed
current factor mismatch. Note that an offset of 200 V on an
intended 100 mV bias would correspond to a 0.2% systematic
current factor mismatch!
For very detailed mismatch studies like the one presented in
this paper, the effects of this systematic SMU voltage difference can be suppressed by measuring the mismatch distributions twice: initially as depicted in Fig. 6, and then the entire
mismatch distribution is remeasured after interchanging the two
drain probe positions, or alternatively by swapping the cables to
SMU3 and SMU4 (the manual cable chaser switch matrix).
consists of
Let us assume that an observed mismatch
associated with the actual
two independent components: a
due to the
mismatch between the devices of the pair and a
measurement system (for instance caused by the voltage source
offset difference suggested above). During the initial measurements of the population of pairs this results into mismatch obserfor each pair:
.
vations
When we interchange the physical connections to the pair we
.
get a second set of observations
As we can safely assume that the devices (and hence their mismatch) have not changed, the observed mismatch of the device (as seen by the measurement system) should reverse sign
, whereas the contribution of the system
itself will remain unchanged (if the voltage offset between the
two SMUs has not changed during the entire double measure. Now it follows that
ment procedure):
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306
1 (solid triangles;
= 00:093% and =
= 0 015
0 01
= 0 17
V. ALGORITHM IMPROVEMENTS
Fig. 9. Cumulative probability plots for current factor mismatch for the three
offset matched pair test structures (#1 reticle position). Estimators: see Table II.
It will be evident that once the main limitations of the original method are pinpointed, several alternative measurement
methods spring to mind. After all, measuring every distribution
twice may be acceptable for an exploratory study, but is not
very practical when many devices are to be characterized.
An example of an alternative method is based on a voltage
transformation scheme combined with SMU ground voltage
offset compensation. This approach is comparable to the one
used for accurate measurements of bipolar junction transistors
as described in [11]. For MOSFETs, this means that instead of
measuring the transistors with the drain at 0.1 V, we ground the
drain for the transistor under test and apply a negative source
voltage. Obviously one has to adapt all other biases for this
approach: i.e., the substrate at 0.1 V while subtracting 0.1 V
from all intended gate biases. Setting its drain bias also to
0.1 can deactivate the transistor of the pair that is supposed
to be inactive. The main advantage of this approach is that
is now also identical for
the secondary driving voltage
both transistors of the pair since it is determined by the forcing
voltage source of SMU2. Likewise to what was reported in
[11], the voltage source inequality problem is now shifted to
the inequality of the zero value (COMMON) of the two drain
SMUs. By placing extra needles on the two drain contact pads
and connecting these with the internal differential voltmeter of
the parameter analyzer (VMU1 and 2), we can monitor (and
compensate for) this offset voltage.
Fig. 10 shows a measured example of the voltage difference
between SMU3 and SMU4 when they are both at COMMON
(both transistors active!). This graph is compiled from offset observations during the mismatch measurements of some 500 pairs
while testing the voltage transformation scheme as sketched
above. As it took several hours to collect these measurements
(this includes the mismatch measurements, aligning the wafer,
adjusting probes etc.) the following conclusions can be drawn
from this figure:
offset voltages of the
1) It is indeed not unlikely that
order of 100 V are the major cause for the systematic
offset that was identified in the previous Section II.
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307
TABLE II
MATCHING AND SYSTEM OFFSET RESULTS FOR OFFSET PAIRS AT #1 POSITION
Fig. 10. Voltage offset between SMU3 and SMU4 during verification of
voltage transformation measurement algorithm (both SMUs grounded).
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308
TABLE III
MATCHING AND SYSTEM OFFSET RESULTS FOR OFFSET PAIRS AT #2 POSITION
Fig. 11. Cumulative probability plots for current factor mismatch for
N-channel (W=L = 2=1) transistors. Estimators: see Table IV.
TABLE IV
MATCHING RESULTS FOR N-CHANNEL W=L = 2=1 PAIRS
chip were investigated. Surprisingly it was found that these systematic differences between the #1 and #2 reticle positions occurred for many pairs. Moreover, some pairs gave significantly
larger differences than others, seemingly without any consistency with respect to their dimensions and respective reticle
positions. A rather spectacular example of the systematic mismatch difference between the two reticle positions for n-channel
[ m/ m] pairs is shown in Fig. 11.
The statistical estimators for the two current factor mismatch
distributions from Fig. 11 are summarized in Table IV. The
values between brackets again represent the statistical uncertainties due to the fairly limited sample size and were again
estimated using the bootstrap technique.
These data were obtained using the original matching characterization algorithm without second measurement and interchanging SMU3 and SMU4. As pointed out before, a systematic mismatch of about 0.1% can be attributed to the offset of
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309
Note for instance the (dark grey) Metal-1 dummy placement difference between the transistors when comparing Fig. 4 (10/10
transistors) and Fig. 12 (2/1 transistors). However, apparently
the origin point is not the same for each mask layer and dummy
pattern, for the used dummy placement algorithm, which in this
case results in slightly different Metal-2 dummy patterns for the
two reticle positions.
As mentioned before, the process family that was used to fabricate these devices has in the past given matching problems due
to incomplete H passivation as well as mechanical stress offsets
when transistors are covered with metal plates [6]. To avoid possible problems, dummy tiles were removed (manually) where
they coincided with a transistor. These seemingly arbitrary removals were intended to at least open-up paths for hydrogen to
diffuse toward the transistors. Unfortunately (or perhaps fortunately!), this last-minute manual removal action resulted in a
significant environmental asymmetry between the two transistors of the pairs. The asymmetries, resulting from these last
minute CMP dummy removals were recognized as they were
created, be it that the extend of their impact came as an interesting surprise .
We demonstrated before in [6] that metal coverage can result in significant matched pair asymmetries due to asymmetry
of the (local) mechanical strain that can be caused by strained
(ILD dielectric or Tungsten first metal) layers from the back-end
process. Strain differences translate into mobility differences
(and hence transconductance differences) through the piezo-resistance effect in silicon [6], [12]. That the systematic current
factor mismatch difference between the #1 and #2 reticle positions is due to mechanical strain was verified by checking the
distributions of the threshold voltage mismatch of these two
populations. As no significant difference could be distinguished
between the threshold voltage distributions, we felt quite safe to
conclude that we were indeed looking at a mobility related mismatch effect, although strictly speaking we realize that a complete proof of this conclusion is not given here. Further tests
involving extensive back-end experiments and device (or substrate) orientation variations would be required to prove this.
Now let us go back to the much smaller, but nevertheless statistically significant, median differences between Tables II and
III. Careful scrutiny of the 10/10 offset pair test structures indeed reveals similar CMP dummy coverage asymmetries, be it
less blatant than in the example of Figs. 11 and 12.
The careful reader of this paper will now understand the path
that this investigation followed. It was the initial histogram of
Fig. 1, composed of the combined populations of the #1 and #2
reticle positions, that initiated this work. The question whether
the observed systematic mismatch component that was observed
in Fig. 1 was due to the measurement algorithm or caused by
the process should be answered by: Both: We had to refine the
measurement method to get rid of measurement system induced
systematic mismatches of the order of a few tenths of a percent,
but after this we had to conclude that an unexpected mechanical strain related effect caused the major part of the observed
systematic mismatches. This work demonstrates that it is worthwhile to improve mismatch measurement algorithms to an accuracy level well below 0.1%. New mismatch effects are encountered at these levels, which may originally seem small, but can
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310
Hans P. Tuinhout received the M.Sc. degree in electrical engineering from the Delft University of Technology, Delft, The Netherlands, in 1980.
Since then, he worked for the Philips Research
Laboratories, Eindhoven, The Netherlands, on
CMOS and BiCMOS process and device characterization. His current research activities in the device
modeling group at Philips Research are focused on
accurate dc parametric measurements, in particular
for characterizing statistical differences between
supposedly identical (matched) IC components and
looking for techniques to interpret stochastic mismatch effects to improve performance and yield of digital and mixed signal integrated circuit technologies.
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