Escolar Documentos
Profissional Documentos
Cultura Documentos
CY7C68015A, CY7C68016A
Features
Errata: For information on silicon errata, see Errata on page 67. Details include trigger conditions, devices affected, and proposed workaround.
408-943-2600
Revised January 15, 2015
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right device for your design, and to help you to quickly
and effectively integrate the device into your design. For a comprehensive list of resources, see the application note AN65209 - Getting
Started with FX2LP.
Application notes: Cypress offers a large number of USB application notes covering a broad range of topics, from basic to
advanced level. Recommended application notes for getting
started with FX2LP are:
AN65209 - Getting Started with FX2LP
AN15456 - Guide to Successful EZ-USB FX2LP and
EZ-USB FX1 Hardware Design and Debug
AN50963 - EZ-USB FX1/FX2LP Boot Options
AN66806 - EZ-USB FX2LP GPIF Design Guide
AN61345 - Implementing an FX2LP- FPGA Interface
AN57322 - Interfacing SRAM with FX2LP over GPIF
AN4053 - Streaming Data through Isochronous/Bulk Endpoints on EZ-USB FX2 and EZUSB FX2LP
AN63787 - EZ-USB FX2LP GPIF and Slave FIFO Configuration Examples using 8-bit Asynchronous Interface
For complete list of Application notes, click here.
Code Examples:
USB Hi-Speed
Reference Designs:
CY4661 - External USB Hard Disk Drives (HDD) with Fingerprint Authentication Security
FX2LP DMB-T/H TV Dongle reference design
Models: IBIS
GPIF Designer
FX2LP General Programmable Interface (GPIF) provides an
independent hardware unit, which creates the data and control
signals required by an external interface. FX2LP GPIF Designer
allows users to create and modify GPIF waveform descriptors for
EZ-USB FX2/ FX2LP family of chips using a graphical user
interface. Extensive discussion of general GPIF discussion and
programming using GPIF Designer is included in FX2LP
Technical Reference Manual and GPIF Designer User Guide,
distributed with GPIF Designer. AN66806 - Getting Started with
EZ-USB FX2LP GPIF can be a good starting point.
Page 2 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
24 MHz
Ext. XTAL
x20
PLL
/0.5
/1.0
/2.0
Data (8)
I2C
8051 Core
12/24/48 MHz,
four clocks/cycle
Master
VCC
Address (16)
FX2LP
1.5k
connected for
full speed
D+
D
USB
2.0
XCVR
Integrated
full speed and
high speed
XCVR
CY
Smart
USB
1.1/2.0
Engine
16 KB
RAM
Soft Configuration
Easy firmware changes
RDY (6)
CTL (6)
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, etc.
8/16
Up to 96 MBytes/s
burst rate
ADDR (9)
GPIF
ECC
4 kB
FIFO
Abundant I/O
including two USARTs
The FX2LP draws less current than the FX2 (CY7C68013), has
double the on-chip code/data RAM, and is fit, form, and function
compatible with the 56-, 100-, and 128-pin FX2.
Page 3 of 71
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CY7C68015A, CY7C68016A
Contents
Applications ...................................................................... 5
Functional Overview ........................................................ 5
USB Signaling Speed .................................................. 5
8051 Microprocessor ................................................... 5
I2C Bus ........................................................................ 5
Buses .......................................................................... 5
USB Boot Methods ...................................................... 6
ReNumeration ............................................................. 6
Bus-Powered Applications .......................................... 6
Interrupt System .......................................................... 6
Reset and Wakeup ...................................................... 9
Program/Data RAM ................................................... 10
Register Addresses ................................................... 11
Endpoint RAM ........................................................... 12
External FIFO Interface ............................................. 13
GPIF .......................................................................... 14
ECC Generation[8] ..................................................... 14
USB Uploads and Downloads ................................... 14
Autopointer Access ................................................... 14
I2C Controller ............................................................. 15
Compatible with Previous Generation
EZ-USB FX2 .............................................................. 15
CY7C68013A/14A and CY7C68015A/16A
Differences ................................................................ 15
Pin Assignments ............................................................ 16
CY7C68013A/15A Pin Descriptions .......................... 23
Register Summary .......................................................... 31
Absolute Maximum Ratings .......................................... 39
Operating Conditions ..................................................... 39
Thermal Characteristics ................................................. 39
DC Characteristics ......................................................... 40
USB Transceiver ....................................................... 40
Page 4 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
1. Applications
MPEG/TV conversion
DSL modems
ATA interface
Cameras
Scanners
Wireless LAN
MP3 players
Networking
2.2.2 USARTs
C1
24 MHz
12 pF
C2
12 pF
20 PLL
2. Functional Overview
2.1 USB Signaling Speed
Parallel resonant
Fundamental mode
2.4 Buses
Note
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a 1 for UART0, UART1, or both respectively.
Page 5 of 71
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CY7C68015A, CY7C68016A
8x
IOA
SP
9x
IOB
EXIF
Ax
IOC
INT2CLR
Bx
IOD
IOE
Cx
SCON1
SBUF1
Dx
PSW
Ex
ACC
Fx
B
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DPL0
DPH0
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
MPAGE
SCON0
SBUF0
AUTOPTRH1
AUTOPTRL1
reserved
AUTOPTRH2
AUTOPTRL2
reserved
INT4CLR
IE
EP2468STAT
EP24FIFOFLGS
EP68FIFOFLGS
AUTOPTRSET-UP
OEA
OEB
OEC
OED
OEE
IP
EP01STAT
GPIFTRIG
T2CON
RCAP2L
RCAP2H
TL2
TH2
EICON
EIE
EIP
Default VID/PID/DID
0x04B4 Cypress Semiconductor
0x8613 EZ-USB FX2LP
0xAnnn Depends on chip revision
(nnn = chip revision where first
silicon = 001)
2.6 ReNumeration
Because the FX2LPs configuration is soft, one chip can take on
the identities of multiple distinct USB devices.
When first plugged into USB, the FX2LP enumerates
automatically and downloads firmware and USB descriptor
tables over the USB cable. Next, the FX2LP enumerates again,
this time as a device defined by the downloaded information.
This patented two step process called ReNumeration happens
instantly when the device is plugged in, without a hint that the
initial download step has occurred.
GPIFSGLDATH
GPIFSGLDATLX
GPIFSGLDATLNOX
Two control bits in the USBCS (USB Control and Status) register
control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate whether the firmware or the Default USB Device
handles device requests over endpoint zero: if RENUM = 0, the
Default USB Device handles device requests; if RENUM = 1, the
firmware services the requests.
Note
2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
Page 6 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
INT2VEC Value
00
Source
SUDAV
Notes
Setup data available
04
SOF
08
SUTOK
0C
SUSPEND
10
USB RESET
Bus reset
14
HISPEED
18
EP0ACK
1C
20
EP0-IN
10
24
EP0-OUT
11
28
EP1-IN
12
2C
EP1-OUT
13
30
EP2
14
34
EP4
15
38
EP6
16
3C
EP8
17
40
IBN
EP0PING
reserved
18
44
19
48
reserved
20
4C
EP1PING
21
50
EP2PING
22
54
EP4PING
23
58
EP6PING
24
5C
EP8PING
25
60
ERRLIMIT
26
64
27
68
Reserved
28
6C
Reserved
29
70
EP2ISOERR
30
74
EP4ISOERR
31
78
EP6ISOERR
32
7C
EP8ISOERR
If Autovectoring is enabled (AV2EN = 1 in the INTSET-UP register), the FX2LP substitutes its INT2VEC byte. Therefore, if the high
byte (page) of a jump table address is preloaded at the location 0x0044, the automatically inserted INT2VEC byte at 0x0045 directs
the jump to the correct address out of the 27 addresses within the page.
2.8.3 FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual USB interrupt sources, the FIFO/GPIF interrupt is shared among 14 individual
FIFO/GPIF sources. The FIFO/GPIF Interrupt, similar to the USB Interrupt, can employ autovectoring. Table 4 on page 8 shows the
priority and INT4VEC values for the 14 FIFO/GPIF interrupt sources.
Page 7 of 71
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CY7C68015A, CY7C68016A
INT4VEC Value
Source
80
EP2PF
Notes
Endpoint 2 programmable flag
84
EP4PF
88
EP6PF
8C
EP8PF
90
EP2EF
94
EP4EF
98
EP6EF
9C
EP8EF
A0
EP2FF
10
A4
EP4FF
11
A8
EP6FF
12
AC
EP8FF
13
B0
GPIFDONE
14
B4
GPIFWF
addresses within the page. When the ISR occurs, the FX2LP
pushes the program counter to its stack then jumps to address
0x0053, where it expects to find a jump instruction to the ISR
Interrupt service routine.
Note
3. Errata: In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT Endpoint (EP) in the first
transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than one word in the first transaction. For more information, see
the Errata on page 67.
Page 8 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
RESET#
RESET#
VIL
VIL
3.3V
3.0V
3.3V
VCC
VCC
0V
0V
TRESET
TRESET
Power on Reset
Powered Reset
TRESET
5 ms
USB bus activity (if D+/D lines are left floating, noise on these
lines may indicate activity to the FX2LP and initiate a wakeup)
Powered reset
200 s
The 8051 puts itself and the rest of the chip into a power-down
mode by setting PCON.0 = 1. This stops the oscillator and PLL.
When WAKEUP is asserted by external logic, the oscillator
restarts after the PLL stabilizes, and the 8051 receives a wakeup
Note
4. If the external clock is powered at the same time as the CY7C680xxA and has a stabilization wait period, it must be added to the 200 s.
Page 9 of 71
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CY7C68015A, CY7C68016A
USB download
USB upload
Inside FX2LP
Outside FX2LP
FFFF
7.5 KB
USB regs and
4K FIFO buffers
(RD#,WR#)
E200
E1FF 0.5 KB RAM
E000 Data (RD#,WR#)*
(OK to populate
data memory
hereRD#/WR#
strobes are not
active)
40 KB
External
Data
Memory
(RD#,WR#)
48 KB
External
Code
Memory
(PSEN#)
3FFF
16 KB RAM
Code and Data
(PSEN#,RD#,WR#)*
(Ok to populate
data memory
hereRD#/WR#
strobes are not
active)
(OK to populate
program
memory here
PSEN# strobe
is not active)
0000
Data
Code
Page 10 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Inside FX2LP
Outside FX2LP
FFFF
7.5 KB
USB regs and
4K FIFO buffers
(RD#,WR#)
E200
E1FF
0.5 KB RAM
E000 Data (RD#,WR#)*
(OK to populate
data memory
hereRD#/WR#
strobes are not
active)
40 KB
External
Data
Memory
(RD#,WR#)
64 KB
External
Code
Memory
(PSEN#)
3FFF
(Ok to populate
data memory
hereRD#/WR#
strobes are not
active)
16 KB
RAM
Data
(RD#,WR#)*
0000
Data
Code
F000
EFFF
2 KB RESERVED
E800
E7FF
E7C0
E7BF
E780
E77F
E740
E73F
E700
E6FF
E500
E4FF
E480
E47F
E400
E3FF
E200
E1FF
64 BEP1IN
64 Bytes EP1OUT
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
(512)
Reserved (128)
128 Bytes GPIF Waveforms
Reserved (512)
512 Bytes
8051 xdata RAM
E000
Page 11 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
2.12.1 Size
3 64 bytes
(Endpoints 0 and 1)
8 512 bytes
(Endpoints 2, 4, 6, 8)
2.12.2 Organization
EP0
EP1IN, EP1OUT
EP2, 4, 6, 8
64
64
64
64
64
64
64
64
64
64
64
64
EP1 IN
64
64
64
64
64
64
64
64
64
64
64
64
EP1 OUT
64
64
64
64
64
64
64
64
64
64
64
64
EP2
EP2
EP2
EP2
EP2
EP2
EP2
EP2
EP2
EP2
512
512
512
512
512
512
512
512
512
512
512
512
EP4
EP4
512
512
512
512
512
512
512
512
512
512
512
512
EP6
EP6
EP6
EP6
EP6
EP6
512
512
512
512
512
512
512
1024
EP8
512
1024
512
512
1024
1024
1024
512
512
1024
1024
1024
1024
1024
512
512
512
1024
EP6
1024
1024
512
EP6
EP6
512
512
512
512
EP6
512
1024
512
EP8
EP8
512
1024
512
EP4
512
EP2 EP2
512
512
512
512
512
1024
1024
1024
EP8
EP8
512
512
512
512
10
11
1024
1024
12
Page 12 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
ep0
64
64
64
64
ep1out
64 bulk
64 int
64 int
ep1in
64 bulk
64 int
64 int
ep2
ep4
ep6
64 bulk in (2)
64 int in (2)
64 iso in (2)
ep8
64 bulk in (2)
64 bulk in (2)
64 bulk in (2)
ep0
64
64
64
64
ep1out
512 bulk[7]
64 int
64 int
ep1in
512
bulk[7]
64 int
64 int
ep2
ep4
ep6
ep8
Notes
5. 0 means not implemented.
6. 2 means double buffered.
7. Even though these buffers are 64 bytes, they are reported as 512 for USB 2.0 compliance. The user must never transfer packets larger than 64 bytes to EP1.
Page 13 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
2.14 GPIF
ECCM = 0
The ECC can correct any one-bit error or detect any two-bit error.
2.15.1 ECC Implementation
The two ECC configurations are selected by the ECCM bit:
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 256 bytes of data
is calculated and stored in ECC1. The ECC for the next 256 bytes
is stored in ECC2. After the second ECC is calculated, the values
in the ECCx registers do not change until ECCRESET is written
again, even if more data is subsequently passed across the
interface.
ECCM = 1
One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCRESET then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 512 bytes of data
is calculated and stored in ECC1; ECC2 is unused. After the
ECC is calculated, the values in ECC1 do not change even if
more data is subsequently passed across the interface, till
ECCRESET is written again.
Notes
8. To use the ECC logic, the GPIF or Slave FIFO interface must be configured for byte-wide operation.
9. After the data is downloaded from the host, a loader can execute from internal RAM to transfer downloaded data to external memory.
Page 14 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
2.18 I2C Controller
2
Example EEPROM
A2
A1
A0
16
24LC00[10]
N/A
N/A
N/A
128
24LC01
256
24LC02
4K
24LC32
8K
24LC64
16K
24LC128
EZ-USB FX2
Part Number
CY7C68013-56PVC
EZ-USB FX2LP
Part Number
Package
Description
CY7C68013A-56PVXC or 56-pin
CY7C68014A-56PVXC
SSOP
CY7C68013-100AC
CY7C68013A-100AXC or 100-pin
CY7C68014A-100AXC
TQFP
CY7C68013-128AC
CY7C68013A-128AXC or 128-pin
CY7C68014A-128AXC
TQFP
The 8051 can control peripherals connected to the I2C bus using
the I2CTL and I2DAT registers. FX2LP provides I2C master
control only; it is never an I2C slave.
CY7C68015A/CY7C68016A
IFCLK
PE0
CLKOUT
PE1
Note
10. This EEPROM does not have address pins.
Page 15 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
3. Pin Assignments
Figure 3-1 on page 17 identifies all signals for the five package
types. The following pages illustrate the individual pin diagrams,
plus a combination diagram showing which of the full set of
signals are available in the 128-pin, 100-pin, and 56-pin
packages.
The signals on the left edge of the 56-pin package in Figure 3-1
on page 17 are common to all versions in the FX2LP family with
the noted differences between the CY7C68013A/14A and the
CY7C68015A/16A.
The 128-pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100-pin version.
In the 100-pin and 128-pin versions, an 8051 control bit can be
set to pulse the RD# and WR# pins when the 8051 reads
from/writes to PORTC. This feature is enabled by setting the
PORTCSTB bit in the CPUCS register.
Section 9.5 displays the timing diagram of the read and write
strobing function on accessing PORTC.
Nine 8051 signals (two USARTs, three timer inputs, INT4, and
INT5#)
Page 16 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Port
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
56
GPIF Master
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
Slave FIFO
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
RDY0
RDY1
SLRD
SLWR
CTL0
CTL1
CTL2
FLAGA
FLAGB
FLAGC
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
100
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
128
RD#
WR#
CS#
OE#
PSEN#
D7
D6
D5
D4
D3
D2
D1
D0
EA
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2
T1
T0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Page 17 of 71
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CY7C68015A, CY7C68016A
27
28
29
30
31
32
33
34
35
36
37
38
103
26
104
25
105
24
106
23
107
22
108
21
109
20
110
19
111
18
112
17
113
16
114
15
115
14
116
13
117
12
118
11
119
10
120
121
122
123
124
125
126
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
A4
A5
A6
A7
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
A8
A9
A10
127
128
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
EA
SCL
SDA
OE#
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
A3
A2
A1
A0
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
D6
D5
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
GND
CY7C68013A/CY7C68014A
128-pin TQFP
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
D4
D3
D2
D1
D0
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
CS#
WR#
RD#
PSEN#
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
Page 18 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
SCL
SDA
CY7C68013A/CY7C68014A
100-pin TQFP
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
WR#
RD#
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
Page 19 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
CY7C68013A/CY7C68014A
56-pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK
RESERVED
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Page 20 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
GND
VCC
CLKOUT/**PE1
GND
PD7/FD15
PD6/FD14
PD5/FD13
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
RDY0/*SLRD
42
RESET#
RDY1/*SLWR
41
GND
AVCC
40
PA7/*FLAGD/SLCS#
XTALOUT
39
PA6/*PKTEND
XTALIN
38
PA5/FIFOADR1
AGND
37
PA4/FIFOADR0
AVCC
36
PA3/*WU2
DPLUS
35
PA2/*SLOE
DMINUS
34
PA1/INT1#
AGND
10
33
PA0/INT0#
VCC
11
32
VCC
GND
12
31
CTL2/*FLAGC
*IFCLK/**PE0
13
30
CTL1/*FLAGB
RESERVED
14
29
CTL0/*FLAGA
CY7C68013A/CY7C68014A
&
CY7C68015A/CY7C68016A
56-pin QFN
18
19
20
21
22
23
24
25
26
27
28
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
PB4/FD4
PB5/FD5
PB6/FD6
PB7/FD7
GND
VCC
GND
SDA
VCC
16
SCL
17
15
Page 21 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
1A
2A
3A
4A
5A
6A
7A
8A
1B
2B
3B
4B
5B
6B
7B
8B
1C
2C
3C
4C
5C
6C
7C
8C
1D
2D
7D
8D
1E
2E
7E
8E
1F
2F
3F
4F
5F
6F
7F
8F
1G
2G
3G
4G
5G
6G
7G
8G
1H
2H
3H
4H
5H
6H
7H
8H
Page 22 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Name
Type
Default Reset[12]
Description
10
10
2D
AVCC
Power
N/A
N/A
17
16
14
1D
AVCC
Power
N/A
N/A
13
12
13
2F
AGND
Ground
N/A
N/A
20
19
17
10
1F
AGND
Ground
N/A
N/A
19
18
16
1E
DMINUS
I/O/Z
N/A
2E
DPLUS
I/O/Z
N/A
94
18
17
15
A0
Output
95
A1
Output
96
A2
Output
97
A3
Output
117
A4
Output
118
A5
Output
119
A6
Output
120
A7
Output
126
A8
Output
127
A9
Output
128
A10
Output
21
A11
Output
22
A12
Output
23
A13
Output
24
A14
Output
25
A15
Output
59
D0
I/O/Z
60
D1
I/O/Z
61
D2
I/O/Z
62
D3
I/O/Z
63
D4
I/O/Z
86
D5
I/O/Z
87
D6
I/O/Z
88
D7
39
PSEN#
I/O/Z
Output
Notes
11. Unused inputs must not be left floating. Tie either HIGH or LOW as appropriate. Outputs should only be pulled up or down to ensure signals at power up and in standby.
Note also that no pins should be driven while the device is powered down.
12. The Reset column indicates the state of signals during reset (RESET# asserted) or during Power on Reset (POR).
Page 23 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions[11] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
34
28
99
77
49
42
8B
35
12
11
12
11
10
11
100
82
83
Name
BKPT
Type
Default Reset[12]
Description
Output
RESET#
Input
N/A
N/A
EA
Input
N/A
N/A
1C
XTALIN
Input
N/A
N/A
2C
XTALOUT
Output
N/A
N/A
54
2B
67
40
33
8G
PA0 or
INT0#
I/O/Z
I
(PA0)
Z
(PA0)
68
41
34
6G
PA1 or
INT1#
I/O/Z
I
(PA1)
Z
(PA1)
Port A
Page 24 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions[11] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[12]
Description
84
69
42
35
8F
PA2 or
SLOE
I/O/Z
I
(PA2)
Z
(PA2)
85
70
43
36
7F
PA3 or
WU2
I/O/Z
I
(PA3)
Z
(PA3)
89
71
44
37
6F
PA4 or
FIFOADR0
I/O/Z
I
(PA4)
Z
(PA4)
90
72
45
38
8C
PA5 or
FIFOADR1
I/O/Z
I
(PA5)
Z
(PA5)
91
73
46
39
7C
PA6 or
PKTEND
I/O/Z
I
(PA6)
Z
(PA6)
92
74
47
40
6C
PA7 or
FLAGD or
SLCS#
I/O/Z
I
(PA7)
Z
(PA7)
44
34
25
18
3H
PB0 or
FD[0]
I/O/Z
I
(PB0)
Z
(PB0)
45
35
26
19
4F
PB1 or
FD[1]
I/O/Z
I
(PB1)
Z
(PB1)
46
36
27
20
4H
PB2 or
FD[2]
I/O/Z
I
(PB2)
Z
(PB2)
Port B
Page 25 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions[11] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[12]
Description
47
37
28
21
4G
PB3 or
FD[3]
I/O/Z
I
(PB3)
Z
(PB3)
54
44
29
22
5H
PB4 or
FD[4]
I/O/Z
I
(PB4)
Z
(PB4)
55
45
30
23
5G
PB5 or
FD[5]
I/O/Z
I
(PB5)
Z
(PB5)
56
46
31
24
5F
PB6 or
FD[6]
I/O/Z
I
(PB6)
Z
(PB6)
57
47
32
25
6H
PB7 or
FD[7]
I/O/Z
I
(PB7)
Z
(PB7)
PORT C
72
57
PC0 or
GPIFADR0
I/O/Z
I
(PC0)
Z
(PC0)
73
58
PC1 or
GPIFADR1
I/O/Z
I
(PC1)
Z
(PC1)
74
59
PC2 or
GPIFADR2
I/O/Z
I
(PC2)
Z
(PC2)
75
60
PC3 or
GPIFADR3
I/O/Z
I
(PC3)
Z
(PC3)
76
61
PC4 or
GPIFADR4
I/O/Z
I
(PC4)
Z
(PC4)
77
62
PC5 or
GPIFADR5
I/O/Z
I
(PC5)
Z
(PC5)
78
63
PC6 or
GPIFADR6
I/O/Z
I
(PC6)
Z
(PC6)
79
64
PC7 or
GPIFADR7
I/O/Z
I
(PC7)
Z
(PC7)
Page 26 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions[11] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[12]
Description
PORT D
102
80
52
45
8A
PD0 or
FD[8]
I/O/Z
I
(PD0)
Z
(PD0)
103
81
53
46
7A
PD1 or
FD[9]
I/O/Z
I
(PD1)
Z
(PD1)
104
82
54
47
6B
PD2 or
FD[10]
I/O/Z
I
(PD2)
Z
(PD2)
105
83
55
48
6A
PD3 or
FD[11]
I/O/Z
I
(PD3)
Z
(PD3)
121
95
56
49
3B
PD4 or
FD[12]
I/O/Z
I
(PD4)
Z
(PD4)
122
96
50
3A
PD5 or
FD[13]
I/O/Z
I
(PD5)
Z
(PD5)
123
97
51
3C
PD6 or
FD[14]
I/O/Z
I
(PD6)
Z
(PD6)
124
98
52
2A
PD7 or
FD[15]
I/O/Z
I
(PD7)
Z
(PD7)
108
86
PE0 or
T0OUT
I/O/Z
I
(PE0)
Z
(PE0)
109
87
PE1 or
T1OUT
I/O/Z
I
(PE1)
Z
(PE1)
Port E
Page 27 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions[11] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[12]
Description
110
88
PE2 or
T2OUT
I/O/Z
I
(PE2)
Z
(PE2)
111
89
PE3 or
RXD0OUT
I/O/Z
I
(PE3)
Z
(PE3)
112
90
PE4 or
RXD1OUT
I/O/Z
I
(PE4)
Z
(PE4)
113
91
PE5 or
INT6
I/O/Z
I
(PE5)
Z
(PE5)
114
92
PE6 or
T2EX
I/O/Z
I
(PE6)
Z
(PE6)
115
93
PE7 or
GPIFADR8
I/O/Z
I
(PE7)
Z
(PE7)
1A
RDY0 or
SLRD
Input
N/A
N/A
1B
RDY1 or
SLWR
Input
N/A
N/A
RDY2
Input
N/A
N/A
RDY3
Input
N/A
N/A
RDY4
Input
N/A
N/A
Page 28 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions[11] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
9
69
54
36
29
70
55
37
71
56
38
Name
Type
Default Reset[12]
Description
RDY5
Input
N/A
N/A
7H
CTL0 or
FLAGA
O/Z
30
7G
CTL1 or
FLAGB
O/Z
31
8H
CTL2 or
FLAGC
O/Z
66
51
CTL3
O/Z
67
52
CTL4
Output
CTL5
98
76
32
26
20
13
2G
Output
IFCLK on
CY7C68013
A
and
CY7C68014
A
I/O/Z
28
22
INT4
Input
N/A
N/A
106
84
INT5#
Input
N/A
N/A
31
25
T2
Input
N/A
N/A
Page 29 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions[11] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[12]
Description
30
24
T1
Input
N/A
N/A
29
23
T0
Input
N/A
N/A
53
43
RXD1
Input
N/A
N/A
52
42
TXD1
Output
51
41
RXD0
Input
N/A
N/A
50
40
TXD0
Output
CS#
Output
42
41
32
WR#
Output
40
31
RD#
Output
OE#
Output
38
33
27
21
14
2H
Reserved
Input
N/A
N/A
101
79
51
44
7B
WAKEUP
Input
N/A
N/A
36
29
22
15
3F
SCL
OD
Z
Clock for the I2C interface. Connect to VCC with a
(if
2.2-k resistor, even if no I2C peripheral is attached.
booting
is done)
37
30
23
16
3G
SDA
OD
Z
Data for I2C compatible interface. Connect to VCC
(if
with a 2.2-k resistor, even if no I2C compatible
booting peripheral is attached.
is done)
55
5A
VCC
Power
N/A
N/A
26
20
18
11
1G
VCC
Power
N/A
N/A
43
33
24
17
7E
VCC
Power
N/A
N/A
48
38
VCC
Power
N/A
N/A
64
49
34
27
8E
VCC
Power
N/A
N/A
68
53
VCC
Power
N/A
N/A
81
66
39
32
5C
VCC
Power
N/A
N/A
Page 30 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 10. FX2LP Pin Descriptions[11] (continued)
128 100
56
56
56
TQFP TQFP SSOP QFN VFBGA
Name
Type
Default Reset[12]
Description
100
78
50
43
5B
VCC
Power
N/A
N/A
107
85
VCC
Power
N/A
N/A
56
4B
GND
Ground
N/A
N/A
Ground
27
21
19
12
1H
GND
Ground
N/A
N/A
Ground
49
39
GND
Ground
N/A
N/A
Ground
58
48
33
26
7D
GND
Ground
N/A
N/A
Ground
65
50
35
28
8D
GND
Ground
N/A
N/A
Ground
80
65
GND
Ground
N/A
N/A
Ground
93
75
48
41
4C
GND
Ground
N/A
N/A
Ground
116
94
GND
Ground
N/A
N/A
Ground
125
99
53
4A
GND
Ground
N/A
N/A
Ground
14
13
NC
N/A
N/A
N/A
15
14
NC
N/A
N/A
N/A
16
15
NC
N/A
N/A
N/A
4. Register Summary
FX2LP register bit definitions are described in the FX2LP TRM in greater detail.
Table 11. FX2LP Register Summary
Hex Size
Name
Description
GPIF Waveform Memories
E400 128 WAVEDATA
GPIF Waveform
Descriptor 0, 1, 2, 3 data
E480 128 reserved
GENERAL CONFIGURATION
E50D
GPCR2
General Purpose Configuration Register 2
E600 1
CPUCS
CPU Control & Status
E601 1
IFCONFIG
Interface Configuration
(Ports, GPIF, slave FIFOs)
[13]
E602 1
PINFLAGSAB
Slave FIFO FLAGA and
FLAGB Pin Configuration
E603 1
PINFLAGSCD[13]
Slave FIFO FLAGC and
FLAGD Pin Configuration
[13]
E604 1
FIFORESET
Restore FIFOS to default
state
E605 1
BREAKPT
Breakpoint Control
E606 1
BPADDRH
Breakpoint Address H
E607 1
BPADDRL
Breakpoint Address L
E608 1
UART230
230 Kbaud internally
generated ref. clock
[13]
E609 1
FIFOPINPOLAR
Slave FIFO Interface pins
polarity
E60A 1
REVID
Chip Revision
E60B 1
E60C 1
3
E610 1
E611 1
E612
E613
E614
E615
1
1
1
1
REVCTL[13]
b7
b6
b5
D7
D6
D5
reserved
reserved
reserved
0
IFCLKSRC
b4
D4
b3
D3
b2
b1
b0
Default
Access
D2
D1
D0
xxxxxxxx RW
reserved
reserved
reserved
00000000 R
0
3048MHZ
FULL_SPEE reserved
D_ONLY
PORTCSTB CLKSPD1
CLKSPD0
IFCLKOE
IFCLKPOL ASYNC
CLKINV
GSTATE
CLKOE
IFCFG1
8051RES
IFCFG0
00000010 rrbbbbbr
10000000 RW
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
00000000 RW
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
00000000 RW
NAKALL
EP3
EP2
EP1
EP0
xxxxxxxx W
0
A15
A7
0
0
A14
A6
0
0
A13
A5
0
0
A12
A4
0
BREAK
A11
A3
0
BPPULSE
A10
A2
0
BPEN
A9
A1
230UART1
0
A8
A0
230UART0
00000000
xxxxxxxx
xxxxxxxx
00000000
PKTEND
SLOE
SLRD
SLWR
EF
FF
00000000 rrbbbbbb
rv7
rv6
rv5
rv4
rv3
rv2
rv1
rv0
dyn_out
enh_pkt
RevA
R
00000001
00000000 rrrrrrbb
VALID
TYPE1
TYPE0
10100000 brbbrrrr
VALID
TYPE1
TYPE0
10100000 brbbrrrr
VALID
VALID
VALID
VALID
DIR
DIR
DIR
DIR
TYPE1
TYPE1
TYPE1
TYPE1
TYPE0
TYPE0
TYPE0
TYPE0
SIZE
0
SIZE
0
0
0
0
0
BUF1
0
BUF1
0
BUF0
0
BUF0
0
10100010
10100000
11100010
11100000
rrrrbbbr
RW
RW
rrrrrrbb
bbbbbrbb
bbbbrrrr
bbbbbrbb
bbbbrrrr
Page 31 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Description
Endpoint 2 / slave FIFO
configuration
Endpoint 4 / slave FIFO
configuration
Endpoint 6 / slave FIFO
configuration
Endpoint 8 / slave FIFO
configuration
E619 1
EP4FIFOCFG
E61A 1
EP6FIFOCFG[13]
E61B 1
EP8FIFOCFG[13]
E61C 4
E620 1
reserved
EP2AUTOINLENH[13 Endpoint 2 AUTOIN
Packet Length H
EP2AUTOINLENL[13] Endpoint 2 AUTOIN
Packet Length L
EP4AUTOINLENH[13] Endpoint 4 AUTOIN
Packet Length H
EP4AUTOINLENL[13] Endpoint 4 AUTOIN
Packet Length L
EP6AUTOINLENH[13] Endpoint 6 AUTOIN
Packet Length H
EP6AUTOINLENL[13] Endpoint 6 AUTOIN
Packet Length L
EP8AUTOINLENH[13] Endpoint 8 AUTOIN
Packet Length H
EP8AUTOINLENL[13] Endpoint 8 AUTOIN
Packet Length L
ECCCFG
ECC Configuration
ECCRESET
ECC Reset
ECC1B0
ECC1 Byte 0 Address
E621 1
E622 1
E623 1
E624 1
E625 1
E626 1
E627 1
E628 1
E629 1
E62A 1
b7
b6
b5
b4
b3
b2
b1
b0
Default
Access
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
INFM1
OEP1
AUTOOUT
AUTOIN
ZEROLENIN 0
PL10
PL9
PL8
00000010 rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
PL9
PL8
00000010 rrrrrrbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
PL10
PL9
PL8
00000010 rrrrrbbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
PL9
PL8
00000010 rrrrrrbb
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
00000000 RW
0
x
LINE15
0
x
LINE14
0
x
LINE13
0
x
LINE12
0
x
LINE11
0
x
LINE10
0
x
LINE9
ECCM
x
LINE8
00000000 rrrrrrrb
00000000 W
00000000 R
Note
13. Read and writes to these registers may require synchronization delay; see Technical Reference Manual for Synchronization Delay.
Page 32 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Size
1
1
1
1
1
1
Name
ECC1B1
ECC1B2
ECC2B0
ECC2B1
ECC2B2
EP2FIFOPFH[13]
EP2FIFOPFH[13]
EP2FIFOPFL[13]
EP2FIFOPFL
[13]
EP4FIFOPFH[13]
EP4FIFOPFH
[13]
EP4FIFOPFL[13]
EP4FIFOPFL[13]
EP6FIFOPFH
[13]
EP6FIFOPFH[13]
EP6FIFOPFL[13]
EP6FIFOPFL[13]
EP8FIFOPFH
[13]
EP8FIFOPFH[13]
EP8FIFOPFL[13]
EP8FIFOPFL[13]
8
E640 1
reserved
EP2ISOINPKTS
E641 1
EP4ISOINPKTS
E642 1
EP6ISOINPKTS
E643 1
EP8ISOINPKTS
E644 4
E648 1
E649 7
E650 1
reserved
INPKTEND[13]
OUTPKTEND[13]
INTERRUPTS
EP2FIFOIE[13]
E651 1
EP2FIFOIRQ[13,14]
E652 1
EP4FIFOIE[13]
E653 1
[13,14]
EP4FIFOIRQ
[13]
E654 1
EP6FIFOIE
E655 1
EP6FIFOIRQ[13,14]
E656 1
EP8FIFOIE[13]
[13,14]
E657 1
EP8FIFOIRQ
E658 1
IBNIE
E659 1
IBNIRQ[14]
E65A 1
NAKIE
E65B 1
NAKIRQ[14]
E65C 1
USBIE
Description
ECC1 Byte 1 Address
ECC1 Byte 2 Address
ECC2 Byte 0 Address
ECC2 Byte 1 Address
ECC2 Byte 2 Address
Endpoint 2 / slave FIFO
Programmable Flag H
Endpoint 2 / slave FIFO
Programmable Flag H
Endpoint 2 / slave FIFO
Programmable Flag L
Endpoint 2 / slave FIFO
Programmable Flag L
Endpoint 4 / slave FIFO
Programmable Flag H
Endpoint 4 / slave FIFO
Programmable Flag H
Endpoint 4 / slave FIFO
Programmable Flag L
Endpoint 4 / slave FIFO
Programmable Flag L
Endpoint 6 / slave FIFO
Programmable Flag H
Endpoint 6 / slave FIFO
Programmable Flag H
Endpoint 6 / slave FIFO
Programmable Flag L
Endpoint 6 / slave FIFO
Programmable Flag L
Endpoint 8 / slave FIFO
Programmable Flag H
Endpoint 8 / slave FIFO
Programmable Flag H
Endpoint 8 / slave FIFO
Programmable Flag L
Endpoint 8 / slave FIFO
Programmable Flag L
b7
LINE7
COL5
LINE15
LINE7
COL5
DECIS
b6
LINE6
COL4
LINE14
LINE6
COL4
PKTSTAT
b4
LINE4
COL2
LINE12
LINE4
COL2
IN:PKTS[1]
OUT:PFC11
OUT:PFC11
b3
LINE3
COL1
LINE11
LINE3
COL1
IN:PKTS[0]
OUT:PFC10
OUT:PFC10
b2
LINE2
COL0
LINE10
LINE2
COL0
0
b1
LINE1
LINE17
LINE9
LINE1
0
PFC9
b0
LINE0
LINE16
LINE8
LINE0
0
PFC8
Default
00000000
00000000
00000000
00000000
00000000
10001000
PKTSTAT
b5
LINE5
COL3
LINE13
LINE5
COL3
IN:PKTS[2]
OUT:PFC12
OUT:PFC12
DECIS
Access
R
R
R
R
R
bbbbbrbb
PFC9
10001000 bbbbbrbb
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
IN:PKTS[2]
OUT:PFC8
PFC0
IN:PKTS[1]
OUT:PFC7
DECIS
IN:PKTS[0]
OUT:PFC6
PKTSTAT
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
PFC8
10001000 bbrbbrrb
DECIS
PKTSTAT
PFC8
10001000 bbrbbrrb
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
IN: PKTS[1]
OUT:PFC7
DECIS
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
IN:PKTS[1] IN:PKTS[0] 0
OUT:PFC11 OUT:PFC10
OUT:PFC11 OUT:PFC10 0
PFC9
PFC8
00001000 bbbbbrbb
DECIS
PFC9
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
IN:PKTS[2]
OUT:PFC8
PFC0
00001000 bbbbbrbb
PFC7
IN:PKTS[1]
OUT:PFC7
DECIS
IN:PKTS[0]
OUT:PFC6
PKTSTAT
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
PFC8
00001000 bbrbbrrb
PKTSTAT
DECIS
PFC8
00001000 bbrbbrrb
PFC7
PFC6
PFC5
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
IN: PKTS[1]
OUT:PFC7
PFC4
PFC3
PFC2
PFC1
PFC0
00000000 RW
AADJ
INPPF1
INPPF0
00000001 brrrrrbb
AADJ
INPPF1
INPPF0
00000001 brrrrrrr
AADJ
INPPF1
INPPF0
00000001 brrrrrbb
AADJ
INPPF1
INPPF0
00000001 brrrrrrr
Skip
Skip
0
0
0
0
0
0
EP3
EP3
EP2
EP2
EP1
EP1
EP0
EP0
xxxxxxxx W
xxxxxxxx W
EDGEPF
PF
EF
FF
00000000 RW
PF
EF
FF
00000000 rrrrrbbb
EDGEPF
PF
EF
FF
00000000 RW
PF
EF
FF
00000000 rrrrrbbb
EDGEPF
PF
EF
FF
00000000 RW
PF
EF
FF
00000000 rrrrrbbb
EDGEPF
PF
EF
FF
00000000 RW
PF
EF
FF
00000000 rrrrrbbb
EP8
EP6
EP4
EP2
EP1
EP0
00000000 RW
EP8
EP6
EP4
EP2
EP1
EP0
00xxxxxx rrbbbbbb
EP8
EP6
EP4
EP2
EP1
EP0
IBN
00000000 RW
EP8
EP6
EP4
EP2
EP1
EP0
IBN
xxxxxx0x bbbbbbrb
EP0ACK
HSGRANT
URES
SUSP
SUTOK
SOF
SUDAV
00000000 RW
00000000 RW
00000000 RW
Note
14. The register can only be reset; it cannot be set.
Page 33 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
EPIRQ[14]
E660 1
E661 1
E662 1
GPIFIE[13]
GPIFIRQ[13]
USBERRIE
E663 1
USBERRIRQ[14]
E664 1
E665 1
E666 1
ERRCNTLIM
CLRERRCNT
INT2IVEC
E667 1
INT4IVEC
E668 1
E669 7
E670 1
INTSET-UP
reserved
INPUT / OUTPUT
PORTACFG
E671 1
PORTCCFG
E672 1
PORTECFG
E673 4
E677 1
E678 1
reserved
reserved
I2CS
E679 1
I2DAT
E67A 1
I2CTL
E67B 1
XAUTODAT1
E67C 1
XAUTODAT2
E680
E681
E682
E683
E684
E685
E686
E687
E688
1
1
1
1
1
1
1
1
2
UDMA CRC
UDMACRCH[13]
UDMACRCL[13]
UDMACRCQUALIFIER
USB CONTROL
USBCS
SUSPEND
WAKEUPCS
TOGCTL
USBFRAMEH
USBFRAMEL
MICROFRAME
FNADDR
reserved
E68A
E68B
E68C
E68D
1
1
1
1
ENDPOINTS
EP0BCH[13]
EP0BCL[13]
reserved
EP1OUTBC
E68E
E68F
E690
E691
E692
E694
E695
E696
E698
E699
E69A
E69C
E69D
E69E
1
1
1
1
2
1
1
2
1
1
2
1
1
2
reserved
EP1INBC
EP2BCH[13]
EP2BCL[13]
reserved
EP4BCH[13]
EP4BCL[13]
reserved
EP6BCH[13]
EP6BCL[13]
reserved
EP8BCH[13]
EP8BCL[13]
reserved
E67D 1
E67E 1
E67F 1
Description
b7
USB Interrupt Requests 0
Endpoint Interrupt
EP8
Enables
Endpoint Interrupt
EP8
Requests
GPIF Interrupt Enable
0
GPIF Interrupt Request
0
USB Error Interrupt
ISOEP8
Enables
USB Error Interrupt
ISOEP8
Requests
USB Error counter and limit EC3
Clear Error Counter EC3:0 x
Interrupt 2 (USB)
0
Autovector
Interrupt 4 (slave FIFO & 1
GPIF) Autovector
Interrupt 2&4 setup
0
b6
EP0ACK
EP6
b5
HSGRANT
EP4
b4
URES
EP2
b3
SUSP
EP1OUT
b2
SUTOK
EP1IN
b1
SOF
EP0OUT
b0
SUDAV
EP0IN
Default Access
0xxxxxxx rbbbbbbb
00000000 RW
EP6
EP4
EP2
EP1OUT
EP1IN
EP0OUT
EP0IN
0
0
ISOEP6
0
0
ISOEP4
0
0
ISOEP2
0
0
0
0
0
0
GPIFWF
GPIFWF
0
GPIFDONE
GPIFDONE
ERRLIMIT
00000000 RW
000000xx RW
00000000 RW
ISOEP6
ISOEP4
ISOEP2
ERRLIMIT
0000000x bbbbrrrb
EC2
x
I2V4
EC1
x
I2V3
EC0
x
I2V2
LIMIT3
x
I2V1
LIMIT2
x
I2V0
LIMIT1
x
0
LIMIT0
x
0
xxxx0100 rrrrbbbb
xxxxxxxx W
00000000 R
I4V3
I4V2
I4V1
I4V0
10000000 R
AV2EN
INT4SRC
AV4EN
00000000 RW
FLAGD
SLCS
INT1
INT0
00000000 RW
GPIFA7
GPIFA6
GPIFA5
GPIFA4
GPIFA3
GPIFA2
GPIFA1
GPIFA0
00000000 RW
GPIFA8
T2EX
INT6
RXD1OUT
RXD0OUT
T2OUT
T1OUT
T0OUT
00000000 RW
IC Bus
Control & Status
IC Bus
Data
IC Bus
Control
Autoptr1 MOVX access,
when APTREN=1
Autoptr2 MOVX access,
when APTREN=1
START
STOP
LASTRD
ID1
ID0
BERR
ACK
DONE
000xx000 bbbrrrrr
d7
d6
d5
d4
d3
d2
d1
d0
xxxxxxxx RW
STOPIE
400KHZ
00000000 RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
CRC15
CRC7
QENABLE
CRC14
CRC6
0
CRC13
CRC5
0
CRC12
CRC4
0
CRC11
CRC3
QSTATE
CRC10
CRC2
QSIGNAL2
CRC9
CRC1
QSIGNAL1
CRC8
CRC0
QSIGNAL0
01001010 RW
10111010 RW
00000000 brrrbbbb
HSM
x
WU2
Q
0
FC7
0
0
0
x
WU
S
0
FC6
0
FA6
0
x
WU2POL
R
0
FC5
0
FA5
0
x
WUPOL
I/O
0
FC4
0
FA4
DISCON
x
0
EP3
0
FC3
0
FA3
NOSYNSOF
x
DPEN
EP2
FC10
FC2
MF2
FA2
RENUM
x
WU2EN
EP1
FC9
FC1
MF1
FA1
SIGRSUME
x
WUEN
EP0
FC8
FC0
MF0
FA0
x0000000
xxxxxxxx
xx000101
x0000000
00000xxx
xxxxxxxx
00000xxx
0xxxxxxx
(BC15)
(BC7)
(BC14)
BC6
(BC13)
BC5
(BC12)
BC4
(BC11)
BC3
(BC10)
BC2
(BC9)
BC1
(BC8)
BC0
xxxxxxxx RW
xxxxxxxx RW
BC6
BC5
BC4
BC3
BC2
BC1
BC0
0xxxxxxx RW
BC6
0
BC6
BC5
0
BC5
BC4
0
BC4
BC3
0
BC3
BC2
BC10
BC2
BC1
BC9
BC1
BC0
BC8
BC0
0xxxxxxx RW
00000xxx RW
xxxxxxxx RW
0
BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC9
BC1
BC8
BC0
000000xx RW
xxxxxxxx RW
0
BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
BC10
BC2
BC9
BC1
BC8
BC0
00000xxx RW
xxxxxxxx RW
0
BC7/SKIP
0
BC6
0
BC5
0
BC4
0
BC3
0
BC2
BC9
BC1
BC8
BC0
000000xx RW
xxxxxxxx RW
RW
rrrrbbbb
W
bbbbrbbb
rrrbbbbb
R
R
R
R
Page 34 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
EP1OUTCS
E6A2 1
EP1INCS
E6A3 1
EP2CS
E6A4 1
EP4CS
E6A5 1
EP6CS
E6A6 1
EP8CS
E6A7 1
EP2FIFOFLGS
E6A8 1
EP4FIFOFLGS
E6A9 1
EP6FIFOFLGS
E6AA 1
EP8FIFOFLGS
E6AB 1
EP2FIFOBCH
E6AC 1
EP2FIFOBCL
E6AD 1
EP4FIFOBCH
E6AE 1
EP4FIFOBCL
E6AF 1
EP6FIFOBCH
E6B0 1
EP6FIFOBCL
E6B1 1
EP8FIFOBCH
E6B2 1
EP8FIFOBCL
E6B3 1
SUDPTRH
E6B4 1
SUDPTRL
E6B5 1
SUDPTRCTL
2
E6B8 8
reserved
SET-UPDAT
E6C0 1
E6C1 1
GPIF
GPIFWFSELECT
GPIFIDLECS
E6C2
E6C3
E6C4
E6C5
1
1
1
1
E6C6 1
GPIFIDLECTL
GPIFCTLCFG
GPIFADRH[13]
GPIFADRL[13]
FLOWSTATE
FLOWSTATE
E6C7 1
E6C8 1
FLOWLOGIC
FLOWEQ0CTL
E6C9 1
FLOWEQ1CTL
E6CA 1
E6CB 1
FLOWHOLDOFF
FLOWSTB
E6CC 1
FLOWSTBEDGE
E6CD 1
E6CE 1
FLOWSTBPERIOD
GPIFTCB3[13]
Description
b7
Endpoint 0 Control and Sta- HSNAK
tus
Endpoint 1 OUT Control 0
and Status
Endpoint 1 IN Control and 0
Status
Endpoint 2 Control and Sta- 0
tus
Endpoint 4 Control and Sta- 0
tus
Endpoint 6 Control and Sta- 0
tus
Endpoint 8 Control and Sta- 0
tus
Endpoint 2 slave FIFO
0
Flags
Endpoint 4 slave FIFO
0
Flags
Endpoint 6 slave FIFO
0
Flags
Endpoint 8 slave FIFO
0
Flags
Endpoint 2 slave FIFO
0
total byte count H
Endpoint 2 slave FIFO
BC7
total byte count L
Endpoint 4 slave FIFO
0
total byte count H
Endpoint 4 slave FIFO
BC7
total byte count L
Endpoint 6 slave FIFO
0
total byte count H
Endpoint 6 slave FIFO
BC7
total byte count L
Endpoint 8 slave FIFO
0
total byte count H
Endpoint 8 slave FIFO
BC7
total byte count L
Setup Data Pointer high A15
address byte
Setup Data Pointer low ad- A7
dress byte
Setup Data Pointer Auto 0
Mode
8 bytes of setup data
D7
SET-UPDAT[0] =
bmRequestType
SET-UPDAT[1] =
bmRequest
SET-UPDAT[2:3] = wValue
SET-UPDAT[4:5] = wIndex
SET-UPDAT[6:7] =
wLength
b6
0
b5
0
b4
0
b3
0
b2
b1
BUSY
b0
STALL
Default Access
10000000 bbbbbbrb
BUSY
STALL
00000000 bbbbbbrb
BUSY
STALL
00000000 bbbbbbrb
NPAK2
NPAK1
NPAK0
FULL
EMPTY
STALL
00101000 rrrrrrrb
NPAK1
NPAK0
FULL
EMPTY
STALL
00101000 rrrrrrrb
NPAK2
NPAK1
NPAK0
FULL
EMPTY
STALL
00000100 rrrrrrrb
NPAK1
NPAK0
FULL
EMPTY
STALL
00000100 rrrrrrrb
PF
EF
FF
00000010 R
PF
EF
FF
00000010 R
PF
EF
FF
00000110 R
PF
EF
FF
00000110 R
BC12
BC11
BC10
BC9
BC8
00000000 R
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000 R
BC10
BC9
BC8
00000000 R
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000 R
BC11
BC10
BC9
BC8
00000000 R
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000 R
BC10
BC9
BC8
00000000 R
BC6
BC5
BC4
BC3
BC2
BC1
BC0
00000000 R
A14
A13
A12
A11
A10
A9
A8
xxxxxxxx RW
A6
A5
A4
A3
A2
A1
xxxxxxx0 bbbbbbbr
SDPAUTO
00000001 RW
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx R
Waveform Selector
GPIF Done, GPIF IDLE
drive mode
Inactive Bus, CTL states
CTL Drive Type
GPIF Address H
GPIF Address L
FIFOWR0
0
FIFORD1
0
FIFORD0
IDLEDRV
11100100 RW
10000000 RW
0
TRICTL
0
GPIFA7
0
0
0
GPIFA6
CTL5
CTL5
0
GPIFA5
CTL4
CTL4
0
GPIFA4
CTL3
CTL3
0
GPIFA3
CTL2
CTL2
0
GPIFA2
CTL1
CTL1
0
GPIFA1
CTL0
CTL0
GPIFA8
GPIFA0
11111111
00000000
00000000
00000000
FSE
FS2
FS1
FS0
00000000 brrrrbbb
LFUNC1
CTL0E3
LFUNC0
CTL0E2
TERMA2
CTL0E1/
CTL5
TERMA1
CTL0E0/
CTL4
TERMA0
CTL3
TERMB2
CTL2
TERMB1
CTL1
TERMB0
CTL0
00000000 RW
00000000 RW
CTL0E3
CTL0E2
RW
RW
RW
RW
CTL0E1/
CTL5
HOPERIOD3 HOPERIOD2 HOPERIOD1
SLAVE
RDYASYNC CTLTOGL
CTL0E0/
CTL3
CTL4
HOPERIOD0 HOSTATE
SUSTAIN
0
CTL2
CTL1
CTL0
00000000 RW
HOCTL2
MSTB2
HOCTL1
MSTB1
HOCTL0
MSTB0
00010010 RW
00100000 RW
FALLING
RISING
00000001 rrrrrrbb
D7
TC31
D6
TC30
D5
TC29
D4
TC28
D3
TC27
D2
TC26
D1
TC25
D0
TC24
00000010 RW
00000000 RW
Page 35 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
GPIFTCB1[13]
E6D1 1
GPIFTCB0[13]
E6D2 1
E6D3 1
E6D4 1
3
E6DA 1
E6DB 1
E6DC 1
3
E6E2 1
E6E3 1
E6E4 1
3
E6EA 1
E6EB 1
E6EC 1
3
E6F0 1
E6F1 1
E6F2 1
E6F3 1
E6F4 1
E6F5 1
E6F6 2
E740
E780
E7C0
E800
F000
64
64
64
2048
1024
F400 512
F600 512
F800 1024
FC00 512
FE00 512
Description
GPIF Transaction Count
Byte 2
GPIF Transaction Count
Byte 1
GPIF Transaction Count
Byte 0
reserved
reserved
reserved
EP2GPIFFLGSEL[13] Endpoint 2 GPIF Flag
select
EP2GPIFPFSTOP
Endpoint 2 GPIF stop
transaction on prog. flag
[13]
EP2GPIFTRIG
Endpoint 2 GPIF Trigger
reserved
reserved
reserved
EP4GPIFFLGSEL[13] Endpoint 4 GPIF Flag
select
EP4GPIFPFSTOP
Endpoint 4 GPIF stop
transaction on GPIF Flag
[13]
EP4GPIFTRIG
Endpoint 4 GPIF Trigger
reserved
reserved
reserved
EP6GPIFFLGSEL[13] Endpoint 6 GPIF Flag
select
EP6GPIFPFSTOP
Endpoint 6 GPIF stop
transaction on prog. flag
[13]
EP6GPIFTRIG
Endpoint 6 GPIF Trigger
reserved
reserved
reserved
EP8GPIFFLGSEL[13] Endpoint 8 GPIF Flag
select
EP8GPIFPFSTOP
Endpoint 8 GPIF stop
transaction on prog. flag
[13]
EP8GPIFTRIG
Endpoint 8 GPIF Trigger
reserved
XGPIFSGLDATH
GPIF Data H
(16-bit mode only)
XGPIFSGLDATLX
Read/Write GPIF Data L &
trigger transaction
XGPIFSGLDATLNOX Read GPIF Data L, no
transaction trigger
GPIFREADYCFG
Internal RDY, Sync/Async,
RDY pin states
GPIFREADYSTAT
GPIF Ready Status
GPIFABORT
Abort GPIF Waveforms
reserved
ENDPOINT BUFFERS
EP0BUF
EP0-IN/-OUT buffer
EP10UTBUF
EP1-OUT buffer
EP1INBUF
EP1-IN buffer
reserved
EP2FIFOBUF
512/1024 byte EP 2 / slave
FIFO buffer (IN or OUT)
EP4FIFOBUF
512 byte EP 4 / slave FIFO
buffer (IN or OUT)
reserved
EP6FIFOBUF
512/1024 byte EP 6 / slave
FIFO buffer (IN or OUT)
EP8FIFOBUF
512 byte EP 8 / slave FIFO
buffer (IN or OUT)
reserved
TC23
b7
TC22
b6
TC21
b5
b4
TC20
b3
TC19
b2
TC18
b1
TC17
TC16
b0
Default Access
00000000 RW
TC15
TC14
TC13
TC12
TC11
TC10
TC9
TC8
00000000 RW
TC7
TC6
TC5
TC4
TC3
TC2
TC1
TC0
00000001 RW
00000000 RW
FS1
FS0
00000000 RW
FIFO2FLAG 00000000 RW
xxxxxxxx W
FS1
FS0
00000000 RW
FIFO4FLAG 00000000 RW
xxxxxxxx W
FS1
FS0
00000000 RW
FIFO6FLAG 00000000 RW
xxxxxxxx W
FS1
FS0
00000000 RW
FIFO8FLAG 00000000 RW
xxxxxxxx W
D15
D14
D13
D12
D11
D10
D9
D8
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx R
INTRDY
SAS
TCXRDY5
00000000 bbbrrrrr
0
x
0
x
RDY5
x
RDY4
x
RDY3
x
RDY2
x
RDY1
x
RDY0
x
00xxxxxx R
xxxxxxxx W
D7
D7
D7
D6
D6
D6
D5
D5
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
D0
D0
D0
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
xxxxxxxx RW
xxxxxxxx RW
RW
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
D7
D6
D5
D4
D3
D2
D1
D0
xxxxxxxx RW
Page 36 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
80
81
82
83
84
85
86
87
88
1
1
1
1
1
1
1
1
1
89
8A
8B
8C
8D
8E
8F
90
91
92
1
1
1
1
1
1
1
1
1
93
98
5
1
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A8
1
1
1
1
1
1
1
1
1
1
5
1
A9
AA
1
1
AB
AC
AD
AF
B0
B1
2
1
1
1
B2
B3
B4
B5
B6
B7
B8
1
1
1
1
1
1
1
B9
BA
BB
1
1
1
BC
BD
1
1
Description
b7
b6
DISCON
b5
0
b4
0
b3
0
b2
0
b1
b0
400KHZ
Default Access
xxxxxxxx n/a
D7
D7
A7
A15
A7
A15
0
SMOD0
TF1
D6
D6
A6
A14
A6
A14
0
x
TR1
D5
D5
A5
A13
A5
A13
0
1
TF0
D4
D4
A4
A12
A4
A12
0
1
TR0
D3
D3
A3
A11
A3
A11
0
x
IE1
D2
D2
A2
A10
A2
A10
0
x
IT1
D1
D1
A1
A9
A1
A9
0
x
IE0
D0
D0
A0
A8
A0
A8
SEL
IDLE
IT0
xxxxxxxx
00000111
00000000
00000000
00000000
00000000
00000000
00110000
00000000
GATE
CT
M1
M0
GATE
CT
M1
M0
00000000 RW
D7
D7
D15
D15
x
D6
D6
D14
D14
x
D5
D5
D13
D13
T2M
D4
D4
D12
D12
T1M
D3
D3
D11
D11
T0M
D2
D2
D10
D10
MD2
D1
D1
D9
D9
MD1
D0
D0
D8
D8
MD0
00000000
00000000
00000000
00000000
00000001
D7
IE5
A15
D6
IE4
A14
D5
ICINT
A13
D4
USBNT
A12
D3
1
A11
D2
0
A10
D1
0
A9
D0
0
A8
xxxxxxxx RW
00001000 RW
00000000 RW
SM0_0
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
00000000 RW
D7
A15
A7
D6
A14
A6
D5
A13
A5
D4
A12
A4
D3
A11
A3
D2
A10
A2
D1
A9
A1
D0
A8
A0
00000000 RW
00000000 RW
00000000 RW
A15
A7
A14
A6
A13
A5
A12
A4
A11
A3
A10
A2
A9
A1
A8
A0
00000000 RW
00000000 RW
D7
x
x
D6
x
x
D5
x
x
D4
x
x
D3
x
x
D2
x
x
D1
x
x
D0
x
x
xxxxxxxx RW
xxxxxxxx W
xxxxxxxx W
EA
ES1
ET2
ES0
ET1
EX1
ET0
EX0
00000000 RW
EP8F
EP8E
EP6F
EP6E
EP4F
EP4E
EP2F
EP2E
01011010 R
EP4PF
EP4EF
EP4FF
EP2PF
EP2EF
EP2FF
00100010 R
EP8PF
EP8EF
EP8FF
EP6PF
EP6EF
EP6FF
01100110 R
0
D7
D7
0
D6
D6
0
D5
D5
0
D4
D4
0
D3
D3
APTR2INC
D2
D2
APTR1INC
D1
D1
APTREN
D0
D0
00000110 RW
xxxxxxxx RW
xxxxxxxx RW
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
00000000
00000000
00000000
00000000
00000000
PS1
PT2
PS0
PT1
PX1
PT0
PX0
10000000 RW
0
DONE
0
0
0
0
0
0
0
0
EP1INBSY
RW
EP1OUTBSY EP0BSY
EP1
EP0
00000000 R
10000xxx brrrrbbb
D15
D14
D13
D12
D11
D10
D9
xxxxxxxx RW
D8
[16]
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Notes
15. SFRs not part of the standard 8051 architecture.
16. If no EEPROM is detected by the SIE then the default is 00000000.
Page 37 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
1
6
1
SBUF1[15]
reserved
T2CON
C9
CA
1
1
reserved
RCAP2L
CB
RCAP2H
CC
CD
CE
D0
1
1
2
1
TL2
TH2
reserved
PSW
D1
D8
D9
E0
7
1
7
1
reserved
EICON[15]
reserved
ACC
E1
E8
7
1
reserved
EIE[15]
E9
F0
F1
F8
7
1
7
1
reserved
B
reserved
EIP[15]
F9
reserved
Description
GPIF Data L w/ Trigger
D7
GPIF Data L w/ No Trigger D7
b7
D6
D6
b6
D5
D5
b5
D4
D4
b4
D3
D3
b3
D2
D2
b2
D1
D1
b1
D0
D0
b0
Default Access
xxxxxxxx RW
xxxxxxxx R
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00000000 RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000 RW
Timer/Counter 2 Control
(bit addressable)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
CT2
CPRL2
00000000 RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000 RW
D7
D6
D5
D4
D3
D2
D1
D0
00000000 RW
D7
D15
D6
D14
D5
D13
D4
D12
D3
D11
D2
D10
D1
D9
D0
D8
00000000 RW
00000000 RW
AC
F0
RS1
RS0
OV
F1
00000000 RW
ERESI
RESI
INT6
01000000 RW
D6
D5
D4
D3
D2
D1
D0
00000000 RW
EX6
EX5
EX4
EIC
EUSB
11100000 RW
B (bit addressable)
D7
D6
D5
D4
D3
D2
D1
D0
00000000 RW
PX6
PX5
PX4
PIC
PUSB
11100000 RW
Page 38 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
6. Operating Conditions
7. Thermal Characteristics
The following table displays the thermal characteristics of various packages:
Table 12. Thermal Characteristics
Package
Ambient
Temperature (C)
Jc
Junction to Case
Thermal Resistance (C/W)
Ja
Junction to Ambient Thermal
Resistance (C/W)
56 SSOP
70
24.4
47.7
100 TQFP
70
11.9
45.9
128 TQFP
70
15.5
43.2
56 QFN
70
10.6
25.2
56 VFBGA
70
30.9
58.6
The junction temperature j, can be calculated using the following equation: j = P*Ja + a
Where,
P = Power
Ja = Junction to ambient temperature (Jc + Ca)
a = Ambient temperature (70 C)
The case temperature c, can be calculated using the following equation: c = P*Ca + a
where,
P = Power
Ca = Case to ambient temperature
a = Ambient temperature (70 C)
Note
17. Do not power I/O with the chip power OFF.
Page 39 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
8. DC Characteristics
Table 13. DC Characteristics
Parameter
VCC
Description
Supply voltage
Min
Typ
Max
Unit
Conditions
3.00
3.3
3.60
200
VIH
5.25
VIL
0.5
0.8
VIH_X
5.25
VIL_X
0.5
0.8
II
10
VOH
IOUT = 4 mA
2.4
VOL
IOUT = 4 mA
0.4
IOH
mA
IOL
mA
CIN
ISUSP
ICC
TRESET
Except D+/D
10
pF
D+/D
15
pF
Suspend current
Connected
300
380[18]
CY7C68014/CY7C68016
Disconnected
100
150[18]
A
mA
Suspend current
Connected
0.5
1.2[18]
CY7C68013/CY7C68015
Disconnected
0.3
1.0[18]
mA
Supply current
50
85
mA
35
65
mA
5.0
ms
200
Note
18. Measured at Max VCC, 25 C.
Page 40 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9. AC Electrical Characteristics
9.1 USB Transceiver
USB 2.0 compliant in Full-Speed and Hi-Speed modes.
CLKOUT[19]
tAV
tAV
A[15..0]
tSTBH
tSTBL
PSEN#
[20]
tACC1
D[7..0]
tDH
data in
tSOEL
OE#
tSCSL
CS#
Description
1/CLKOUT frequency
Min
Typ
Max
Unit
Notes
20.83
ns
48 MHz
41.66
ns
24 MHz
83.2
ns
12 MHz
tAV
10.7
ns
tSTBL
ns
tSTBH
ns
tSOEL
Clock to OE LOW
11.1
ns
tSCSL
Clock to CS LOW
13
ns
tDSU
tDH
9.6
ns
ns
Notes
19. CLKOUT is shown with positive polarity.
20. tACC1 is computed from these parameters as follows:
tACC1(24 MHz) = 3*tCL tAV tDSU = 106 ns.
tACC1(48 MHz) = 3*tCL tAV tDSU = 43 ns.
Page 41 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.3 Data Memory Read[21]
Figure 9-2. Data Memory Read Timing Diagram
tCL
Stretch = 0
CLKOUT[19]
tAV
tAV
A[15..0]
tSTBH
tSTBL
RD#
tSCSL
CS#
tSOEL
OE#
[22]
tDSU
tDH
tACC2
D[7..0]
data in
tCL
Stretch = 1
CLKOUT[19]
tAV
A[15..0]
RD#
CS#
tDSU
tACC3 [22]
D[7..0]
tDH
data in
Description
1/CLKOUT frequency
Min
Typ
Max
Unit
Notes
20.83
ns
48 MHz
41.66
ns
24 MHz
83.2
ns
12 MHz
10.7
ns
tAV
tSTBL
Clock to RD LOW
11
ns
tSTBH
Clock to RD HIGH
11
ns
tSCSL
Clock to CS LOW
13
ns
tSOEL
Clock to OE LOW
11.1
ns
tDSU
9.6
ns
tDH
ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either
RD# or WR# is active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is
based on the stretch value.
Notes
21. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including
typical strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual. The address cycle width can be interpreted from these.
22. tACC2 and tACC3 are computed from these parameters as follows:
tACC2(24 MHz) = 3*tCL tAV tDSU = 106 ns
tACC2(48 MHz) = 3*tCL tAV tDSU = 43 ns
tACC3(24 MHz) = 5*tCL tAV tDSU = 190 ns
tACC3(48 MHz) = 5*tCL tAV tDSU = 86 ns
Page 42 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
9.4 Data Memory Write[23]
Figure 9-3. Data Memory Write Timing Diagram
tCL
CLKOUT
tAV
tSTBL
tSTBH
tAV
A[15..0]
WR#
tSCSL
CS#
tON1
tOFF1
data out
D[7..0]
Stretch = 1
tCL
CLKOUT
tAV
A[15..0]
WR#
CS#
tON1
tOFF1
data out
D[7..0]
Max
Unit
Notes
tAV
Parameter
Description
10.7
ns
tSTBL
11.2
ns
tSTBH
11.2
ns
tSCSL
13.0
ns
tON1
13.1
ns
tOFF1
13.1
ns
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the address valid time for which is based on
the stretch value.
Note
23. The stretch memory cycle feature enables EZ-USB firmware to adjust the speed of data memory accesses not the program memory accesses. Details including
typical strobe width timings can be found in the section 12.1.2 of the Technical Reference Manual. The address cycle width can be interpreted from these.
Page 43 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
The RD# signal prompts the external logic to prepare the next
data byte. Nothing gets sampled internally on assertion of the
RD# signal itself; it is just a prefetch type signal to get the next
data byte prepared. So, using it with that in mind easily meets the
setup time to the next read.
The RD# and WR# strobes are asserted for two CLKOUT cycles
when PORTC is accessed.
CLKOUT
PORTC IS UPDATED
tSTBL
tSTBH
WR#
CLKOUT
tSTBH
RD#
Page 44 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
RDYX
tSRY
tRYH
DATA(input)
valid
tSGD
tDAH
CTLX
tXCTL
DATA(output)
N+1
tXGD
Table 17. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK[24, 25]
Parameter
tIFCLK
tSRY
tRYH
tSGD
tDAH
tSGA
tXGD
tXCTL
tIFCLKR
tIFCLKF
tIFCLKOD
tIFCLKJ
Description
IFCLK Period
RDYX to clock setup time
Clock to RDYX
GPIF data to clock setup time
GPIF data hold time
Clock to GPIF address propagation delay
Clock to GPIF data output propagation delay
Clock to CTLX output propagation delay
IFCLK rise time
IFCLK fall time
IFCLK output duty cycle
IFCLK jitter peak to peak
Min
Max
20.83
8.9
0
9.2
0
7.5
11
6.7
Typ
Min
49
Max
900
900
51
300
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
%
ps
Table 18. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK[25]
Parameter
tIFCLK
tSRY
tRYH
tSGD
tDAH
tSGA
tXGD
tXCTL
Description
IFCLK period[26]
RDYX to clock setup time
Clock to RDYX
GPIF data to clock setup time
GPIF data hold time
Clock to GPIF address propagation delay
Clock to GPIF data output propagation delay
Clock to CTLX output propagation delay
Min
20.83
2.9
3.7
3.2
4.5
Max
200
11.5
15
10.7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
24. Dashed lines denote signals with programmable polarity.
25. GPIF asynchronous RDYx signals have a minimum setup time of 50 ns when using the internal 48-MHz IFCLK.
26. IFCLK must not exceed 48 MHz.
Page 45 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
IFCLK
tSRD
tRDH
SLRD
tXFLG
FLAGS
DATA
N+1
N
tOEon
tXFD
tOEoff
SLOE
Table 19. Slave FIFO Synchronous Read Parameters with Internally Sourced IFCLK[25]
Parameter
Description
Min
Max
Typ
Min
Max
Unit
tIFCLK
IFCLK period
20.83
ns
tSRD
18.7
ns
tRDH
ns
tOEon
10.5
ns
tOEoff
10.5
ns
tXFLG
9.5
ns
tXFD
11
ns
tIFCLKR
900
ps
tIFCLKF
900
ps
tIFCLKOD
49
51
tIFCLKJ
300
ps
Page 46 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Table 20. Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK[25]
Min
Max
Unit
tIFCLK
Parameter
IFCLK period
Description
20.83
200
ns
tSRD
12.7
ns
tRDH
3.7
ns
tOEon
10.5
ns
tOEoff
10.5
ns
tXFLG
13.5
ns
tXFD
15
ns
tRDpwl
FLAGS
tXFD
tXFLG
DATA
N+1
tOEon
tOEoff
SLOE
Max
Unit
tRDpwl
Parameter
Description
50
ns
tRDpwh
50
ns
tXFLG
70
ns
tXFD
15
ns
tOEon
10.5
ns
tOEoff
10.5
ns
Note
27. Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz.
Page 47 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
SLWR
DATA
tSWR
tWRH
Z
tSFD
tFDH
FLAGS
tXFLG
Table 22. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[25]
Min
Max
Unit
tIFCLK
Parameter
IFCLK period
Description
20.83
ns
tSWR
10.4
ns
tWRH
ns
tSFD
9.2
ns
tFDH
ns
tXFLG
9.5
ns
Table 23. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[25]
Min
Max
Unit
tIFCLK
Parameter
IFCLK Period
Description
20.83
200
ns
tSWR
12.1
ns
tWRH
3.6
ns
tSFD
3.2
ns
tFDH
4.5
ns
tXFLG
13.5
ns
Page 48 of 71
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CY7C68015A, CY7C68016A
tWRpwl
tSFD
tFDH
DATA
tXFD
FLAGS
Table 24. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK [27]
Min
Max
Unit
tWRpwl
Parameter
SLWR pulse LOW
Description
50
ns
tWRpwh
70
ns
tSFD
10
ns
tFDH
10
ns
tXFD
70
ns
IFCLK
tPEH
PKTEND
tSPE
FLAGS
tXFLG
Table 25. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK[25]
Min
Max
Unit
tIFCLK
Parameter
IFCLK period
Description
20.83
ns
tSPE
14.6
ns
tPEH
ns
tXFLG
9.5
ns
Table 26. Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK[25]
Parameter
Description
Min
Max
Unit
tIFCLK
IFCLK period
20.83
200
ns
tSPE
8.6
ns
tPEH
2.5
ns
tXFLG
13.5
ns
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CY7C68015A, CY7C68016A
caused the last byte or word to be clocked into the previous auto
committed packet. Figure 9-12 shows this scenario. X is the
value the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Note that there is at least one IFCLK cycle timing between the
assertion of PKTEND and clocking of the last byte of the previous
packet (causing the packet to be committed automatically).
Failing to adhere to this timing results in the FX2 failing to send
the one byte or word short packet.
Figure 9-12. Slave FIFO Synchronous Write Sequence and Timing Diagram[24]
tIFCLK
IFCLK
tSFA
tFAH
FIFOADR
>= tWRH
>= tSWR
SLWR
tFDH
tSFD
DATA
tSFD
X-4
tFDH
tFDH
tSFD
X-3
tFDH
tSFD
X-2
tSFD
X-1
tFDH
tSFD
tFDH
tSPE
tPEH
PKTEND
tPEpwl
FLAGS
tXFLG
Description
Min
Max
Unit
tPEpwl
50
ns
tPWpwh
50
ns
tXFLG
115
ns
Page 50 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
tOEon
DATA
Unit
tOEon
Parameter
Description
Min
10.5
ns
tOEoff
10.5
ns
N+1
Description
Min
Max
Unit
tXFLG
10.7
ns
tXFD
14.3
ns
SLCS/FIFOADR [1:0]
tSFA
tFAH
Description
Min
Max
Unit
20.83
200
ns
tIFCLK
tSFA
25
ns
tFAH
10
ns
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CY7C68015A, CY7C68016A
tSFA
SLRD/SLWR/PKTEND
Max
Unit
tSFA
Parameter
Description
10
ns
tFAH
10
ns
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSRD
T=0
tRDH
>= tSRD
>= tRDH
SLRD
t=3
t=2
T=3
T=2
SLCS
tXFLG
FLAGS
tXFD
tXFD
Data Driven: N
DATA
N+1
N+1
N+2
N+3
tOEon
tOEoff
tOEon
tXFD
tXFD
N+4
tOEoff
SLOE
t=4
T=4
T=1
t=1
FIFO POINTER
IFCLK
IFCLK
N+1
Driven: N
N+1
SLOE
SLRD
SLRD
SLOE
N+1
IFCLK
IFCLK
N+1
IFCLK
N+3
IFCLK
N+4
SLRD
SLOE
Not Driven
IFCLK
N+2
N+1
IFCLK
N+4
SLRD
N+2
N+3
N+4
IFCLK
N+4
SLOE
N+4
Not Driven
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CY7C68015A, CY7C68016A
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
Note For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is on
the data bus. During the first read cycle, on the rising edge of the
clock, the FIFO pointer is updated and incremented to point to
address N+1. For each subsequent rising edge of IFCLK, while
the SLRD is asserted, the FIFO pointer is incremented and the
next data value is placed on the data bus.
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSWR
tWRH
>= tWRH
>= tSWR
T=0
SLWR
t=2
T=2
t=3
T=5
SLCS
tXFLG
tXFLG
FLAGS
tFDH
tSFD
tSFD
N+1
DATA
t=1
tFDH
T=1
tSFD
tSFD
tFDH
N+3
N+2
T=3
tFDH
T=4
tSPE
tPEH
PKTEND
Page 53 of 71
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CY7C68015A, CY7C68016A
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5.
Note For the burst mode, SLWR and SLCS are left asserted for
the entire duration of writing all the required data values. In this
burst write mode, after the SLWR is asserted, the data on the
FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 9-20, after the four bytes are written to the
FIFO, SLWR is deasserted. The short 4 byte packet can be
committed to the host by asserting the PKTEND signal.
Page 54 of 71
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CY7C68015A, CY7C68016A
9.17.3 Sequence Diagram of a Single and Burst Asynchronous Read
Figure 9-21. Slave FIFO Asynchronous Read Sequence and Timing Diagram[24]
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tRDpwl
tRDpwh
tRDpwl
T=0
tRDpwl
tRDpwh
tRDpwl
tRDpwh
tRDpwh
SLRD
t=2
t=3
T=3
T=2
T=5
T=4
T=6
SLCS
tXFLG
tXFLG
FLAGS
tXFD
Data (X)
Driven
DATA
tXFD
tXFD
N
N+3
N+2
tOEon
tOEoff
tOEon
tXFD
N+1
tOEoff
SLOE
t=4
t=1
T=7
T=1
FIFO POINTER
SLRD
SLRD
SLOE
SLOE
SLRD
SLRD
SLRD
SLRD
SLOE
N+1
N+1
N+1
N+1
N+2
N+2
N+3
N+3
Driven: X
Not Driven
N+1
N+1
N+2
N+2
Not Driven
Note In the burst read mode, during SLOE is asserted, the data
bus is in a driven state and outputs the previous data. After SLRD
is asserted, the data from the FIFO is driven on the data bus
(SLOE must also be asserted) and then the FIFO pointer is
incremented.
Page 55 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
tFAH
tSFA
tFAH
FIFOADR
t=0
tWRpwl
tWRpwh
T=0
tWRpwl
tWRpwl
tWRpwh
tWRpwl
tWRpwh
tWRpwh
SLWR
t=3
t =1
T=1
T=3
T=4
T=6
T=7
T=9
SLCS
tXFLG
tXFLG
FLAGS
tSFD tFDH
tSFD tFDH
tSFD tFDH
tSFD tFDH
N+1
N+2
N+3
DATA
t=2
T=2
T=5
T=8
tPEpwl
tPEpwh
PKTEND
Page 56 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Package Type
RAM Size
Address
# Prog I/Os 8051
/Data Bus
Serial Debug[28]
16 K
40
16-/8-bit
CY7C68014A-100AXC
16 K
40
CY7C68014A-56PVXC
56 SSOP Pb-free
16 K
24
CY7C68014A-56LTXC
56 QFN - Pb-free
16 K
24
CY7C68016A-56LTXC
56 QFN - Pb-free
16 K
26
CY7C68016A-56LTXCT
56 QFN - Pb-free
16 K
26
16 K
40
16-/8-bit
CY7C68013A-128AXI
16 K
40
16-/8-bit
CY7C68013A-100AXC
16 K
40
CY7C68013A-100AXI
16 K
40
CY7C68013A-56PVXC
56 SSOP Pb-free
16 K
24
CY7C68013A-56PVXCT
56 SSOP Pb-free
16 K
24
CY7C68013A-56PVXI
16 K
24
CY7C68013A-56BAXC
56 VFBGA Pb-free
16 K
24
CY7C68013A-56BAXCT
56 VFBGA Pb-free
16 K
24
CY7C68013A-56LTXC
56 QFN Pb-free
16 K
24
CY7C68013A-56LTXCT
56 QFN Pb-free
16 K
24
CY7C68013A-56LTXI
16 K
24
CY7C68015A-56LTXC
56 QFN Pb-free
16 K
26
Note
28. As UART is not available in the 56-pin package of CY7C68013A, serial port debugging using Keil Monitor is not possible.
Page 57 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Page 58 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
56-pin SSOP
56-pin QFN
100-pin TQFP
128-pin TQFP
56-ball VFBGA
Figure 11-1. 56-Pin Shrunk Small Outline Package O56 (51-85062)
51-85062 *F
Page 59 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
001-53450 *D
Page 60 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 11-3. 100-Pin Thin Plastic Quad Flatpack (14 20 1.4 mm) A100RA (51-85050)
51-85050 *E
Page 61 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 11-4. 128-Pin Thin Plastic Quad Flatpack (14 20 1.4 mm) A128 (51-85101)
51-85101 *F
Page 62 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Figure 11-5. 56-Pin VFBGA (5 5 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 (001-03901)
001-03901 *E
Page 63 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
Note
29. Source for recommendations: EZ-USB FX2PCB Design Recommendations, http://www.cypress.com and High Speed USB Platform Design Guidelines,
http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.
Page 64 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Cu Fill
PCB Material
0.013 dia
PCB Material
Page 65 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Acronyms
Document Conventions
Units of Measure
Acronym
Description
Symbol
Unit of Measure
ASIC
kHz
kilohertz
ATA
mA
milliamperes
DID
device identifier
Mbps
DSL
MBPs
DSP
MHz
megahertz
ECC
uA
microamperes
EEPROM
volts
EPP
FIFO
GPIF
GPIO
I/O
input output
LAN
MPEG
PCMCIA
PID
product identifier
PLL
QFN
RAM
SIE
SOF
start of frame
SSOP
TQFP
USART
USB
UTOPIA
VFBGA
VID
vendor identifier
Page 66 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Errata
This section describes the errata for the EZ-USB FX2LP CY7C68013A/14A/15A/16A Rev. B silicon. Details include errata trigger
conditions, scope of impact, available workaround, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Package Type
Operating Range
CY7C68013A
All
Commercial
CY7C68014A
All
Commercial
CY7C68015A
All
Commercial
CY7C68016A
All
Commercial
CY7C68013A/14A/15A/16A
Silicon Revision
Fix Status
Problem Definition
In Slave FIFO Asynchronous Word Wide mode, if a single word data is transferred from the USB host to EP2, configured as OUT
Endpoint (EP) in the first transaction, then the Empty flag behaves incorrectly. This does not happen if the data size is more than
one word in the first transaction.
Parameters Affected
NA
Trigger Condition(S)
In Slave FIFO Asynchronous Word Wide Mode, after firmware boot and initialization, EP2 OUT endpoint empty flag indicates the
status as Empty. When data is received in EP2, the status changes to Not-Empty. However, if data transferred to EP2 is a single
word, then asserting SLRD with FIFOADR pointing to any other endpoint changes Not-Empty status to Empty for EP2 even
though there is a word data (or it is untouched). This is noticed only when the single word is sent as the first transaction and not if
it follows a multi-word packet as the first transaction.
Scope of Impact
External interface does not see data available in EP2 OUT endpoint and can end up waiting for data to be read.
Workaround
One of the following workarounds can be used:
Send a pulse signal to the SLWR pin, with FIFOADR pins pointing to an endpoint other than EP2, after firmware initialization
and before or after transferring the data to EP2 from the host
Set the length of the first data to EP2 to be more than a word
Prioritize EP2 read from the Master for multiple OUT EPs and single word write to EP2
Write to an IN EP, if any, from the Master before reading from other OUT EPs (other than EP2) from the Master.
Fix Status
There is no silicon fix planned for this currently; use the workarounds provided.
Page 67 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
124316
VCS
03/17/03
New datasheet
*A
128461
VCS
09/02/03
*B
130335
KKV
10/09/03
Restored PRELIMINARY to header (had been removed in error from rev. *A)
*C
131673
KKU
02/12/04
*D
230713
KKU
See ECN
Changed Lead free Marketing part numbers in Table 32 as per spec change in
28-00054.
*E
242398
TMD
See ECN
*F
271169
MON
See ECN
*G
316313
MON
See ECN
*H
338901
MON
See ECN
*I
371097
MON
See ECN
Added timing for strobing RD#/WR# signals when using PortC strobe feature
(Section 9.5)
*J
397239
MON
See ECN
Page 68 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*K
420505
MON
See ECN
*L
2064406
CMCC/PY
RS
See ECN
*M
2710327
DPT
05/22/2009
*N
2727334
ODC
07/01/09
*O
2756202
ODC
08/26/2009
*P
2785207
ODC
10/12/2009
*Q
2811890
ODC
11/20/2009
*R
2896281
ODC
03/19/10
Removed inactive parts from the ordering information table. Updated package
diagrams.Updated links in Sales, Solutions and Legal Information.
*S
3035980
ODC
09/22/10
Updated template.
Changed PPM requirement for the external crystal from +/- 10 ppm to +/- 100
ppm under Electrical specifications.
Added table of contents, ordering code definitions, acronym table, and units of
measure.
*T
3161410
AAE
02/03/2011
*U
3195232
ODC
03/14/2011
*V
3512313
GAYA
02/01/2012
Page 69 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
ECN No.
Orig. of
Change
Submission
Date
*W
3998554
GAYA
07/19/2013
Description of Change
Added Errata footnote (Note 3).
Updated Functional Overview:
Updated Interrupt System:
Updated FIFO/GPIF Interrupt (INT4):
Added Note 3 and referred the same note in Endpoint 2 empty flag in Table 4.
Updated Package Diagrams:
spec 51-85062 Changed revision from *E to *F.
spec 001-53450 Changed revision from *B to *C.
Added Errata.
Updated in new template.
*X
4617527
GAYA
01/15/2015
Page 70 of 71
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/go/plc
Memory
cypress.com/go/memory
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/support
cypress.com/go/touch
USB Controllers
Wireless/RF
Technical Support
cypress.com/go/USB
cypress.com/go/wireless
Cypress Semiconductor Corporation, 2003-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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