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Monolithic Op Amp
AD844
FUNCTIONAL BLOCK DIAGRAMS
Wide bandwidth
60 MHz at gain of 1
33 MHz at gain of 10
Slew rate: 2000 V/s
20 MHz full power bandwidth, 20 V p-p, RL = 500
Fast settling: 100 ns to 0.1% (10 V step)
Differential gain error: 0.03% at 4.4 MHz
Differential phase error: 0.16 at 4.4 MHz
Low offset voltage: 150 V maximum (B Grade)
Low quiescent current: 6.5 mA
Available in tape and reel in accordance with
EIA-481-A standard
NULL 1
+VS
+IN 3
OUTPUT
VS 4
TZ
NC 1
16 NC
OFFSETNULL 2
15 OFFSETNULL
IN 3
14 V+
NC 4
13 NC
+IN 5
12 OUTPUT
V 7
AD844
11 TZ
10 NC
TOP VIEW
NC 8 (Not to Scale) 9 NC
NC = NO CONNECT
00897-002
NC 6
PRODUCT HIGHLIGHTS
1.
3.
NULL
TOP VIEW
(Not to Scale)
APPLICATIONS
GENERAL DESCRIPTION
AD844
IN 2
00897-001
FEATURES
2.
4.
5.
6.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD844
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Specifications..................................................................................... 3
Noise ............................................................................................ 16
REVISION HISTORY
2/09Rev. E to Rev F
Updated Format .................................................................. Universal
Changes to Features Section............................................................ 1
Changes to Differential Phase Error Parameter, Table 1 ............. 3
Changes to Figure 13 ........................................................................ 8
Changes to Figure 18 ........................................................................ 9
Changes to Figure 23 and Figure 24 ............................................. 11
Changes to Figure 42 and High Speed DAC Buffer Section ..... 17
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
Rev. F | Page 2 of 20
AD844
SPECIFICATIONS
TA = 25C and VS = 15 V dc, unless otherwise noted.
Table 1.
Parameter
INPUT OFFSET VOLTAGE 1
TMIN to TMAX
vs. Temperature
vs. Supply
Initial
TMIN to TMAX
vs. Common Mode
Initial
TMIN to TMAX
INPUT BIAS CURRENT
Negative Input Bias Current1
TMIN to TMAX
vs. Temperature
vs. Supply
Initial
TMIN to TMAX
vs. Common Mode
Initial
TMIN to TMAX
Positive Input Bias Current1
TMIN to TMAX
vs. Temperature
vs. Supply
Initial
TMIN to TMAX
vs. Common Mode
Initial
TMIN to TMAX
INPUT CHARACTERISTICS
Input Resistance
Negative Input
Positive Input
Input Capacitance
Negative Input
Positive Input
Input Common-Mode Voltage
Range
INPUT VOLTAGE NOISE
INPUT CURRENT NOISE
Negative Input
Positive Input
OPEN-LOOP TRANSRESISTANCE
TMIN to TMAX
Transcapacitance
DIFFERENTIAL GAIN ERROR 2
DIFFERENTIAL PHASE ERROR2
Conditions
AD844J/AD844A
Min
Typ
Max
50
300
75
500
1
Min
AD844B
Typ
50
75
1
Max
150
200
5
Min
AD844S
Typ
50
125
1
Max
300
500
5
Unit
V
V
V/C
5 V to 18 V
4
4
20
4
4
10
10
4
4
20
20
V/V
V/V
10
10
35
10
10
20
20
10
10
35
35
V/V
V/V
200
800
9
450
1500
150
750
9
250
1100
15
200
1900
20
450
2500
30
nA
nA
nA/C
175
220
250
175
220
200
240
175
220
250
300
nA/V
nA/V
90
110
150
350
3
160
90
110
100
300
3
110
150
200
500
7
90
120
100
800
7
160
200
400
1300
15
nA/V
nA/V
nA
nA
nA/C
VCM = 10 V
5 V to 18 V
VCM = 10 V
400
700
5 V to 18 V
80
100
150
80
100
100
120
80
120
150
200
nA/V
nA/V
90
130
150
90
130
120
190
90
140
150
200
nA/V
nA/V
50
10
65
50
10
65
50
10
65
VCM = 10 V
2
2
10
2
2
10
2
2
pF
pF
V
10
f 1 kHz
nV/Hz
f 1 kHz
f 1 kHz
VOUT = 10 V
RL = 500
10
12
10
12
10
12
pV/Hz
pV/Hz
3.0
1.6
4.5
0.03
0.16
M
M
pF
%
Degree
f = 4.4 MHz
f = 4.4 MHz
2.2
1.3
3.0
2.0
4.5
0.03
0.16
Rev. F | Page 3 of 20
2.8
1.6
3.0
2.0
4.5
0.03
0.16
2.2
1.3
AD844
Parameter
FREQUENCY RESPONSE
Small Signal Bandwidth 3, 4
Gain = 1
Gain = 10
TOTAL HARMONIC DISTORTION
SETTLING TIME
10 V Output Step
Gain = 1, to 0.1%5
Gain = 10, to 0.1% 6
2 V Output Step
Gain = 1, to 0.1%5
Gain = 10, to 0.1%6
OUTPUT SLEW RATE
FULL POWER BANDWIDTH
VOUT = 20 V p-p5
VOUT = 2 V p-p5
OUTPUT CHARACTERISTICS
Voltage
Short-Circuit Current
TMIN to T MAX
Output Resistance
POWER SUPPLY
Operating Range
Quiescent Current
TMIN to TMAX
Conditions
AD844J/AD844A
Min
Typ
Max
f = 100 kHz,
2 V rms 5
Min
AD844B
Typ
Max
Min
AD844S
Typ
Max
Unit
60
33
0.005
60
33
0.005
60
33
0.005
MHz
MHz
%
100
100
100
100
100
100
ns
ns
110
100
2000
110
100
2000
110
100
2000
ns
ns
V/s
20
20
MHz
MHz
11
80
60
15
V
mA
mA
15 V supplies
5 V supplies
Overdriven
input
THD = 3%
VS = 15 V
VS = 5 V
1200
RL = 500
10
1200
20
20
Open loop
20
20
11
80
60
15
4.5
6.5
7.5
1200
10
18
7.5
8.5
4.5
Rev. F | Page 4 of 20
11
80
60
15
6.5
7.5
10
18
7.5
8.5
4.5
6.5
7.5
18
7.5
8.5
V
mA
mA
AD844
ABSOLUTE MAXIMUM RATINGS
METALLIZATION PHOTOGRAPH
Table 2.
Parameter
Supply Voltage
Power Dissipation1
Output Short-Circuit Duration
Input Common-Mode Voltage
Differential Input Voltage
Inverting Input Current
Continuous
Transient
Storage Temperature Range (Q)
Storage Temperature Range (N, RW)
Lead Temperature (Soldering, 60 sec)
ESD Rating
5 mA
10 mA
65C to +150C
65C to +125C
300C
1000 V
NULL
NULL
+VS
0.076
(1.9)
+IN
VS
TZ
0.095
(2.4)
SUBSTRATE CONNECTED TO +VS
ESD CAUTION
Rev. F | Page 5 of 20
OUTPUT
00897-003
Ratings
18 V
1.1 W
Indefinite
VS
6V
AD844
TYPICAL PERFORMANCE CHARACTERISTICS
20
60
15
70
50
40
10
15
20
10
15
20
10
00897-007
30
TA = 25C
00897-004
1V rms
RL = 500
TA = 25C
70
15
80
90
100
110
SECOND HARMONIC
10
10k
100k
00897-005
1k
10
15
20
00897-008
THIRD HARMONIC
130
100
140
00897-009
120
5
RL =
9
SUPPLY CURRENT (mA)
RL = 500
3
2
RL = 50
0
50
7
VS = 15V
6
VS = 5V
50
100
TEMPERATURE (C)
150
4
60
00897-006
TRANSRESISTANCE (M)
40
20
20
40
60
TEMPERATURE (-C)
80
100
120
Rev. F | Page 6 of 20
AD844
40
VS = 15V
IBP
1
IBN
50
100
150
TEMPERATURE (C)
Figure 10. Inverting Input Bias Current (IBN) and Noninverting Input Bias
Current (IBP) vs. Temperature
0.1
10M
100M
00897-011
OUTPUT IMPEDANCE ()
5V SUPPLIES
1M
20
20
40
60
80
100
120
140
FREQUENCY (Hz)
40
TEMPERATURE (-C)
10
100k
VS = 5V
20
10
60
100
0.01
10k
25
15
00897-010
2
50
30
00897-012
35
Rev. F | Page 7 of 20
AD844
INVERTING GAIN-OF-1 AC CHARACTERISTICS
+VS
0.22F
5V
4.7
100
R1
IN
R2
90
AD844
OUTPUT
+
RL
CL
10
0.22F
00897-013
VS
20ns
00897-016
4.7
500nV
R1 = R2 = 500
100
90
GAIN (dB)
R1 = R2 = 1k
6
12
10
18
1M
10M
100M
FREQUENCY (Hz)
00897-014
20ns
24
100k
R1 = R2 = 500
240
270
R1 = R2 = 1k
300
330
25
50
FREQUENCY (MHz)
00897-015
PHASE (Degrees)
210
Rev. F | Page 8 of 20
00897-017
AD844
INVERTING GAIN-OF-10 AC CHARACTERISTICS
180
+VS
210
500
PHASE (Degrees)
50
RL = 50
IN
AD844
OUTPUT
+
RL
CL
RL = 500
240
270
300
0.22F
00897-018
4.7
VS
330
25
FREQUENCY (MHz)
26
RL = 500
RL = 50
14
4
100k
1M
10M
FREQUENCY (Hz)
100M
00897-019
GAIN (dB)
20
Rev. F | Page 9 of 20
50
00897-020
0.22F
4.7
AD844
INVERTING GAIN-OF-10 PULSE RESPONSE
500nV
100
90
90
10
10
20ns
00897-021
100
20ns
00897-022
5V
Rev. F | Page 10 of 20
AD844
NONINVERTING GAIN-OF-10 AC CHARACTERISTICS
+VS
4.7
2V
0.22F
100ns
100
450
50
90
OUTPUT
AD844
+
IN
0.22F
RL
CL
00897-023
4.7
10
0
00897-026
VS
Figure 26. Noninverting Amplifier Large Signal Pulse Response, Gain = +10,
RL = 500
200nV
20
GAIN (dB)
RL = 50
50ns
100
RL = 500
90
14
10
1M
10M
100M
FREQUENCY (Hz)
180
210
RL = 500
240
270
300
330
25
FREQUENCY (MHz)
50
00897-025
PHASE (Degrees)
RL = 50
00897-027
4
100k
00897-024
Rev. F | Page 11 of 20
AD844
UNDERSTANDING THE AD844
RESPONSE AS AN INVERTING AMPLIFIER
OPEN-LOOP BEHAVIOR
Figure 28 shows a current feedback amplifier reduced to essentials. Sources of fixed dc errors, such as the inverting node bias
current and the offset voltage, are excluded from this model.
The most important parameter limiting the dc gain is the
transresistance, Rt, which is ideally infinite. A finite value of Rt
is analogous to the finite open-loop voltage gain in a conventional op amp.
+1
IIN
Ct
+1
IIN
00897-028
RIN
Rt
When R1 is fairly large (above 5 k) but still much less than Rt,
the closed-loop HF response is dominated by the time constant
R1 Ct. Under such conditions, the AD844 is overdamped and
provides only a fraction of its bandwidth potential. Because of
the absence of slew rate limitations under these conditions, the
circuit exhibits a simple single-pole response even under large
signal conditions.
In Figure 29, R3 is used to properly terminate the input if desired.
R3 in parallel with R2 gives the terminated resistance. As R1 is
lowered, the signal bandwidth increases, but the time constant
R1 Ct becomes comparable to higher order poles in the closedloop response. Therefore, the closed-loop response becomes
complex, and the pulse response shows overshoot. When R2
is much larger than the input resistance, RIN, at Pin 2, most of
the feedback current in R1 is delivered to this input, but as R2
becomes comparable to RIN, less of the feedback is absorbed at
Pin 2, resulting in a more heavily damped response. Consequently,
for low values of R2, it is possible to lower R1 without causing
instability in the closed-loop response. Table 3 lists combinations
of R1 and R2 and the resulting frequency response for the circuit
of Figure 29. Figure 16 shows the very clean and fast 10 V
pulse response of the AD844.
Rev. F | Page 12 of 20
R1
VIN
R3
OPTIONAL
R2
AD844
VOUT
RL
CL
00897-029
AD844
R1
R2
1 k
500
1 k
500
1 k
100
100
50
50
50
BW (MHz)
35
60
15
30
5.2
49
23
33
21
3.2
GBW (MHz)
35
60
30
60
26
245
230
330
420
320
VOUT = I sig
K R1
(1 + sTd ) (1 + sTn )
Rt
Rt + R1
VOUT
RL
CL
where:
K is a factor very close to unity and represents the finite dc gain
of the amplifier.
Td is the dominant pole.
Tn is the nuisance pole.
K=
AD844
CS
00897-030
Gain
1
1
2
2
5
5
10
10
20
100
ISIG
IB
+IN 3
2 IN
TZ 5
6 OUTPUT
Td = KR1Ct
4 VS
00897-031
IB
AD844
It is important to understand that the low input impedance at
the inverting input is locally generated and does not depend on
feedback. This is very different from the virtual ground of a
conventional operational amplifier used in the current summing
mode, which is essentially an open circuit until the loop settles.
In the AD844, transient current at the input does not cause
voltage spikes at the summing node while the amplifier is
settling. Furthermore, all of the transient current is delivered
to the slewing (TZ) node (Pin 5) via a short signal path (the
grounded base stages and the wideband current mirrors).
The current available to charge the capacitance (about 4.5 pF) at
the TZ node is always proportional to the input error current,
and the slew rate limitations associated with the large signal
response of the op amps do not occur. For this reason, the rise
and fall times are almost independent of signal level. In practice,
the input current eventually causes the mirrors to saturate.
When using 15 V supplies, this occurs at about 10 mA (or
2200 V/s). Because signal currents are rarely this large,
classical slew rate limitations are absent.
CPK
3nF
R1
499
20
VIN
AD844
RL
0.22F
4.7
00897-032
0.22F
R2
4.99
VS
Figure 32. Noninverting Amplifier Gain = 100, Optional Offset Trim Is Shown
46
VS = 15V
40
GAIN (dB)
VS = 5V
34
28
16
100k
1M
FREQUENCY (Hz)
10M
20M
00897-040
22
Rev. F | Page 14 of 20
AD844
USING THE AD844
BOARD LAYOUT
As with all high frequency circuits considerable care must be
used in the layout of the components surrounding the AD844.
A ground plane, to which the power supply decoupling capacitors are connected by the shortest possible leads, is essential to
achieving clean pulse response. Even a continuous ground plane
exhibits finite voltage drops between points on the plane, and
this must be kept in mind when selecting the grounding points.
In general, decoupling capacitors should be taken to a point
close to the load (or output connector) because the load
currents flow in these capacitors at high frequencies. The +IN
and IN circuits (for example, a termination resistor and Pin 3)
must be taken to a common point on the ground plane close to
the amplifier package.
AD844
VOUT
CL
750
22pF
00897-034
10
00897-035
500ns
INPUT IMPEDANCE
SETTLING TIME
Settling time is measured with the circuit of Figure 36. This
circuit employs a false summing node, clamped by the two
Schottky diodes, to create the error signal and limit the input
signal to the oscilloscope. For measuring settling time, the ratio
of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 k, and
RL = 500 . For the gain of 10, R5 = 50 , R6 = 500 , and RL
was not used because the summing network loads the output
with approximately 275 . Using this network in a unity-gain
configuration, settling time is 100 ns to 0.1% for a 5 V to +5 V
step with CL = 10 pF.
TO SCOPE
(TEK 7A11 FET PROBE)
R5
Capacitive drive capability is 100 pF without an external network. With the addition of the network shown in Figure 34,
the capacitive drive can be extended to over 10,000 pF, limited
by internal power dissipation. With capacitive loads, the output
speed becomes a function of the overdriven output current limit.
Because this is roughly 100 mA, under these conditions, the
maximum slew rate into a 1000 pF load is 100 V/s. Figure 35
shows the transient response of an inverting amplifier (R1 =
R2 = 1 k) using the feedforward network shown in Figure 34,
driving a load of 1000 pF.
R6
D1
D2
R1
VIN
R2
AD844
VOUT
R3
RL
NOTES
1. D1, D2 IN6263 OR EQUIVALENT SCHOTTKY DIODE.
Rev. F | Page 15 of 20
CL
00897-036
AD844
+5V
DC ERROR CALCULATION
2.2F
VIN
50
50
ZO = 50
VOUT
RL
50
2.2F
300
5V
00897-038
300
R1
VO = (I BP R P + VOS + I BN R IN )1 +
+ I BN R1
R2
Because IBN and IBP are unrelated both in sign and magnitude,
inserting a resistor in series with the noninverting input does
not necessarily reduce dc error and may actually increase it.
HP8753A
NETWORK
ANALYZER
RF OUT
IN
OUT
RF IN
EXT
TRIG
SYNC OUT
R1
OUT
HP11850C
SPLITTER
50
(TERMINATOR)
VIN
VIN
CIRCUIT
UNDER
TEST
VOUT
OUT
470
RIN
INN
IBN
00897-039
HP3314A
OUT
STAIRCASE
GENERATOR
VN
R2
0.3
AD844
00897-037
RP
IBP
Figure 37. Offset Voltage and Noise Model for the AD844
NOISE
Noise sources can be modeled in a manner similar to the dc bias
currents, but the noise sources are INN, INP, VN, and the amplifier
induced noise at the output, VON, is:
VON =
0.2
0.1
0.1
0.2
0.3
18
((I NP R P )2 + VN 2 )1 + R1 + (I NN R1)2
36
54
72
90
VOUT (IRE)
00897-040
INP
IRE = 7.14mV
R2
0.06
0.04
Rev. F | Page 16 of 20
0.02
0.02
0.04
0.06
18
36
54
72
VOUT (IRE)
90
00897-041
IRE = 7.14mV
AD844
+15V
DIGITAL
INPUTS
REFCOM 23
15V (VEE) 22
IBPO 21
IOUT 20
AD568 RL
0.22F*
0.22F*
0.22F*
AD844
ACOM 18
LCOM 17
SPAN 16
10
SPAN 15
11
THCOM 14
15V
19
12 LSB
0.22F*
VOUT
RI
ANALOG
SUPPLY
GROUND
GROUND
DIGITAL
SUPPLY
100pF
VTH 13
5V
00897-042
TOP VIEW
(Not to Scale)
*POWER SUPPLY BYPASS CAPACITORS.
The AD844 performs very well in applications requiring currentto-voltage conversion. Figure 42 shows connections for use with
the AD568 current output DAC. In this application, the bipolar
offset is used so that the full-scale current is 5.12 mA, which
generates an output of 5.12 V using the 1 k application resistor
on the AD568. Figure 43 shows the full-scale transient response.
Care is needed in power supply decoupling and grounding
techniques to achieve the full 12-bit accuracy and realize the
fast settling capabilities of the system. The AD568 data sheet
should be consulted for more complete details about its use.
VW =
VXVY
2V
(1)
100
90
10
10
50ns
00897-043
INPUTS
VX*
0V TO 3V
VY*
2V FS
3nF
INPUT
GND
0.22F
+VS
TYP +6V
AT 15A
10
0.22F
0.22F
16
15
14
3
4
AD539
TOP VIEW
5 (Not to Scale) 12
6
11
10
AD844
13
3
OUTPUT
VW
VW =
0.22F
VXVY
2V
10
10
Rev. F | Page 17 of 20
VS
TYP 6V
AT 15A
00897-044
2V
AD844
4
VX = 3.15V
6
VX = 1.0V
16
GAIN (dB)
VX = 0.316V
26
VX = 0.10V
36
VX = 0.032V
56
100k
1M
10M
60M
FREQUENCY (Hz)
1V
50ns
100
90
10
00897-046
Rev. F | Page 18 of 20
00897-045
46
AD844
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.005 (0.13)
MIN
8
0.055 (1.40)
MAX
5
0.310 (7.87)
0.220 (5.59)
1
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
SEATING
PLANE
15
0
0.015 (0.38)
0.008 (0.20)
Rev. F | Page 19 of 20
070606-A
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
AD844
10.50 (0.4134)
10.10 (0.3976)
16
7.60 (0.2992)
7.40 (0.2913)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
45
8
0
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
032707-B
ORDERING GUIDE
Model
AD844AN
AD844ANZ 1
AD844ACHIPS
AD844AQ
AD844BQ
AD844JR-16
AD844JR-16-REEL
AD844JR-16-REEL7
AD844JRZ-161
AD844JRZ-16-REEL1
AD844JRZ-16-REEL71
AD844SCHIPS
AD844SQ
AD844SQ/883B
5962-8964401PA 2
1
2
Temperature Range
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
0C to 70C
55C to +125C
55C to +125C
55C to +125C
55C to +125C
Package Description
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Plastic Dual In-Line Package [PDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead SOIC_W, 13 Tape and Reel
16-Lead SOIC_W, 7 Tape and Reel
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead SOIC_W, 13 Tape and Reel
16-Lead SOIC_W, 7 Tape and Reel
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
8-Lead Ceramic Dual In-Line Package [CERDIP]
Rev. F | Page 20 of 20
Package Option
N-8
N-8
Die
Q-8
Q-8
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
Die
Q-8
Q-8
Q-8