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Mahdi Shabany
Electrical Engineering Department
Sharif University of Technology
)( )
The DCT-2D is computed as follows: first, the image data is divided into non-overlapped 8*8 matrix
blocks; second, all of the 8*8 matrix blocks are transformed by the two dimensional Discrete Cosine
Transform, which is given by the following equation.
The result of this equation is an 8*8 matrix representing the frequency domain of the pixel values in the
original 8*8 block. Most of the image data will be retained in only a portion of the matrix.
Quantization
Quantization is used to allow for a better compression ration, the quantization is the operation that
introduces information losses in the JPEG compression process. The goal of the quantization step is to
generate a sparse matrix to allow a large compression rate at the entropy coding operation.
Quantization is defined as division of each DCT coefficient by the corresponding quantization value
S(u,v) , followed by rounding to the nearest integer, which is given by equation [4]
(
The matrix of
is represented as follows:
[
Where [...] represents truncation to integer value. So the DCT coefficient is actually multiplied by 5041
which is stored in the proposed implementation as the corresponding quantization value and then the
least significant 16 bits are discarded by a shift operation.
Afterwards, the remaining values in the matrix are called as the AC coefficients. These values are
encoded slightly differently using an 8-bit value represented as RRRRSSSS. The run-length, 4 bits RRRR
value, is the number of zeros preceding a non-zero value using the zigzag format of reading the matrix.
The non-zero value is then coded by size, 4 bits SSSS value, as is described for the difference magnitude.
Finally, all of the DC coefficient and the AC coefficients should be coded by Huffman code. While
considering that this is not focus in our research, so it will not be described particularly in this paper.
Your Tasks
You are highly recommended to study the relevant papers available in WEB. Your design should be real
time, so use the technics discussed in class.
You should simulate this system in MATLAB, then you should design and implement a hardware for
complete system, this part should be done by ISE (over VIRTEX 6), although you should write a testbench
and design a test strategy using matlab outputs and ModelSim.
The verified design should be synthesized by Design Compiler and the ASIC flow should be completely
done (using DC and SoC encounter).
All the parts should be documented and be delivered according to this timeline:
MATAB simulation and RTL design and hardware
implementation of YCbCr and DCT and
Quntization
MATAB simulation and RTL design and hardware
implementation zig-zag and entropy coding
The complete ASIC Flow
Preparing the final report
16 ordibehesht
30 ordibehesht
13 khordad
20 khordad
References
1. Multiplierless and fully pipelined JPEG compression soft IP targeting FPGAs
2. A Novel Parallel JPEG Compression System Based on FPGA