(When) Will FPGAs Kill

ASICs?
Rajeev Jayaraman
Xilinx Inc.
DAC-2001
1

FPGAs vs. ASICs

Cost the real story.
Time to market
Why choose ASICs?
Where are FPGAs going?

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Unit Cost Analysis

Total cost
FPGA .25

FPGA .15

ASIC .15
ASIC Costs
Start higher,
but slope is flatter

ASIC .25

For each technology advance,

crossover volume moves higher
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Volume K units

$4,000,000
$3,000,000
$2,000,000
$1,000,000

0.35

0.25

0.2

0.15

0.1

Process Geometry (Micron)

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$0
0.05

NRE and Mask Costs

Cost: The exploding ASIC NRE

Source: Dataquest

Time to market is critical

Revenue

Potential profit if you

come early to the market

FPGA

Long time to market is a cost

What you get if you

design with an ASIC
and come late to the market

ASIC
Start of market window

Time

End of market

Missing the market window will wipe out all savings from
development and production
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COST: System Reconfigurability

Revenue

Without reconfigurability
(with ASICs)

Extend the market window

with reconfigurability
(with FPGAs)

Time
Lack of reconfigurability is a huge opportunity cost of ASICs
FPGAs offer flexible life cycle management
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Breakeven Cost: Just the facts

ASIC

Total cost
Time-to-market

Re-spins & Inventory

Unit cost

Volume K units
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Time To Market: Design Cycle

ASIC
Spec

FPGA

Iterations?

Freeze design
Design & verification

Silicon
Prototype

System
Integration

Freeze design

Spec Design and

verification

System
Integration

Production

First
Ship

ASIC Methodology is very unforgiving

FPGA flexibility allows late design changes
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Production

First
Ship

Designing with ASICs

DSM
Effects

Verification

Process
issues

Timing Closure is a very serious problem in DSM

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Designing with FPGAs

DSM
Effects

Process
issues

Verification
is much simpler

Super fast compile times

~1M gates in < 1hr

Timing Closure is a much simpler problem in FPGAs

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Why do people design ASICs?

Cost/Volume
Cost/Volume

Density
Density

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Performance
Performance

IP
IPLibraries
Libraries

Volume requirement for ASICs

Cost
Cost
Density
Density
Performance
Performance
IPIPLibraries
Libraries
45.9

48.1

<100K
100-250K
>250K
Source: IMS 2000

>50% of market is available today for FPGAs

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Gate count requirement for ASICs

Cost
Cost
Density
Density
Performance
Performance
IPIPLibraries
Libraries

20

<3M
3-5M
>5M
Source: IMS 2000

73

FPGAs can address very large part of the ASIC market today
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Performance requirement for ASICs

Cost
Cost
Density
Density

10.8

Performance
Performance
IPIPLibraries
Libraries
53.9
38.5

<100Mhz
100-200Mhz
>200Mhz
Source: IMS 2000

FPGAs can address very large part of the ASIC market today
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IP in FPGAs

Cost
Cost
Density
Density

5 Years ago FPGAs were

only gates and routing
~25000 gates

Performance
Performance
IPIPLibraries
Libraries

Multiple I/O Standards

Clock management FIFO/CAM
RAM
Processors
Multipliers
High Speed I/O: LVDS, Gigabit
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Today, there are several

system-level features.
~10,000,000 gates
The trend to add more IP in
FPGAs continues

The Question is
The question is not if FPGAs will kill ASICs
Everyone understands the advantages of
programmability
The real question is How can I get programmability
in my system?
More IP on an FPGA or Progammability on an
ASIC?

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What is the future? You decide

More IP on FPGA

More Prog. On ASIC

Time-to-market Verification remains simple

Timing closure is easier

Verification remains a problem

Timing closure remains an
issue

Cost

NRE is non-existent
Extensive reconfigurability

NRE not reduced

Very limited reconfigurability

Design
methodology/
Software

Simple methodology
Ease of use
Extremely fast SW runtimes

Still a complex methodology

Ease of use is still lacking

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